23 files changed, 36556 insertions, 33372 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index d1ad31617..4fcd96b8e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.884241                       # Number of seconds simulated
-sim_ticks                                1884241273000                       # Number of ticks simulated
-final_tick                               1884241273000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.884236                       # Number of seconds simulated
+sim_ticks                                1884235597000                       # Number of ticks simulated
+final_tick                               1884235597000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 193195                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193195                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6486085343                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317148                       # Number of bytes of host memory used
-host_seconds                                   290.51                       # Real time elapsed on the host
-sim_insts                                    56124126                       # Number of instructions simulated
-sim_ops                                      56124126                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 284222                       # Simulator instruction rate (inst/s)
+host_op_rate                                   284222                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9542341098                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 373416                       # Number of bytes of host memory used
+host_seconds                                   197.46                       # Real time elapsed on the host
+sim_insts                                    56122640                       # Number of instructions simulated
+sim_ops                                      56122640                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          25914944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          25914816                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25915904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1052928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1052928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7561408                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7561408                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             404921                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25915776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1053184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1053184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7561856                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7561856                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             404919                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404936                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118147                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118147                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             13753517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                404934                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118154                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118154                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             13753490                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13754026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          558807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             558807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4012972                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4012972                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4012972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            13753517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13754000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          558945                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             558945                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4013222                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4013222                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4013222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            13753490                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17766999                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404936                       # Number of read requests accepted
-system.physmem.writeReqs                       159699                       # Number of write requests accepted
-system.physmem.readBursts                      404936                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     159699                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25909568                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6336                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10083392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25915904                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10220736                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       99                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2126                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            153                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25482                       # Per bank write bursts
+system.physmem.bw_total::total               17767222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404934                       # Number of read requests accepted
+system.physmem.writeReqs                       159706                       # Number of write requests accepted
+system.physmem.readBursts                      404934                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     159706                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25910208                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5568                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10081344                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25915776                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10221184                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       87                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2165                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            154                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25481                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               25742                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25842                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25776                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25226                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25839                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25784                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25228                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               24953                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24814                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24563                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24817                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24560                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               25102                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25273                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25528                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24851                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24526                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25274                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25530                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24856                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24523                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              25574                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25842                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25743                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10288                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10037                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10678                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               10053                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9806                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9437                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9137                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8750                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9885                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8937                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9881                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9301                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9770                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              10691                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10395                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              10507                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25845                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25739                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10323                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10094                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10597                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9998                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9794                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9430                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9122                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8746                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9866                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8965                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9841                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9391                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9895                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10602                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10396                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10461                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1884232486500                       # Total gap between requests
+system.physmem.totGap                    1884226862500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404936                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404934                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 159699                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402545                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        71                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 159706                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402541                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        69                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -144,119 +144,119 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     8041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     9181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    11113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    12053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4012                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     9238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    10015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11798                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11832                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7957                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65749                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      547.429771                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     335.789885                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     418.130322                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14719     22.39%     22.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10714     16.30%     38.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4807      7.31%     45.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3176      4.83%     50.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2550      3.88%     54.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1953      2.97%     57.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1437      2.19%     59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1697      2.58%     62.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24696     37.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65749                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5738                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        70.553154                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2788.767091                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5735     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65747                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      547.425008                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     336.336786                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.790126                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14590     22.19%     22.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10813     16.45%     38.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4856      7.39%     46.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3188      4.85%     50.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2531      3.85%     54.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1959      2.98%     57.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1455      2.21%     59.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1675      2.55%     62.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24680     37.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65747                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5741                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.518028                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2788.038880                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5738     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5738                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5738                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.457825                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.746842                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       34.017596                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4693     81.79%     81.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             187      3.26%     85.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             275      4.79%     89.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              67      1.17%     91.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              92      1.60%     92.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              47      0.82%     93.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              24      0.42%     93.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              11      0.19%     94.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              19      0.33%     94.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               7      0.12%     94.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103             14      0.24%     94.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             6      0.10%     94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             7      0.12%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             4      0.07%     95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            17      0.30%     95.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            47      0.82%     96.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            17      0.30%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            17      0.30%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            79      1.38%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            32      0.56%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            20      0.35%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            19      0.33%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            15      0.26%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             7      0.12%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             4      0.07%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             3      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5738                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2167079250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9757773000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2024185000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        5352.97                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5741                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5741                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.437903                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.774518                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       33.753883                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4686     81.62%     81.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             175      3.05%     84.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             305      5.31%     89.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              60      1.05%     91.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              91      1.59%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              55      0.96%     93.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              13      0.23%     93.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              10      0.17%     93.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              19      0.33%     94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.09%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             16      0.28%     94.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            10      0.17%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            11      0.19%     95.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             3      0.05%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            17      0.30%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            40      0.70%     96.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            20      0.35%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            16      0.28%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            94      1.64%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            33      0.57%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            16      0.28%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            17      0.30%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             9      0.16%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.09%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.05%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5741                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2143675250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9734556500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2024235000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5295.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24102.97                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24045.03                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.75                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           5.35                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.75                       # Average system read bandwidth in MiByte/s
@@ -266,66 +266,71 @@ system.physmem.busUtil                           0.15                       # Da
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364185                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    132456                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        25.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364210                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    132411                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   89.96                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.06                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3337080.57                       # Average gap between requests
+system.physmem.writeRowHitRate                  84.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3337041.06                       # Average gap between requests
 system.physmem.pageHitRate                      88.31                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1774592996500                       # Time in different power states
-system.physmem.memoryStateTime::REF       62918700000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       46722146000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 242668440                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 254394000                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 132408375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 138806250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1578704400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1579024200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               506645280                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               514298160                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          123068977200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          123068977200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           59931006120                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           60719870160                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1077969239250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1077277253250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1263429649065                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1263552623220                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.526996                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.592261                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                15011318                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13019220                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            376037                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9980368                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5204970                       # Number of BTB hits
+system.physmem_0.actEnergy                  243152280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132672375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1578751200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                506113920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           123068977200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            59789504475                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1078093355250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1263412526700                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.517914                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1793297401750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62918700000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28017727000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  253895040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  138534000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1579055400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                514622160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           123068977200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            60612218820                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1077371684250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1263538986870                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.585024                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1792097761500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62918700000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     29217381000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                15006303                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13014667                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            375459                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9787101                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5202858                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             52.152085                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  808971                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              32603                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             53.160359                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  808926                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32598                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9241438                       # DTB read hits
-system.cpu.dtb.read_misses                      17791                       # DTB read misses
+system.cpu.dtb.read_hits                      9241313                       # DTB read hits
+system.cpu.dtb.read_misses                      17796                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   766265                       # DTB read accesses
-system.cpu.dtb.write_hits                     6385998                       # DTB write hits
-system.cpu.dtb.write_misses                      2317                       # DTB write misses
-system.cpu.dtb.write_acv                          159                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298404                       # DTB write accesses
-system.cpu.dtb.data_hits                     15627436                       # DTB hits
-system.cpu.dtb.data_misses                      20108                       # DTB misses
-system.cpu.dtb.data_acv                           370                       # DTB access violations
-system.cpu.dtb.data_accesses                  1064669                       # DTB accesses
-system.cpu.itb.fetch_hits                     4019003                       # ITB hits
-system.cpu.itb.fetch_misses                      6884                       # ITB misses
-system.cpu.itb.fetch_acv                          661                       # ITB acv
-system.cpu.itb.fetch_accesses                 4025887                       # ITB accesses
+system.cpu.dtb.read_accesses                   766310                       # DTB read accesses
+system.cpu.dtb.write_hits                     6385986                       # DTB write hits
+system.cpu.dtb.write_misses                      2327                       # DTB write misses
+system.cpu.dtb.write_acv                          160                       # DTB write access violations
+system.cpu.dtb.write_accesses                  298447                       # DTB write accesses
+system.cpu.dtb.data_hits                     15627299                       # DTB hits
+system.cpu.dtb.data_misses                      20123                       # DTB misses
+system.cpu.dtb.data_acv                           371                       # DTB access violations
+system.cpu.dtb.data_accesses                  1064757                       # DTB accesses
+system.cpu.itb.fetch_hits                     4016976                       # ITB hits
+system.cpu.itb.fetch_misses                      6883                       # ITB misses
+system.cpu.itb.fetch_acv                          674                       # ITB acv
+system.cpu.itb.fetch_accesses                 4023859                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -338,39 +343,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        175285694                       # number of cpu cycles simulated
+system.cpu.numCycles                        175257245                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56124126                       # Number of instructions committed
-system.cpu.committedOps                      56124126                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2495853                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5575                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3593196852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.123179                       # CPI: cycles per instruction
-system.cpu.ipc                               0.320187                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56122640                       # Number of instructions committed
+system.cpu.committedOps                      56122640                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2496382                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5595                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3593213949                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.122755                       # CPI: cycles per instruction
+system.cpu.ipc                               0.320230                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211480                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74791     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6377                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211475                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74790     40.94%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105868     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182691                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73424     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105864     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182686                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73423     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73424     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148880                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1833816082000     97.32%     97.32% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                80474500      0.00%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               673053000      0.04%     97.36% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             49670669500      2.64%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1884240279000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good::31                    73423     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148878                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1833807390500     97.32%     97.32% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                80545000      0.00%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               673176000      0.04%     97.36% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             49673506000      2.64%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1884234617500                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981722                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693543                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814928                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693560                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814939                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -409,7 +414,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175532     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175527     91.22%     93.43% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
@@ -418,28 +423,28 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.97% # nu
 system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192418                       # number of callpals executed
+system.cpu.kern.callpal::total                 192413                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5870                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1743                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1913                      
-system.cpu.kern.mode_good::user                  1743                      
+system.cpu.kern.mode_good::kernel                1910                      
+system.cpu.kern.mode_good::user                  1740                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.325894                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.325383                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393986                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36270859500      1.92%      1.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4083023000      0.22%      2.14% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1843886386500     97.86%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.393490                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36258202500      1.92%      1.92% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4079939000      0.22%      2.14% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1843896466000     97.86%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
-system.cpu.tickCycles                        84485847                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        90799847                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1395229                       # number of replacements
+system.cpu.tickCycles                        84474734                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        90782511                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1395383                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.982334                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13773041                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395741                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.867906                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            13772439                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395895                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.866386                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          86820250                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982334                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999965                       # Average percentage of cache occupancy
@@ -449,72 +454,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          231
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63657366                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63657366                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst      7814636                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7814636                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst      5576637                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5576637                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182736                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182736                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          63656284                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63656284                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst      7814297                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7814297                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      5576378                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576378                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182732                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182732                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.inst       198999                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       198999                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      13391273                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13391273                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     13391273                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13391273                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      1201532                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201532                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       573582                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573582                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17284                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17284                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1775114                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1775114                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1775114                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1775114                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31036730750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31036730750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20700048539                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20700048539                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231020000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    231020000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  51736779289                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51736779289                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  51736779289                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51736779289                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst      9016168                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9016168                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst      6150219                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6150219                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.inst      13390675                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13390675                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     13390675                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13390675                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1201640                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201640                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       573763                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573763                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17288                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17288                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1775403                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775403                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1775403                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775403                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31034654250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31034654250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20679395543                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20679395543                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231275750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    231275750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  51714049793                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51714049793                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  51714049793                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51714049793                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst      9015937                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9015937                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      6150141                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6150141                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200020                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200020                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198999                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       198999                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     15166387                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15166387                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     15166387                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15166387                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133264                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133264                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093262                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093262                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086411                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086411                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.117043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.117043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29145.609403                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29145.609403                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.inst     15166078                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15166078                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     15166078                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15166078                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133280                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133280                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093293                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093293                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086431                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086431                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.117064                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117064                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.117064                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117064                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25826.915091                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36041.702834                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13377.819875                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29128.062639                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29128.062639                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29128.062639                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29128.062639                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -523,64 +528,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838115                       # number of writebacks
-system.cpu.dcache.writebacks::total            838115                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127210                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127210                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269406                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269406                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       838265                       # number of writebacks
+system.cpu.dcache.writebacks::total            838265                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127268                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127268                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269487                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269487                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       396616                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       396616                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       396616                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       396616                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074322                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074322                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304176                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304176                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17281                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17281                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1378498                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378498                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1378498                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378498                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26919627250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26919627250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10259801597                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10259801597                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196291500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196291500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37179428847                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37179428847                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37179428847                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37179428847                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423887000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423887000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2002910000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002910000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426797000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426797000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119155                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119155                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049458                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086396                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086396                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090892                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090892                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090892                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090892                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26970.970467                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26970.970467                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26970.970467                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26970.970467                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.inst       396755                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       396755                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       396755                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       396755                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074372                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074372                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304276                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304276                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17285                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17285                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1378648                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378648                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1378648                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378648                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26917637000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26917637000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10249005096                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10249005096                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196537750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196537750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37166642096                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37166642096                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37166642096                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37166642096                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423897500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423897500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2002909000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002909000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426806500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426806500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119164                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119164                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049475                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086416                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086416                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090903                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090903                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090903                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090903                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25054.298697                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33683.251706                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11370.422332                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26958.761117                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26958.761117                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -588,58 +593,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1458001                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.626489                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18970775                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1458512                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             13.006938                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31607473250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.626489                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           1459474                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.626385                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18964719                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1459985                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.989667                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31607466250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.626385                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.995364                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.995364                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21888154                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21888154                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18970778                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18970778                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18970778                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18970778                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18970778                       # number of overall hits
-system.cpu.icache.overall_hits::total        18970778                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1458688                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1458688                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1458688                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1458688                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1458688                       # number of overall misses
-system.cpu.icache.overall_misses::total       1458688                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20029373869                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20029373869                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20029373869                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20029373869                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20029373869                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20029373869                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20429466                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20429466                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20429466                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20429466                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20429466                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20429466                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071401                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071401                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071401                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071401                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071401                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071401                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13731.088395                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13731.088395                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13731.088395                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13731.088395                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13731.088395                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13731.088395                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          21885040                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21885040                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18964722                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18964722                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18964722                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18964722                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18964722                       # number of overall hits
+system.cpu.icache.overall_hits::total        18964722                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1460159                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1460159                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1460159                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1460159                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1460159                       # number of overall misses
+system.cpu.icache.overall_misses::total       1460159                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20038728384                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20038728384                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20038728384                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20038728384                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20038728384                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20038728384                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20424881                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20424881                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20424881                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20424881                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20424881                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20424881                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071489                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071489                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071489                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071489                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071489                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071489                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13723.661864                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13723.661864                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13723.661864                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13723.661864                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13723.661864                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -648,115 +653,115 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458688                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1458688                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1458688                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1458688                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1458688                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1458688                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17104729131                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17104729131                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17104729131                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17104729131                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17104729131                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17104729131                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071401                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071401                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071401                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11726.105330                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11726.105330                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11726.105330                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1460159                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1460159                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1460159                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1460159                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1460159                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1460159                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17111152616                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17111152616                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17111152616                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17111152616                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17111152616                       # number of overall MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071489                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11718.691332                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11718.691332                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           339435                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65326.200893                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2981535                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404597                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.369148                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           339433                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65325.334655                       # Cycle average of tags in use
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+system.cpu.l2cache.tags.avg_refs             7.373326                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       5873248750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2791                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55536                       # Occupied blocks per task id
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-system.cpu.l2cache.Writeback_hits::total       838115                       # number of Writeback hits
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 system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           21                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.809524                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474                       # average ReadReq miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69119.344261                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66572.913111                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66572.913111                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -765,54 +770,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76635                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76635                       # number of writebacks
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 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           17                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       271014                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       271014                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333779000                       # number of ReadReq MSHR uncacheable cycles
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 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.809524                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383500                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383500                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142009                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.142009                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142009                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.142009                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383443                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383443                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.141928                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141928                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.141928                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141928                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.852143                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst        15942                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15942                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56539.364471                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54048.584026                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54048.584026                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -820,42 +825,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2557364                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557331                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2558889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2558856                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       838115                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       838265                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304285                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304285                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917316                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3662927                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6580243                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93352192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143021148                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          236373340                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       41941                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3734307                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.011173                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.105112                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2920255                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3663385                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6583640                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93446144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143040604                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          236486748                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       41944                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3736082                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.011168                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.105088                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3692582     98.88%     98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3694357     98.88%     98.88% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2              41725      1.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3734307                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2697490998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3736082                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2698528498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2191666369                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2193867384                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2194528153                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2194759654                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -928,7 +933,7 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           406196790                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406197789                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
@@ -937,14 +942,14 @@ system.iobus.respLayer0.utilization               0.0                       # La
 system.iobus.respLayer1.occupancy            42010500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.296059                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.296028                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1728026020000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.296059                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081004                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081004                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1728025570000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.296028                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081002                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081002                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -960,8 +965,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13635314907                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  13635314907                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13635920906                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13635920906                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
@@ -984,17 +989,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        206297                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs        206267                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                23564                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23556                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.754753                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.756453                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1010,8 +1015,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11474610907                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11474610907                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11475216906                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11475216906                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
@@ -1026,57 +1031,57 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              295796                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295780                       # Transaction distribution
+system.membus.trans_dist::ReadReq              295774                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295758                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
-system.membus.trans_dist::Writeback            118147                       # Transaction distribution
+system.membus.trans_dist::Writeback            118154                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              155                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             155                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116517                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116517                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              156                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             156                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116537                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116537                       # Transaction distribution
 system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887063                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920188                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920193                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1044992                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1044997                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30819584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30863900                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30819904                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30864220                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36180956                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36181276                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
-system.membus.snoop_fanout::samples            565237                       # Request fanout histogram
+system.membus.snoop_fanout::samples            565243                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  565237    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  565243    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              565237                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30298500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              565243                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30308000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1878232500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1878196000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy               20000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3792450097                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3792332596                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           43109500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 092a1319f..38c6e11f9 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.901187                       # Number of seconds simulated
-sim_ticks                                1901187238000                       # Number of ticks simulated
-final_tick                               1901187238000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.901175                       # Number of seconds simulated
+sim_ticks                                1901175003500                       # Number of ticks simulated
+final_tick                               1901175003500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164685                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164685                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5473626023                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 324480                       # Number of bytes of host memory used
-host_seconds                                   347.34                       # Real time elapsed on the host
-sim_insts                                    57201060                       # Number of instructions simulated
-sim_ops                                      57201060                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 154934                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154934                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5197600055                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 378544                       # Number of bytes of host memory used
+host_seconds                                   365.78                       # Real time elapsed on the host
+sim_insts                                    56671579                       # Number of instructions simulated
+sim_ops                                      56671579                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           886592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24764800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            96384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           525056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           885824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24795264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            95808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           496320                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26273792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       886592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        96384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          982976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7873024                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7873024                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13853                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            386950                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1506                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8204                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26274176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       885824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        95808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          981632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7885056                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7885056                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13841                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            387426                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1497                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              7755                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                410528                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123016                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123016                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              466336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            13025966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               50697                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              276173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                410534                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123204                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123204                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              465935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            13042073                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               50394                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              261060                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13819676                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         466336                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          50697                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517033                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4141109                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4141109                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4141109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             466336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13025966                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              50697                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             276173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13819967                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         465935                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          50394                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             516329                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4147465                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4147465                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4147465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             465935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13042073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              50394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             261060                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17960785                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        410528                       # Number of read requests accepted
-system.physmem.writeReqs                       164568                       # Number of write requests accepted
-system.physmem.readBursts                      410528                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     164568                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26267072                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10385920                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26273792                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10532352                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2261                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           6311                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25881                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25672                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26260                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25757                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25283                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25202                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25755                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25257                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25550                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25721                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25770                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25804                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25810                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25881                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25644                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25176                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10943                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9789                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10222                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9625                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9290                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9560                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10277                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9346                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9649                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9784                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9978                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              10113                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              11182                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              11629                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10712                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              10181                       # Per bank write bursts
+system.physmem.bw_total::total               17967432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410534                       # Number of read requests accepted
+system.physmem.writeReqs                       164756                       # Number of write requests accepted
+system.physmem.readBursts                      410534                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     164756                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26267904                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6272                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10393408                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26274176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10544384                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       98                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2335                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4921                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25742                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25822                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25939                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25643                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25873                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25657                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25709                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25201                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25222                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               26115                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25677                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25575                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25800                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26085                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25301                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25075                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10194                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10103                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10030                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9736                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9490                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10167                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10200                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9338                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9741                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10459                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10157                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10688                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              11170                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              11200                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10147                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9577                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1901182789000                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1901170614000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  410528                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410534                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 164568                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317417                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     40637                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     43118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        73                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 164756                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317401                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     40588                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     43093                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9265                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
@@ -158,187 +158,193 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5616                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    11504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    12419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    12067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    12285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    11257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9416                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    12109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    11277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10599                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9498                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      259                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      180                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        67066                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      546.521218                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     334.319778                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     419.846112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14858     22.15%     22.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11363     16.94%     39.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5157      7.69%     46.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2935      4.38%     51.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2350      3.50%     54.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1701      2.54%     57.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1587      2.37%     59.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1704      2.54%     62.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25411     37.89%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          67066                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6000                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        68.402667                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2725.840527                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5997     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67203                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      545.527075                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     333.566914                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.530844                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14928     22.21%     22.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11337     16.87%     39.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5205      7.75%     46.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2937      4.37%     51.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2377      3.54%     54.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1798      2.68%     57.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1602      2.38%     59.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1684      2.51%     62.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25335     37.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67203                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6020                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.178073                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2721.311016                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6017     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6000                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.046667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.651184                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       33.190276                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4953     82.55%     82.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             193      3.22%     85.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             289      4.82%     90.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              50      0.83%     91.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              96      1.60%     93.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              44      0.73%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              19      0.32%     94.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               8      0.13%     94.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              23      0.38%     94.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              10      0.17%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103             13      0.22%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             6      0.10%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             7      0.12%     95.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             5      0.08%     95.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            20      0.33%     95.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            38      0.63%     96.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            17      0.28%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            12      0.20%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            91      1.52%     98.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            43      0.72%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            17      0.28%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            19      0.32%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             8      0.13%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             9      0.15%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6000                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3893190750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11588622000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2052115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9485.80                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6020                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6020                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        26.976246                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.646869                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       33.117275                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4955     82.31%     82.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             186      3.09%     85.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             316      5.25%     90.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              58      0.96%     91.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              93      1.54%     93.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              41      0.68%     93.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              21      0.35%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              11      0.18%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              26      0.43%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               4      0.07%     94.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             17      0.28%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.07%     95.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             7      0.12%     95.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.03%     95.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            20      0.33%     95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            42      0.70%     96.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            17      0.28%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             7      0.12%     96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            80      1.33%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            45      0.75%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            12      0.20%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            27      0.45%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             6      0.10%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.08%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             4      0.07%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             4      0.07%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             4      0.07%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6020                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3885054500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11580729500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2052180000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9465.68                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28235.80                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28215.68                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.82                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           5.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.47                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.82                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.54                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.97                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     370176                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    135461                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         2.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     370181                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    135448                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   90.19                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.46                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3305852.92                       # Average gap between requests
-system.physmem.pageHitRate                      88.29                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1800384684500                       # Time in different power states
-system.physmem.memoryStateTime::REF       63484720000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37315104250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 252216720                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 254802240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 137618250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 139029000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1599522600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1601776800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               512256960                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               539317440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          124176112320                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          124176112320                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           57055460715                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           57001965930                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1090662047250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1090708972500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1274395234815                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1274421976230                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.316446                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.330512                       # Core power per rank (mW)
-system.cpu0.branchPred.lookups               15024669                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13090822                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           302150                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             9266199                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5129053                       # Number of BTB hits
+system.physmem.writeRowHitRate                  83.39                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3304716.95                       # Average gap between requests
+system.physmem.pageHitRate                      88.26                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  253260000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  138187500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1603570800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                513591840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124175095200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            57090888495                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1090621618500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1274396212335                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.322456                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1814181645000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63484200000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23503077500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  254688840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  138967125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1597455600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                538429680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124175095200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            57028143465                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1090676670000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1274409449910                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.329412                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1814277217000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63484200000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23408681000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu0.branchPred.lookups               16131633                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14074847                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           326763                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             9526803                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5411642                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            55.352286                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 762066                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             14857                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            56.804387                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 814199                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             17678                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8699665                       # DTB read hits
-system.cpu0.dtb.read_misses                     31652                       # DTB read misses
-system.cpu0.dtb.read_acv                          518                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  684964                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5527628                       # DTB write hits
-system.cpu0.dtb.write_misses                     7312                       # DTB write misses
-system.cpu0.dtb.write_acv                         384                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 236678                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14227293                       # DTB hits
-system.cpu0.dtb.data_misses                     38964                       # DTB misses
-system.cpu0.dtb.data_acv                          902                       # DTB access violations
-system.cpu0.dtb.data_accesses                  921642                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1360805                       # ITB hits
-system.cpu0.itb.fetch_misses                    29325                       # ITB misses
-system.cpu0.itb.fetch_acv                         623                       # ITB acv
-system.cpu0.itb.fetch_accesses                1390130                       # ITB accesses
+system.cpu0.dtb.read_hits                     9231009                       # DTB read hits
+system.cpu0.dtb.read_misses                     34580                       # DTB read misses
+system.cpu0.dtb.read_acv                          535                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  687791                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5940395                       # DTB write hits
+system.cpu0.dtb.write_misses                     7538                       # DTB write misses
+system.cpu0.dtb.write_acv                         382                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 237219                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15171404                       # DTB hits
+system.cpu0.dtb.data_misses                     42118                       # DTB misses
+system.cpu0.dtb.data_acv                          917                       # DTB access violations
+system.cpu0.dtb.data_accesses                  925010                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1435355                       # ITB hits
+system.cpu0.itb.fetch_misses                    29386                       # ITB misses
+system.cpu0.itb.fetch_acv                         625                       # ITB acv
+system.cpu0.itb.fetch_accesses                1464741                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -351,467 +357,466 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       108792579                       # number of cpu cycles simulated
+system.cpu0.numCycles                       112944275                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          24480610                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      66921510                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   15024669                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5891119                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     76960209                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1006918                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       587                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               30320                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      1459024                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       459440                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          228                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7808182                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               214478                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         103893877                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.644133                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.944480                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          26734623                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      70871158                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   16131633                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6225841                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     78572167                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1087344                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       938                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               28136                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      1452901                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       461019                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          278                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8195583                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               233790                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         107793734                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.657470                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.965319                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                91308838     87.89%     87.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  814381      0.78%     88.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1763801      1.70%     90.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  741690      0.71%     91.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2523255      2.43%     93.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  561128      0.54%     94.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  635570      0.61%     94.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  719335      0.69%     95.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4825879      4.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                94531257     87.70%     87.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  858509      0.80%     88.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1823492      1.69%     90.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  785861      0.73%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2602190      2.41%     93.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  590625      0.55%     93.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  664328      0.62%     94.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  839547      0.78%     95.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5097925      4.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           103893877                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.138104                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.615129                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                19900832                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             73745257                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8046257                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1730950                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                470580                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              495026                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                33344                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              58913691                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               103815                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                470580                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                20722206                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               48316669                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17970373                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  8856068                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7557979                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              56901533                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               202703                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2015999                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                141191                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               3736855                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           38160864                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             69501237                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        69376844                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           115358                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33567232                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4593624                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1365129                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        198221                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12480015                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8824182                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5791367                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1299957                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          953544                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  50831435                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1735186                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 49951846                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            52661                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5989483                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2856975                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1193961                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    103893877                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.480797                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.214404                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           107793734                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.142828                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.627488                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                21731474                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             75223274                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8544304                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1787077                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                507604                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              524648                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                36495                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              62167212                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               115754                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                507604                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                22589385                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               48401768                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      19164228                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9376952                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7753795                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              60013920                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               204923                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2024034                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                144343                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               3822558                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           40119139                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             72975711                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        72834321                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           131688                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             35221894                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4897237                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1480119                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        216056                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12920416                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9368350                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6206352                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1340557                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          962340                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  53512619                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1895957                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 52599778                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            52230                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6392747                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3006442                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1305426                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    107793734                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.487967                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.221871                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           83240383     80.12%     80.12% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            8994841      8.66%     88.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3729897      3.59%     92.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2662216      2.56%     94.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2692674      2.59%     97.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1272103      1.22%     98.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             842802      0.81%     99.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             349148      0.34%     99.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             109813      0.11%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           86044446     79.82%     79.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9475309      8.79%     88.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3928815      3.64%     92.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2790586      2.59%     94.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2836372      2.63%     97.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1349941      1.25%     98.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             893970      0.83%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             358292      0.33%     99.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             116003      0.11%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      103893877                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      107793734                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 174329     19.02%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     19.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                437335     47.71%     66.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               305033     33.28%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 177733     18.25%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                467063     47.95%     66.19% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               329340     33.81%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             34481483     69.03%     69.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               54630      0.11%     69.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              27712      0.06%     69.20% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.20% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.20% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.20% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9019851     18.06%     87.26% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5598402     11.21%     98.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            764115      1.53%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             36087462     68.61%     68.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57222      0.11%     68.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              28709      0.05%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9582527     18.22%     87.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6011046     11.43%     98.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            827159      1.57%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              49951846                       # Type of FU issued
-system.cpu0.iq.rate                          0.459148                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     916697                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.018352                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         204260867                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         58336070                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     48679612                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             506059                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            237571                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       232415                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              50592327                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 272446                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          560089                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              52599778                       # Type of FU issued
+system.cpu0.iq.rate                          0.465714                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     974136                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018520                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         213441030                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         61548330                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     51220095                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             578625                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            270952                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       265721                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              53258517                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 311627                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          583786                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1038811                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4304                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        17864                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       487331                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1112279                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         5019                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18330                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       503254                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18869                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       349661                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18853                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       369989                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                470580                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               44276704                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1577501                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           55768983                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           120052                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8824182                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5791367                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1533608                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 47079                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1307470                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         17864                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        152204                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       328517                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              480721                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             49479281                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8753036                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           472564                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                507604                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               44339596                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1604348                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           58817574                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           124782                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9368350                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6206352                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1675353                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 48473                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1332642                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18330                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        164161                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       356822                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              520983                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             52091421                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9288991                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           508356                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3202362                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14301032                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7879408                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5547996                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.454804                       # Inst execution rate
-system.cpu0.iew.wb_sent                      49022541                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     48912027                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 25297454                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 34938196                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3408998                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15250639                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8273174                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5961648                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.461213                       # Inst execution rate
+system.cpu0.iew.wb_sent                      51600991                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     51485816                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26436063                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36546981                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.449590                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.724063                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.455851                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.723345                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6548409                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         541225                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           440159                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    102738863                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.478033                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.411836                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        7016261                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         590531                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           476969                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    106554717                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.485172                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.424408                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     85310078     83.04%     83.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      6928869      6.74%     89.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3804927      3.70%     93.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2004533      1.95%     95.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1514323      1.47%     96.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       555844      0.54%     97.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       414883      0.40%     97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       408778      0.40%     98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1796628      1.75%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     88252662     82.82%     82.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7298996      6.85%     89.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3974083      3.73%     93.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2090799      1.96%     95.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1561874      1.47%     96.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       585444      0.55%     97.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       439090      0.41%     97.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       445608      0.42%     98.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1906161      1.79%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    102738863                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            49112602                       # Number of instructions committed
-system.cpu0.commit.committedOps              49112602                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    106554717                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            51697359                       # Number of instructions committed
+system.cpu0.commit.committedOps              51697359                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13089407                       # Number of memory references committed
-system.cpu0.commit.loads                      7785371                       # Number of loads committed
-system.cpu0.commit.membars                     183023                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7443994                       # Number of branches committed
-system.cpu0.commit.fp_insts                    229281                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 45524861                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              617737                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2801788      5.70%      5.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        32185758     65.53%     71.24% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          53394      0.11%     71.35% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.35% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         27239      0.06%     71.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        7968394     16.22%     87.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5310031     10.81%     98.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       764115      1.56%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      13959169                       # Number of memory references committed
+system.cpu0.commit.loads                      8256071                       # Number of loads committed
+system.cpu0.commit.membars                     200989                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7816314                       # Number of branches committed
+system.cpu0.commit.fp_insts                    262681                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 47879291                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              663768                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2971590      5.75%      5.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        33646334     65.08%     70.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55999      0.11%     70.94% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.94% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         28236      0.05%     70.99% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.99% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.99% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.99% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1883      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8457060     16.36%     87.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5709098     11.04%     98.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       827159      1.60%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         49112602                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1796628                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         51697359                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1906161                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   156399894                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  112470885                       # The number of ROB writes
-system.cpu0.timesIdled                         448982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        4898702                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3693581898                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   46314581                       # Number of Instructions Simulated
-system.cpu0.committedOps                     46314581                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.348992                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.348992                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.425715                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.425715                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                65241971                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               35484902                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   114300                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  114851                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1680980                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                762179                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          1226061                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.967877                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9972327                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1226573                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.130235                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                   163161097                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  118660594                       # The number of ROB writes
+system.cpu0.timesIdled                         501791                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5150541                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3689405733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   48729536                       # Number of Instructions Simulated
+system.cpu0.committedOps                     48729536                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.317779                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.317779                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.431448                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.431448                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                68466406                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37249066                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   130692                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  131766                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1811017                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                827352                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          1291740                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.889209                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10636670                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1292252                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.231111                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         25151000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.967877                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988219                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988219                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.889209                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988065                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988065                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          236                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         53849509                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        53849509                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6192446                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6192446                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3442531                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3442531                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150135                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       150135                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       172107                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       172107                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9634977                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9634977                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9634977                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9634977                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1501821                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1501821                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1669841                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1669841                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        19141                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19141                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4636                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         4636                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3171662                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3171662                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3171662                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3171662                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39101656628                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  39101656628                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  78115764371                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  78115764371                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    290102987                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    290102987                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     35172730                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     35172730                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 117217420999                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 117217420999                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7694267                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7694267                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5112372                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5112372                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       169276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176743                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       176743                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12806639                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12806639                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12806639                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12806639                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.195187                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.195187                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.326627                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.326627                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113076                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113076                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026230                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026230                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.247658                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.247658                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.247658                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.247658                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7586.870147                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7586.870147                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      3837622                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         3343                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           160954                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             89                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.842974                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    37.561798                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         57483025                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        57483025                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6556019                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6556019                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3715997                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3715997                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       164872                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       164872                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       189733                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       189733                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10272016                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10272016                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10272016                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10272016                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1615331                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1615331                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1779982                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1779982                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21282                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21282                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2627                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2627                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3395313                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3395313                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3395313                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3395313                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40801843239                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  40801843239                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  80191363617                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  80191363617                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    336613990                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    336613990                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     19436381                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     19436381                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 120993206856                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 120993206856                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8171350                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8171350                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5495979                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5495979                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       186154                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       186154                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192360                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       192360                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13667329                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13667329                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13667329                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13667329                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197682                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.197682                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.323870                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.323870                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114325                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114325                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.013657                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.013657                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248425                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.248425                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248425                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.248425                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7398.698515                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7398.698515                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      3895440                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         3799                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           167914                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             94                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.199019                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    40.414894                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       711843                       # number of writebacks
-system.cpu0.dcache.writebacks::total           711843                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       520027                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       520027                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1419840                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1419840                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4544                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4544                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1939867                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1939867                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1939867                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1939867                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       981794                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       981794                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       250001                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       250001                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14597                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14597                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4636                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         4636                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1231795                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1231795                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1231795                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1231795                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27071690424                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27071690424                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11368022018                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11368022018                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    148174261                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    148174261                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25899270                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25899270                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  38439712442                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  38439712442                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  38439712442                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  38439712442                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1458085000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1458085000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2211101998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2211101998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3669186998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3669186998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127601                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127601                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048901                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048901                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086232                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086232                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026230                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026230                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096184                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096184                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096184                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096184                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5586.555220                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5586.555220                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       762456                       # number of writebacks
+system.cpu0.dcache.writebacks::total           762456                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       593909                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       593909                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1512221                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1512221                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5168                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5168                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2106130                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2106130                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2106130                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2106130                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1021422                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1021422                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       267761                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       267761                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16114                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16114                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2626                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2626                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1289183                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1289183                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1289183                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1289183                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27591103326                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27591103326                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11693886534                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11693886534                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    178834256                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    178834256                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14183619                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14183619                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  39284989860                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  39284989860                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  39284989860                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  39284989860                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1458359000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1458359000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2137811998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2137811998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3596170998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3596170998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125000                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125000                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048719                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048719                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086563                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086563                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.013651                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.013651                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094326                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.094326                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094326                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.094326                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5401.225819                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5401.225819                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -819,126 +824,126 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           821620                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.585426                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            6946118                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           822130                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.448929                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      26485869250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.585426                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995284                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995284                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           914535                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.589702                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7236389                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           915045                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             7.908233                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      26485919250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.589702                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995292                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.995292                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          431                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          427                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          8630516                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         8630516                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6946118                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6946118                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6946118                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6946118                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6946118                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6946118                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       862061                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       862061                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       862061                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        862061                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       862061                       # number of overall misses
-system.cpu0.icache.overall_misses::total       862061                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12338398473                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12338398473                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12338398473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12338398473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12338398473                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12338398473                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7808179                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7808179                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7808179                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7808179                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7808179                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7808179                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.110405                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.110405                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.110405                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.110405                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.110405                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.110405                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14312.674478                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14312.674478                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4878                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          9110810                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9110810                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7236389                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7236389                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7236389                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7236389                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7236389                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7236389                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       959193                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       959193                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       959193                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        959193                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       959193                       # number of overall misses
+system.cpu0.icache.overall_misses::total       959193                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13598697683                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13598697683                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13598697683                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13598697683                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13598697683                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13598697683                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8195582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8195582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8195582                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8195582                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8195582                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8195582                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117038                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.117038                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117038                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.117038                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117038                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.117038                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14177.227819                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14177.227819                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4960                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              185                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              197                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.367568                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.177665                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        39724                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        39724                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        39724                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        39724                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        39724                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        39724                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       822337                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       822337                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       822337                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       822337                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       822337                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       822337                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10177943027                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10177943027                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10177943027                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10177943027                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10177943027                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10177943027                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105317                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.105317                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105317                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.105317                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43965                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43965                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        43965                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43965                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        43965                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43965                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915228                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       915228                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       915228                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       915228                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       915228                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       915228                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11221708315                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11221708315                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11221708315                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11221708315                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11221708315                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11221708315                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111673                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.111673                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111673                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.111673                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                4575539                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          4011453                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            80159                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2846769                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1118608                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3410499                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2981782                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            63006                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             1861186                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 813170                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            39.293950                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 219011                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              6943                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            43.690958                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 161954                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              4822                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2376918                       # DTB read hits
-system.cpu1.dtb.read_misses                      9978                       # DTB read misses
-system.cpu1.dtb.read_acv                            5                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  290947                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1576285                       # DTB write hits
-system.cpu1.dtb.write_misses                     2026                       # DTB write misses
-system.cpu1.dtb.write_acv                          38                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 109535                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3953203                       # DTB hits
-system.cpu1.dtb.data_misses                     12004                       # DTB misses
-system.cpu1.dtb.data_acv                           43                       # DTB access violations
-system.cpu1.dtb.data_accesses                  400482                       # DTB accesses
-system.cpu1.itb.fetch_hits                     602928                       # ITB hits
-system.cpu1.itb.fetch_misses                     5576                       # ITB misses
-system.cpu1.itb.fetch_acv                          51                       # ITB acv
-system.cpu1.itb.fetch_accesses                 608504                       # ITB accesses
+system.cpu1.dtb.read_hits                     1800297                       # DTB read hits
+system.cpu1.dtb.read_misses                      9623                       # DTB read misses
+system.cpu1.dtb.read_acv                            4                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  290908                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1120103                       # DTB write hits
+system.cpu1.dtb.write_misses                     2035                       # DTB write misses
+system.cpu1.dtb.write_acv                          37                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 109629                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2920400                       # DTB hits
+system.cpu1.dtb.data_misses                     11658                       # DTB misses
+system.cpu1.dtb.data_acv                           41                       # DTB access violations
+system.cpu1.dtb.data_accesses                  400537                       # DTB accesses
+system.cpu1.itb.fetch_hits                     513208                       # ITB hits
+system.cpu1.itb.fetch_misses                     5417                       # ITB misses
+system.cpu1.itb.fetch_acv                          59                       # ITB acv
+system.cpu1.itb.fetch_accesses                 518625                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -951,463 +956,463 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        18735029                       # number of cpu cycles simulated
+system.cpu1.numCycles                        13834996                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8327481                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      17619609                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4575539                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1337619                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9079051                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 321428                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles               26636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       222369                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        65129                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           13                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1934705                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                65647                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          17881393                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.985360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.396691                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           5742756                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      13201278                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3410499                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches            975124                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      7052078                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 251690                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               24829                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       212437                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        51117                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           24                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1482208                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                50416                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          13209086                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.999409                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.408470                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                14806869     82.81%     82.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  203122      1.14%     83.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  303524      1.70%     85.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  223355      1.25%     86.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  384843      2.15%     89.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  149669      0.84%     89.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  166893      0.93%     90.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  294645      1.65%     92.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1348473      7.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                10898169     82.51%     82.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  144102      1.09%     83.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  239022      1.81%     85.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  173764      1.32%     86.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  293834      2.22%     88.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  119928      0.91%     89.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  132080      1.00%     90.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  175112      1.33%     92.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1033075      7.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            17881393                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.244224                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.940463                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 6834927                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8400269                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2240291                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               252863                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                153042                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              134285                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 7749                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              14408505                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                25621                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                153042                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 7012697                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 586426                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6840794                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2316099                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               972333                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              13683407                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 9781                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 69005                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 16467                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                367791                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            8910587                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             16181694                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        16097130                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            77675                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              7724005                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1186582                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            556647                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         57942                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2323703                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2456737                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1657029                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           275399                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          155321                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  12021391                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             653222                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 11806375                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            22216                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1705669                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       770229                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        468205                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     17881393                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.660260                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.377042                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            13209086                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.246512                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.954195                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 4781490                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              6446001                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1665086                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               196515                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                119993                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              102189                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 5928                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              10739248                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                19374                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                119993                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 4918512                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 544557                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       5139003                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1724887                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               762132                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              10178184                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 4877                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 68265                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 13199                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                289695                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            6692544                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             12133960                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        12078154                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            50250                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              5671659                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1020885                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            419664                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         38232                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1772644                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1865226                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1191683                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           210655                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          119712                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   8963290                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             478811                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  8726606                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            20522                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1437541                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       698510                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        352654                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     13209086                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.660652                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.378469                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           12935770     72.34%     72.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2198264     12.29%     84.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             914656      5.12%     89.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             630896      3.53%     93.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             572849      3.20%     96.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             314457      1.76%     98.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             208202      1.16%     99.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              77174      0.43%     99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              29125      0.16%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0            9547804     72.28%     72.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1625741     12.31%     84.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             686242      5.20%     89.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             474957      3.60%     93.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             417301      3.16%     96.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             221804      1.68%     98.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             145793      1.10%     99.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              65024      0.49%     99.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              24420      0.18%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       17881393                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       13209086                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  23808      8.12%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                159009     54.21%     62.33% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               110483     37.67%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  22353      9.61%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                126163     54.23%     63.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                84116     36.16%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7355530     62.30%     62.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               19854      0.17%     62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              12327      0.10%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2486397     21.06%     83.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1602376     13.57%     97.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            324614      2.75%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              5425627     62.17%     62.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               15090      0.17%     62.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10661      0.12%     62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.51% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1878240     21.52%     84.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1141614     13.08%     97.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            250097      2.87%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              11806375                       # Type of FU issued
-system.cpu1.iq.rate                          0.630176                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     293300                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.024843                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          41494201                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         14236824                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     11389686                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             315458                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            147457                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       145351                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              11926347                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 169810                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          115792                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total               8726606                       # Type of FU issued
+system.cpu1.iq.rate                          0.630763                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     232632                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.026658                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          30722514                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         10791679                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      8409842                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             192938                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             91772                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        89511                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               8852667                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 103053                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           90033                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       308768                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         1081                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4102                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       143102                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       271460                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          498                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         3940                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       125337                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          395                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        55406                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          380                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        50736                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                153042                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 303896                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               248843                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           13398271                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            36703                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2456737                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1657029                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            586577                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4501                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               243181                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4102                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         36741                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       118067                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              154808                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             11654930                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2396476                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           151445                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                119993                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 268498                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               245239                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts            9936241                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            29107                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1865226                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1191683                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            435120                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  4465                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               239666                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          3940                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         28286                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        93108                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              121394                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              8606074                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1816179                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           120532                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       723658                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3982565                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1739472                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1586089                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.622093                       # Inst execution rate
-system.cpu1.iew.wb_sent                      11565622                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     11535037                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5422471                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7736628                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       494140                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     2943760                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1279494                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1127581                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.622051                       # Inst execution rate
+system.cpu1.iew.wb_sent                       8526125                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      8499353                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  4051784                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  5752933                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.615694                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.700883                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.614337                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.704299                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1839025                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         185017                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           142916                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     17538839                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.655077                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.643008                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1506985                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         126157                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           110245                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     12932417                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.645119                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.622232                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     13431880     76.58%     76.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1875136     10.69%     87.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       688221      3.92%     91.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       418119      2.38%     93.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       312509      1.78%     95.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       131127      0.75%     96.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       110360      0.63%     96.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       156367      0.89%     97.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       415120      2.37%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0      9905025     76.59%     76.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1407731     10.89%     87.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       501740      3.88%     91.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       308618      2.39%     93.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       224670      1.74%     95.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        96970      0.75%     96.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6        89070      0.69%     96.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       100805      0.78%     97.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       297788      2.30%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     17538839                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            11489295                       # Number of instructions committed
-system.cpu1.commit.committedOps              11489295                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     12932417                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             8342954                       # Number of instructions committed
+system.cpu1.commit.committedOps               8342954                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3661896                       # Number of memory references committed
-system.cpu1.commit.loads                      2147969                       # Number of loads committed
-system.cpu1.commit.membars                      61867                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1640602                       # Number of branches committed
-system.cpu1.commit.fp_insts                    143665                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 10598150                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              183822                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       606334      5.28%      5.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         6800030     59.19%     64.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          19654      0.17%     64.63% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.63% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         12323      0.11%     64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.74% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        2209836     19.23%     83.99% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1514745     13.18%     97.17% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       324614      2.83%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       2660112                       # Number of memory references committed
+system.cpu1.commit.loads                      1593766                       # Number of loads committed
+system.cpu1.commit.membars                      39768                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1189273                       # Number of branches committed
+system.cpu1.commit.fp_insts                     87820                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  7729091                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              132492                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       404429      4.85%      4.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         4960733     59.46%     64.31% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          14917      0.18%     64.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         10656      0.13%     64.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1759      0.02%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.64% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1633534     19.58%     84.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1066829     12.79%     97.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       250097      3.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         11489295                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               415120                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total          8342954                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               297788                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    30366198                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   26995045                       # The number of ROB writes
-system.cpu1.timesIdled                         163095                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         853636                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3782985916                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   10886479                       # Number of Instructions Simulated
-system.cpu1.committedOps                     10886479                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.720945                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.720945                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.581076                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.581076                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                14951888                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                8155185                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    77020                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   77068                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                1117526                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                276759                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           138501                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          492.617684                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3193598                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           138812                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.006642                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      39570817000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   492.617684                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.962144                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.962144                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          311                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          311                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.607422                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         15087685                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        15087685                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1906947                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1906947                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1195571                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1195571                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        44901                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        44901                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        43886                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        43886                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3102518                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3102518                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3102518                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3102518                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       266692                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       266692                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       262982                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       262982                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8052                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8052                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         4916                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         4916                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       529674                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        529674                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       529674                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       529674                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4020623652                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   4020623652                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8531401983                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8531401983                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     76759992                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     76759992                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     36344731                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     36344731                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  12552025635                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12552025635                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  12552025635                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12552025635                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2173639                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2173639                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1458553                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1458553                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        52953                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        52953                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        48802                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        48802                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3632192                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3632192                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3632192                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3632192                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.122694                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.122694                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.180303                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.180303                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152059                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152059                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100734                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100734                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.145828                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.145828                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.145828                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.145828                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9533.034277                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9533.034277                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7393.151139                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7393.151139                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       379144                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          215                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            18342                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    20.670810                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    23.888889                       # average number of cycles each access was blocked
+system.cpu1.rob.rob_reads                    22401053                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   19972727                       # The number of ROB writes
+system.cpu1.timesIdled                         110858                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         625910                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3787862669                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    7942043                       # Number of Instructions Simulated
+system.cpu1.committedOps                      7942043                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.741995                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.741995                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.574055                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.574055                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                11080172                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                6056867                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    49492                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   48750                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 911686                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                198554                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements            93396                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          491.127271                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2362095                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs            93708                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            25.206973                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1032235519500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.127271                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.959233                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.959233                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          312                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          312                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.609375                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         11044469                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        11044469                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1462423                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1462423                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       846221                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        846221                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        29364                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        29364                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        27945                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        27945                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2308644                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2308644                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2308644                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2308644                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       178507                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       178507                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       183677                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       183677                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4603                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         4603                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2762                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2762                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       362184                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        362184                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       362184                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       362184                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2741731463                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2741731463                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7132330313                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   7132330313                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     45481992                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     45481992                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     20461911                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     20461911                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   9874061776                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   9874061776                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   9874061776                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   9874061776                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1640930                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1640930                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1029898                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1029898                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        33967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        33967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        30707                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        30707                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      2670828                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      2670828                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      2670828                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      2670828                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.108784                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.108784                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.178345                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.178345                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.135514                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.135514                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.089947                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.089947                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135607                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.135607                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135607                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.135607                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9880.945470                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9880.945470                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7408.367487                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7408.367487                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       351094                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          268                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            15302                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             15                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    22.944321                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    17.866667                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        93139                       # number of writebacks
-system.cpu1.dcache.writebacks::total            93139                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       164682                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       164682                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       213530                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       213530                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          655                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          655                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       378212                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       378212                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       378212                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       378212                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       102010                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       102010                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        49452                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        49452                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7397                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7397                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         4916                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         4916                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       151462                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       151462                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       151462                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       151462                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1194457513                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1194457513                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1312928589                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1312928589                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     54001007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     54001007                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     26510269                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     26510269                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2507386102                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2507386102                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2507386102                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2507386102                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     24847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     24847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    692513000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    692513000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    717360500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    717360500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.046931                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.046931                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033905                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.033905                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.139690                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.139690                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100734                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100734                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041700                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.041700                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041700                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.041700                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7300.392997                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7300.392997                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5392.650325                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5392.650325                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks        60059                       # number of writebacks
+system.cpu1.dcache.writebacks::total            60059                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       108966                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       108966                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       150714                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       150714                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          427                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          427                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       259680                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       259680                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       259680                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       259680                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        69541                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        69541                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        32963                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        32963                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4176                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4176                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2762                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2762                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       102504                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       102504                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       102504                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       102504                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    829052502                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    829052502                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1081287205                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1081287205                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     31817008                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     31817008                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     14937089                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     14937089                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1910339707                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1910339707                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1910339707                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1910339707                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     24846500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     24846500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    618764500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    618764500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    643611000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    643611000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042379                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042379                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032006                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032006                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.122943                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.122943                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.089947                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.089947                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.038379                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.038379                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.038379                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.038379                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7619.015326                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7619.015326                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5408.069877                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5408.069877                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1415,95 +1420,95 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           306147                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          470.962529                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1618659                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           306656                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             5.278419                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1878409820250                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.962529                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919849                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.919849                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
+system.cpu1.icache.tags.replacements           205003                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          470.613699                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1269898                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           205514                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.179131                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1878408675250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   470.613699                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.919167                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.919167                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          510                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          2241410                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         2241410                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1618659                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1618659                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1618659                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1618659                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1618659                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1618659                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       316046                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       316046                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       316046                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        316046                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       316046                       # number of overall misses
-system.cpu1.icache.overall_misses::total       316046                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4251188208                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4251188208                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4251188208                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4251188208                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4251188208                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4251188208                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1934705                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1934705                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1934705                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1934705                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1934705                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1934705                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.163356                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.163356                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.163356                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.163356                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.163356                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.163356                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13451.169159                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13451.169159                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          528                       # number of cycles access was blocked
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          1687783                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         1687783                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1269898                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1269898                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1269898                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1269898                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1269898                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1269898                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       212310                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       212310                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       212310                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        212310                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       212310                       # number of overall misses
+system.cpu1.icache.overall_misses::total       212310                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2888653039                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   2888653039                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   2888653039                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   2888653039                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   2888653039                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   2888653039                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1482208                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1482208                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1482208                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1482208                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1482208                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1482208                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.143239                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.143239                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.143239                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.143239                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.143239                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.143239                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13605.826570                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13605.826570                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          412                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs               26                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.307692                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.846154                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9341                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         9341                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         9341                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         9341                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         9341                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         9341                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       306705                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       306705                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       306705                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       306705                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       306705                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       306705                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3543296218                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3543296218                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3543296218                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3543296218                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3543296218                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3543296218                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.158528                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.158528                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.158528                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.158528                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6735                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         6735                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         6735                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         6735                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         6735                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         6735                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       205575                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       205575                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       205575                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       205575                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       205575                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       205575                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2403236890                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   2403236890                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2403236890                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   2403236890                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2403236890                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   2403236890                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.138695                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.138695                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.138695                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.138695                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1517,13 +1522,13 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7368                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7368                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55198                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              13646                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               54536                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              12984                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13082                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11756                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -1534,12 +1539,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        41682                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  125132                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        52328                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40360                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83466                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83466                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123826                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47024                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -1550,13 +1555,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        78554                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2740162                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             12437000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        73266                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661672                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661672                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2734938                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             11111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               356000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1576,52 +1581,52 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           406224779                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406222784                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28036000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27376000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42010550                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42026793                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41693                       # number of replacements
-system.iocache.tags.tagsinuse                0.465320                       # Cycle average of tags in use
+system.iocache.tags.replacements                41701                       # number of replacements
+system.iocache.tags.tagsinuse                0.465228                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41709                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41717                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1710336865000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.465320                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.029083                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.029083                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1710337218000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.465228                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.029077                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.029077                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375597                       # Number of tag accesses
+system.iocache.tags.data_accesses              375597                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          181                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              181                       # number of ReadReq misses
 system.iocache.WriteInvalidateReq_misses::tsunami.ide        41552                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total        41552                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::tsunami.ide          173                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
-system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13658910846                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  13658910846                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21134383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21134383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21134383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21134383                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide          181                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               181                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          181                       # number of overall misses
+system.iocache.overall_misses::total              181                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     22038383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22038383                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13652440608                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13652440608                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     22038383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     22038383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     22038383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     22038383                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          181                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            181                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::tsunami.ide        41552                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        41552                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          173                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             173                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          173                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            173                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide          181                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             181                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          181                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            181                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide            1                       # miss rate for WriteInvalidateReq accesses
@@ -1630,40 +1635,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122164.063584                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122164.063584                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        207096                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 121759.022099                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 121759.022099                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121759.022099                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        206720                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                23572                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23552                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.785678                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.777174                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide          181                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          181                       # number of ReadReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        41552                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total        41552                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          173                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11498106946                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11498106946                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     12137383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     12137383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     12137383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     12137383                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide          181                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          181                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          181                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          181                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12625383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12625383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11491649194                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11491649194                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     12625383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     12625383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     12625383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     12625383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1672,189 +1677,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70158.283237                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70158.283237                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 69753.497238                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 69753.497238                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   345011                       # number of replacements
-system.l2c.tags.tagsinuse                65255.839207                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2587062                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   410177                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.307184                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   345072                       # number of replacements
+system.l2c.tags.tagsinuse                65237.196274                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2611817                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   410198                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.367210                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               7093665750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53401.606938                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5320.695867                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6228.167915                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      214.693065                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       90.675422                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.814844                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081187                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.095034                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003276                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001384                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995725                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65166                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2663                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5629                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5286                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51350                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994354                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27100727                       # Number of tag accesses
-system.l2c.tags.data_accesses                27100727                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             808308                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             697381                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             305176                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              93224                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1904089                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          804982                       # number of Writeback hits
-system.l2c.Writeback_hits::total               804982                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             430                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 602                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            51                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            21                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                72                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           137834                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            34568                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172402                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              808308                       # number of demand (read+write) hits
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-system.l2c.ReadReq_misses::cpu1.data              835                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289427                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2863                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1520                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4383                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          730                       # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total             121925                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13868                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.data              8287                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411352                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13868                       # number of overall misses
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-system.l2c.overall_misses::total               411352                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst   1064381750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  17940986000                       # number of ReadReq miss cycles
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-system.l2c.ReadReq_miss_latency::cpu1.data     74847500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    19201570000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1318455                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      8321116                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      9639571                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1217948                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       209991                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      1427939                       # number of SCUpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu1.data    797025966                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10281703044                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1064381750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  27425663078                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.data    871873466                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     29483273044                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1064381750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  27425663078                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    121354750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    871873466                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    29483273044                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         822176                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         970595                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.data          94059                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2193516                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       804982                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           804982                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3035                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1950                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4985                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          781                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::total          1544                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       252307                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        42020                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           294327                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          822176                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1222902                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.data          136079                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2487843                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         822176                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1222902                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total            2487843                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.016867                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.281491                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004924                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.008877                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.131947                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.943328                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.779487                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.879238                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.934699                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.972477                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.953368                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.453705                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.177344                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.414250                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.016867                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.317022                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.060898                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.165345                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.016867                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.317022                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004924                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.060898                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.165345                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76750.919383                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65666.422658                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.data 89637.724551                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 66343.395744                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   460.515194                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5474.418421                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2199.308921                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1668.421918                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   283.006739                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total   970.067255                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82855.145563                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106954.638486                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 84328.095501                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76750.919383                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70741.766110                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 80367.384106                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 105209.782310                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71674.072434                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76750.919383                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70741.766110                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 80367.384106                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 105209.782310                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71674.072434                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1863,8 +1868,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81496                       # number of writebacks
-system.l2c.writebacks::total                    81496                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu0.inst            13                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             4                       # number of ReadReq MSHR hits
@@ -1877,111 +1882,111 @@ system.l2c.overall_mshr_hits::cpu0.inst            13                       # nu
 system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
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-system.l2c.WriteReq_mshr_uncacheable_latency::total   2737842500                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    675896000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4127200000                       # number of overall MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.281490                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008877                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.943328                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.779487                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.879238                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.934699                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.972477                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.953368                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::total     0.414250                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.016852                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.317021                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.data     0.060898                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.016852                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.317021                       # mshr miss rate for overall accesses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.284868                       # average UpgradeReq mshr miss latency
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.557534                       # average SCUpgradeReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::total 59291.252363                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1992,101 +1997,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              296777                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296698                       # Transaction distribution
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-system.membus.trans_dist::WriteResp             13646                       # Transaction distribution
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 system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
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-system.membus.trans_dist::SCUpgradeReq           9480                       # Transaction distribution
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-system.membus.trans_dist::ReadExResp           121466                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           79                       # Transaction distribution
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-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       933549                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       975389                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124812                       # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        78554                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31488576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31567130                       # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1088624                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73266                       # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.l2c.mem_side::total     31574258                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317568                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      5317568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36884698                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            18563                       # Total snoops (count)
-system.membus.snoop_fanout::samples            600049                       # Request fanout histogram
+system.membus.pkt_size::total                36891826                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            10884                       # Total snoops (count)
+system.membus.snoop_fanout::samples            591178                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  600049    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  591178    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              600049                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40411498                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              591178                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            38973998                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1927899500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1927807998                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               99500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              100000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3832783452                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3829664091                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43159450                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43225207                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2231232                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2231137                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13646                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13646                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           804982                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           14411                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          9552                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          23963                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296031                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296031                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           79                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1644513                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3224840                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       613391                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       402307                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5885051                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     52619264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    123882452                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19627904                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     14694726                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              210824346                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           91368                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3390565                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.012306                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.110249                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2228449                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2228352                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             12984                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            12984                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           822515                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        41553                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            9795                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          5388                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          15183                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           301926                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          301926                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           81                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1830333                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3396960                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       411121                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       269188                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5907602                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     58566720                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    131328844                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     13154944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      9749222                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              212799730                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           73699                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3402430                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.012266                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.110070                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                3348840     98.77%     98.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  41725      1.23%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                3360696     98.77%     98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  41734      1.23%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3390565                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4912159072                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3402430                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4987291538                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           706500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3705712969                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4124247177                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5664612723                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        5936070669                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1381251781                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         692182943                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         925874109                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         467054772                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2120,32 +2125,32 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6735                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    170888                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   59399     40.36%     40.36% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.45% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1921      1.31%     41.76% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    339      0.23%     41.99% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  85372     58.01%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              147162                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    58699     49.14%     49.14% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.11%     49.25% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1921      1.61%     50.86% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     339      0.28%     51.14% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   58360     48.86%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               119450                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1860822176500     97.88%     97.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               61176000      0.00%     97.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              541931500      0.03%     97.91% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              152116500      0.01%     97.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            39608995500      2.08%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1901186396000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.988215                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6564                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    186274                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   65832     40.54%     40.54% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1922      1.18%     41.81% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    173      0.11%     41.91% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  94323     58.09%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              162381                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    64799     49.22%     49.22% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.10%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1922      1.46%     50.78% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     173      0.13%     50.91% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   64626     49.09%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               131651                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1859979639500     97.83%     97.83% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               61305500      0.00%     97.84% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              538798500      0.03%     97.86% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               78674500      0.00%     97.87% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            40515747500      2.13%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1901174165500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.984309                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.683596                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811691                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.685156                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810754                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
@@ -2177,60 +2182,60 @@ system.cpu0.kern.syscall::144                       2      0.86%     99.14% # nu
 system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  432      0.28%      0.28% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.28% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.28% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.28% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3241      2.09%      2.37% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.03%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.40% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               140334     90.29%     92.69% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6381      4.11%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.80% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.81% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4436      2.85%     99.66% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 391      0.25%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                155429                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7000                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  266      0.16%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3573      2.09%      2.25% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.28% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               155550     90.98%     93.26% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6382      3.73%     96.99% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.99% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.99% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     97.00% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.00% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4604      2.69%     99.69% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 391      0.23%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                170980                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7167                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1355                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
 system.cpu0.kern.mode_good::kernel               1354                      
 system.cpu0.kern.mode_good::user                 1355                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.193429                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.188921                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.324237                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1899184407000     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2001981000      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.317883                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1899194834000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1979323500      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3242                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3574                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2589                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     70429                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   23508     38.03%     38.03% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1920      3.11%     41.14% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    432      0.70%     41.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  35949     58.16%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               61809                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    22831     47.98%     47.98% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1920      4.04%     52.02% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     432      0.91%     52.93% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   22399     47.07%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                47582                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1869145937500     98.33%     98.33% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              530408500      0.03%     98.36% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              194479500      0.01%     98.37% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            30989632500      1.63%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1900860458000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.971201                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2428                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     53091                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   16423     36.25%     36.25% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1920      4.24%     40.49% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    266      0.59%     41.08% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  26695     58.92%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               45304                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    16079     47.18%     47.18% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1920      5.63%     52.82% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     266      0.78%     53.60% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   15813     46.40%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                34078                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1870417466500     98.40%     98.40% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              530332500      0.03%     98.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              120265000      0.01%     98.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29780754000      1.57%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900848818000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.979054                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.623077                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.769823                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.592358                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.752207                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
@@ -2246,35 +2251,35 @@ system.cpu1.kern.syscall::74                        9      9.57%     96.81% # nu
 system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  339      0.53%      0.53% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.53% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.53% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1656      2.59%      3.12% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.13% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.14% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                56045     87.56%     90.70% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2366      3.70%     94.40% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.40% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.41% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.41% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3411      5.33%     99.74% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 124      0.19%     99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.07%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  173      0.37%      0.37% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.37% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.38% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  989      2.11%      2.49% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      2.49% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.51% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                40205     85.85%     88.36% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2366      5.05%     93.41% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.41% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     93.42% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.43% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2912      6.22%     99.64% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 124      0.26%     99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 64005                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1702                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 46833                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1197                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                384                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2700                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                740                      
+system.cpu1.kern.mode_switch::idle               2372                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                574                      
 system.cpu1.kern.mode_good::user                  384                      
-system.cpu1.kern.mode_good::idle                  356                      
-system.cpu1.kern.mode_switch_good::kernel     0.434783                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle                  190                      
+system.cpu1.kern.mode_switch_good::kernel     0.479532                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.131852                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.309235                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        6130779500      0.32%      0.32% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           692688500      0.04%      0.36% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1893719133000     99.64%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1657                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.080101                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.290412                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        3852720500      0.20%      0.20% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           690217500      0.04%      0.24% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1895996394000     99.76%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     990                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 44e9b2e2b..aba3b9944 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,113 +1,113 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.859049                       # Number of seconds simulated
-sim_ticks                                1859049148500                       # Number of ticks simulated
-final_tick                               1859049148500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.859045                       # Number of seconds simulated
+sim_ticks                                1859045389000                       # Number of ticks simulated
+final_tick                               1859045389000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168870                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168870                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5931192571                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320216                       # Number of bytes of host memory used
-host_seconds                                   313.44                       # Real time elapsed on the host
-sim_insts                                    52930035                       # Number of instructions simulated
-sim_ops                                      52930035                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 155751                       # Simulator instruction rate (inst/s)
+host_op_rate                                   155751                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5470499619                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 374716                       # Number of bytes of host memory used
+host_seconds                                   339.83                       # Real time elapsed on the host
+sim_insts                                    52929026                       # Number of instructions simulated
+sim_ops                                      52929026                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            967168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24875776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            968128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24876416                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25843904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       967168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          967168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7516224                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7516224                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15112                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388684                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25845504                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       968128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          968128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7516800                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7516800                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15127                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388694                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403811                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117441                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117441                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               520249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13380914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403836                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117450                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117450                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               520766                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13381285                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13901679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          520249                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             520249                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4043047                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4043047                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4043047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              520249                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13380914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13902567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          520766                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             520766                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4043366                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4043366                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4043366                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              520766                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13381285                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17944726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403811                       # Number of read requests accepted
-system.physmem.writeReqs                       158993                       # Number of write requests accepted
-system.physmem.readBursts                      403811                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     158993                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25836928                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10037376                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25843904                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10175552                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2130                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            189                       # Number of requests that are neither read nor write
+system.physmem.bw_total::total               17945933                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403836                       # Number of read requests accepted
+system.physmem.writeReqs                       159002                       # Number of write requests accepted
+system.physmem.readBursts                      403836                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     159002                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25838848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10042304                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25845504                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10176128                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2068                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            208                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               25744                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25560                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25512                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25342                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25388                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24802                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25022                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25128                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24929                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25033                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25435                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24778                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24542                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25239                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25649                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25599                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10531                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10049                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10576                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9740                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9614                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9115                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9087                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8933                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9694                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8895                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9699                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9449                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              10004                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25557                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25510                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25348                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25387                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24799                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25027                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25129                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24928                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25032                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25436                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24784                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24551                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25235                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25659                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25606                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10485                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10108                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10574                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9632                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9668                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9137                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9064                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8900                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9821                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8750                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9677                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9460                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10019                       # Per bank write bursts
 system.physmem.perBankWrBursts::13              10709                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10413                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              10326                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10502                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10405                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1859043836000                       # Total gap between requests
+system.physmem.totGap                    1859040142000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403811                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403836                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 158993                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    314947                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 159002                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    314988                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                     37560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     42912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     42944                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
@@ -148,120 +148,119 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    11173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    12066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1972                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5463                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    11213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      313                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::37                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      117                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::49                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        63789                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      562.390130                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     348.747922                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     419.715872                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13502     21.17%     21.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10319     16.18%     37.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4795      7.52%     44.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2857      4.48%     49.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2332      3.66%     53.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1655      2.59%     55.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1501      2.35%     57.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1587      2.49%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25241     39.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          63789                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5661                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.309309                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2806.420357                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5658     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63696                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      563.318764                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     349.809758                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.596932                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13378     21.00%     21.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10306     16.18%     37.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4860      7.63%     44.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2855      4.48%     49.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2272      3.57%     52.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1671      2.62%     55.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1518      2.38%     57.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1616      2.54%     60.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25220     39.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63696                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5671                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.190619                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2803.945627                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5668     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5661                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5661                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        27.704293                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.909682                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       34.456612                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4621     81.63%     81.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             191      3.37%     85.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             281      4.96%     89.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              54      0.95%     90.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              96      1.70%     92.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              48      0.85%     93.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              17      0.30%     93.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              14      0.25%     94.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              19      0.34%     94.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.09%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103             15      0.26%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             4      0.07%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             5      0.09%     94.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             2      0.04%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            19      0.34%     95.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            42      0.74%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            21      0.37%     96.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            11      0.19%     96.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            96      1.70%     98.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            35      0.62%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            14      0.25%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            13      0.23%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199            10      0.18%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             5      0.09%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             5      0.09%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             2      0.04%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             5      0.09%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             6      0.11%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             2      0.04%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-295             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5661                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3666880250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11236292750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018510000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9083.14                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5671                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5671                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.669018                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.928355                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       34.069194                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4623     81.52%     81.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             171      3.02%     84.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             302      5.33%     89.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              63      1.11%     90.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              97      1.71%     92.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              43      0.76%     93.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              19      0.34%     93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               6      0.11%     93.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              22      0.39%     94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               4      0.07%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             17      0.30%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.07%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            14      0.25%     94.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             6      0.11%     95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            18      0.32%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            43      0.76%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             8      0.14%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            17      0.30%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            89      1.57%     98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            36      0.63%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            17      0.30%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            22      0.39%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            13      0.23%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             4      0.07%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             3      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             5      0.09%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5671                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3621320000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11191295000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018660000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8969.61                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27833.14                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27719.61                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           5.40                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.90                       # Average system read bandwidth in MiByte/s
@@ -270,67 +269,72 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.04                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.92                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     364667                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    132080                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3303181.63                       # Average gap between requests
-system.physmem.pageHitRate                      88.62                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1760890123500                       # Time in different power states
-system.physmem.memoryStateTime::REF       62077600000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       36077600250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 239795640                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 242449200                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 130840875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 132288750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1579484400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1569391200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               503139600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               513144720                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          121423785600                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          121423785600                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           55719498420                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           55486362150                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1066550433000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1066754938500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1246146977535                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1246122360120                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             670.315549                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.302307                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                17761302                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15456576                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            379954                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12009119                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5937139                       # Number of BTB hits
+system.physmem.avgRdQLen                         1.76                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364717                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    132230                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.34                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.26                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3302975.53                       # Average gap between requests
+system.physmem.pageHitRate                      88.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  239009400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  130411875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1579507800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                502640640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           121423785600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            55671864660                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1066592208750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1246139428725                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.311493                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1774205493250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62077600000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     22762216750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  242532360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  132334125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1569601800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                514142640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           121423785600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            55569327930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1066682161500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1246133885955                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.308507                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1774360012750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62077600000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     22607711000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                17755011                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15447257                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            380557                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11928628                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5915753                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             49.438589                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  914399                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21305                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             49.592904                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  917507                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21428                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10308188                       # DTB read hits
-system.cpu.dtb.read_misses                      41379                       # DTB read misses
-system.cpu.dtb.read_acv                           521                       # DTB read access violations
-system.cpu.dtb.read_accesses                   967155                       # DTB read accesses
-system.cpu.dtb.write_hits                     6646702                       # DTB write hits
-system.cpu.dtb.write_misses                      9325                       # DTB write misses
-system.cpu.dtb.write_acv                          410                       # DTB write access violations
-system.cpu.dtb.write_accesses                  342603                       # DTB write accesses
-system.cpu.dtb.data_hits                     16954890                       # DTB hits
-system.cpu.dtb.data_misses                      50704                       # DTB misses
-system.cpu.dtb.data_acv                           931                       # DTB access violations
-system.cpu.dtb.data_accesses                  1309758                       # DTB accesses
-system.cpu.itb.fetch_hits                     1770443                       # ITB hits
-system.cpu.itb.fetch_misses                     36092                       # ITB misses
-system.cpu.itb.fetch_acv                          664                       # ITB acv
-system.cpu.itb.fetch_accesses                 1806535                       # ITB accesses
+system.cpu.dtb.read_hits                     10297861                       # DTB read hits
+system.cpu.dtb.read_misses                      41459                       # DTB read misses
+system.cpu.dtb.read_acv                           502                       # DTB read access violations
+system.cpu.dtb.read_accesses                   968382                       # DTB read accesses
+system.cpu.dtb.write_hits                     6648165                       # DTB write hits
+system.cpu.dtb.write_misses                      9537                       # DTB write misses
+system.cpu.dtb.write_acv                          407                       # DTB write access violations
+system.cpu.dtb.write_accesses                  342637                       # DTB write accesses
+system.cpu.dtb.data_hits                     16946026                       # DTB hits
+system.cpu.dtb.data_misses                      50996                       # DTB misses
+system.cpu.dtb.data_acv                           909                       # DTB access violations
+system.cpu.dtb.data_accesses                  1311019                       # DTB accesses
+system.cpu.itb.fetch_hits                     1769037                       # ITB hits
+system.cpu.itb.fetch_misses                     35976                       # ITB misses
+system.cpu.itb.fetch_acv                          675                       # ITB acv
+system.cpu.itb.fetch_accesses                 1805013                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -343,256 +347,256 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        118298016                       # number of cpu cycles simulated
+system.cpu.numCycles                        118253854                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29541198                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       78055768                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17761302                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6851538                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      80476428                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1253224                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1384                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                28562                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1737629                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       451562                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          217                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9019799                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                273133                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           29528041                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78024704                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17755011                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6833260                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80443267                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1255548                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1917                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1737879                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       457742                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          201                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9020958                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                272859                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          112863592                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.691594                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.010851                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples          112824612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.691557                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.011053                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 98289284     87.09%     87.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   935566      0.83%     87.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1976201      1.75%     89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   911928      0.81%     90.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2795335      2.48%     92.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   642698      0.57%     93.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   727750      0.64%     94.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1007954      0.89%     95.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5576876      4.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 98261708     87.09%     87.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   933543      0.83%     87.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1973411      1.75%     89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   908515      0.81%     90.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2794922      2.48%     92.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   638903      0.57%     93.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   728605      0.65%     94.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1007079      0.89%     95.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5577926      4.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            112863592                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.150140                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.659823                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24058379                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              76821722                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9496623                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1902660                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 584207                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               588094                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42817                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68303161                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                133250                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 584207                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24982800                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                47259981                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20734687                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10387203                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8914712                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65869472                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                202922                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2041149                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 141248                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4766165                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43946104                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79818079                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79637315                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168311                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38139253                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5806843                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1691151                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         241440                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13536828                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10424364                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6928356                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1483959                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1059889                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58630025                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2138995                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57603342                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             50950                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7503583                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3485287                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1477804                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     112863592                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.510380                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.252962                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            112824612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.150143                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.659807                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24062318                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              76790103                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9490656                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1896068                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 585466                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               586954                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42767                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68209057                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                130935                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 585466                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24987088                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                47248716                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20734654                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10372019                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8896667                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65782894                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                200446                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2040001                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 143212                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4746299                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43863584                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79748694                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79567373                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168869                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38138490                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5725086                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1691130                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         241601                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13583154                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10423192                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6953251                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1496634                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1073096                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58558441                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2136854                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57535876                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             59225                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7428094                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3503981                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1475675                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     112824612                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.509959                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.252016                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            89383207     79.20%     79.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10013548      8.87%     88.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4301377      3.81%     91.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             2962557      2.62%     94.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3086274      2.73%     97.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1586017      1.41%     98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1012124      0.90%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              396460      0.35%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              122028      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            89346173     79.19%     79.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10029271      8.89%     88.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4305402      3.82%     91.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             2956038      2.62%     94.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3073019      2.72%     97.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1592834      1.41%     98.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1003723      0.89%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              396113      0.35%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              122039      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       112863592                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       112824612                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  213045     18.77%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 547519     48.24%     67.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                374446     32.99%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  206156     18.23%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 547934     48.46%     66.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                376604     33.31%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39102059     67.88%     67.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61815      0.11%     68.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38377      0.07%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10718615     18.61%     86.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6722522     11.67%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949032      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39037949     67.85%     67.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61847      0.11%     67.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38375      0.07%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10709010     18.61%     86.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6728743     11.69%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949030      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57603342                       # Type of FU issued
-system.cpu.iq.rate                           0.486934                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1135010                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019704                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          228544022                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67957775                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55921178                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              712213                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             334464                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       328973                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58348779                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  382287                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           639736                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57535876                       # Type of FU issued
+system.cpu.iq.rate                           0.486545                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1130694                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019652                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          228371695                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          67806986                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55854530                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              714587                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336328                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       329574                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58275622                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  383662                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           641458                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1339690                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4038                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20047                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       554552                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1338736                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3932                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20392                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       579549                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18285                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        544771                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18260                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        537508                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 584207                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                44318330                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                613096                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64473181                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            145267                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10424364                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6928356                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1890724                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  42751                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                366947                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20047                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         190952                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       410451                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               601403                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              57018878                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10377294                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            584463                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 585466                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                44292826                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                620223                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64391845                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            145304                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10423192                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6953251                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1888969                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  42563                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                374293                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20392                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         192990                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       410068                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               603058                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56949005                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10367007                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            586870                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3704161                       # number of nop insts executed
-system.cpu.iew.exec_refs                     17048455                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8982580                       # Number of branches executed
-system.cpu.iew.exec_stores                    6671161                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.481994                       # Inst execution rate
-system.cpu.iew.wb_sent                       56384919                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56250151                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28947314                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  40326252                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3696550                       # number of nop insts executed
+system.cpu.iew.exec_refs                     17039818                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8972525                       # Number of branches executed
+system.cpu.iew.exec_stores                    6672811                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.481583                       # Inst execution rate
+system.cpu.iew.wb_sent                       56323297                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56184104                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28889312                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  40263081                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.475495                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.717828                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.475114                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717514                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8239076                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661191                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            548552                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    111427799                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.503633                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.455266                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         8158001                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661179                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            549251                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    111396128                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.503767                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.456242                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     91796177     82.38%     82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7808087      7.01%     89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4129534      3.71%     93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2155296      1.93%     95.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1855711      1.67%     96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615462      0.55%     97.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       470761      0.42%     97.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       513166      0.46%     98.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2083605      1.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     91779533     82.39%     82.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7802293      7.00%     89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4122327      3.70%     93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2151634      1.93%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1854051      1.66%     96.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       612708      0.55%     97.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       470628      0.42%     97.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       511278      0.46%     98.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2091676      1.88%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    111427799                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56118765                       # Number of instructions committed
-system.cpu.commit.committedOps               56118765                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    111396128                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56117715                       # Number of instructions committed
+system.cpu.commit.committedOps               56117715                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15458478                       # Number of memory references committed
-system.cpu.commit.loads                       9084674                       # Number of loads committed
-system.cpu.commit.membars                      226351                       # Number of memory barriers committed
-system.cpu.commit.branches                    8434924                       # Number of branches committed
-system.cpu.commit.fp_insts                     324518                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  51970227                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               739937                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3196003      5.70%      5.70% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36180557     64.47%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60666      0.11%     70.27% # Class of committed instruction
+system.cpu.commit.refs                       15458158                       # Number of memory references committed
+system.cpu.commit.loads                       9084456                       # Number of loads committed
+system.cpu.commit.membars                      226347                       # Number of memory barriers committed
+system.cpu.commit.branches                    8434758                       # Number of branches committed
+system.cpu.commit.fp_insts                     324451                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  51969244                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               739915                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3195962      5.70%      5.70% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36179881     64.47%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60661      0.11%     70.27% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.27% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd          38089      0.07%     70.34% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd          38087      0.07%     70.34% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.34% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     70.34% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatMult             0      0.00%     70.34% # Class of committed instruction
@@ -618,192 +622,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9311025     16.59%     86.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6379757     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949032      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9310803     16.59%     86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6379655     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949030      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56118765                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2083605                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total          56117715                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2091676                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    173452486                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130147702                       # The number of ROB writes
-system.cpu.timesIdled                          575947                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5434424                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3599800282                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52930035                       # Number of Instructions Simulated
-system.cpu.committedOps                      52930035                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.234988                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.234988                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.447430                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.447430                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74659793                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40587610                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166949                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167607                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2029497                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939434                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1404580                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994645                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11874772                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1405092                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.451242                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    173330307                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129976168                       # The number of ROB writes
+system.cpu.timesIdled                          574999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5429242                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3599836925                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52929026                       # Number of Instructions Simulated
+system.cpu.committedOps                      52929026                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.234197                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.234197                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.447588                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.447588                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74582639                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40531859                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    167323                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167888                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2030592                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939419                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1404198                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994647                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11876238                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1404710                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.454584                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          25219000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994645                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994647                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          413                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63937777                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63937777                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7284414                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7284414                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4188003                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4188003                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186359                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186359                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215726                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215726                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11472417                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11472417                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11472417                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11472417                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1780024                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1780024                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1955346                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1955346                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23271                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23271                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses          63918355                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63918355                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7286393                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7286393                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4187319                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4187319                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186500                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186500                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215720                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215720                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11473712                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11473712                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11473712                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11473712                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1773211                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1773211                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1955934                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1955934                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23306                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23306                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data           28                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total           28                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3735370                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3735370                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3735370                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3735370                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  39520730746                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  39520730746                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  78084026192                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  78084026192                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    364876749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    364876749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       441006                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       441006                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 117604756938                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 117604756938                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 117604756938                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 117604756938                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9064438                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9064438                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6143349                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6143349                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209630                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209630                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215754                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215754                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15207787                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15207787                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15207787                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15207787                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.196374                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.196374                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318287                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318287                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111010                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111010                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      3729145                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3729145                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3729145                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3729145                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  39410540501                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  39410540501                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  77932908678                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  77932908678                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    363692999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    363692999                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       466008                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       466008                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 117343449179                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 117343449179                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 117343449179                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 117343449179                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9059604                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9059604                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6143253                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6143253                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209806                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209806                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215748                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215748                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15202857                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15202857                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15202857                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15202857                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.195727                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.195727                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318387                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318387                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111084                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111084                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000130                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000130                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.245622                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.245622                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.245622                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.245622                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31484.098480                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31484.098480                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      3992388                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1705                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            180260                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              24                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.147942                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    71.041667                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.245292                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.245292                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.245292                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.245292                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31466.582602                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31466.582602                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      3975824                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1887                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            179816                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    22.110513                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    82.043478                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842675                       # number of writebacks
-system.cpu.dcache.writebacks::total            842675                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       683874                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       683874                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664228                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1664228                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5276                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5276                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2348102                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2348102                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2348102                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2348102                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1096150                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1096150                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291118                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       291118                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17995                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17995                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       842396                       # number of writebacks
+system.cpu.dcache.writebacks::total            842396                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       677447                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       677447                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1664842                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1664842                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5278                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5278                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2342289                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2342289                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2342289                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2342289                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1095764                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1095764                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       291092                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       291092                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18028                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18028                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           28                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total           28                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1387268                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1387268                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1387268                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1387268                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27519652282                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27519652282                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11779193020                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11779193020                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    204738251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    204738251                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       384994                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       384994                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39298845302                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  39298845302                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39298845302                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  39298845302                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423580000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423580000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1999637498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1999637498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3423217498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3423217498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120929                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120929                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047388                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047388                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085842                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085842                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1386856                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1386856                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1386856                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1386856                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27504145773                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27504145773                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11747551273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11747551273                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205106501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205106501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       409992                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       409992                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39251697046                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  39251697046                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39251697046                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  39251697046                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423712500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423712500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1999632498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1999632498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3423344998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3423344998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047384                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047384                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085927                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085927                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000130                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000130                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091221                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091221                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091221                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091223                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091223                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091223                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091223                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -811,213 +815,213 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1035530                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.402349                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7932375                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1036038                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.656452                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26422155250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.402349                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994926                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994926                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1034381                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.395054                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7933874                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1034889                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.666401                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26421984250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.395054                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994912                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994912                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10056088                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10056088                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7932376                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7932376                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7932376                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7932376                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7932376                       # number of overall hits
-system.cpu.icache.overall_hits::total         7932376                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1087421                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1087421                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1087421                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1087421                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1087421                       # number of overall misses
-system.cpu.icache.overall_misses::total       1087421                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15131971529                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15131971529                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15131971529                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15131971529                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15131971529                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15131971529                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9019797                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9019797                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9019797                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9019797                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9019797                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9019797                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120559                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.120559                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.120559                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.120559                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.120559                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.120559                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13915.467449                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13915.467449                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5307                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10056110                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10056110                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7933875                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7933875                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7933875                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7933875                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7933875                       # number of overall hits
+system.cpu.icache.overall_hits::total         7933875                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1087081                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1087081                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1087081                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1087081                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1087081                       # number of overall misses
+system.cpu.icache.overall_misses::total       1087081                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15110067823                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15110067823                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15110067823                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15110067823                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15110067823                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15110067823                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9020956                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9020956                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9020956                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9020956                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9020956                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9020956                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.120506                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.120506                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.120506                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.120506                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.120506                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.120506                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13899.670607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13899.670607                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         3991                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    26.142857                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.808743                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        51130                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        51130                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        51130                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        51130                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        51130                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        51130                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1036291                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1036291                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1036291                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1036291                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1036291                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1036291                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12436978135                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12436978135                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12436978135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12436978135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12436978135                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12436978135                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114891                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114891                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114891                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114891                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        51927                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        51927                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        51927                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        51927                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        51927                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1035154                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1035154                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12419429847                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12419429847                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12419429847                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12419429847                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12419429847                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12419429847                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114750                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114750                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114750                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.114750                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114750                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.114750                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338304                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65336.722890                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2576408                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403470                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.385625                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           338332                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65337.269998                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2574624                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403501                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.380713                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       5538371750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5341.050861                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6255.313222                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.820013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081498                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095449                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996959                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65166                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          494                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3497                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3329                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55432                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994354                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26978409                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26978409                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1021005                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        1850441                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       842675                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       842675                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           32                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           32                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           22                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           22                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       186561                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       186561                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1021005                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1015997                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2037002                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1021005                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1015997                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2037002                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        15114                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total       288931                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           47                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           47                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            6                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            6                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115372                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115372                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15114                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        404303                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       389189                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404303                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1159992750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17995310250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  19155303000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       355494                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       355494                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        92496                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        92496                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9679121611                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9679121611                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1159992750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27674431861                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28834424611                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1159992750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27674431861                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28834424611                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1036119                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1103253                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2139372                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       842675                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       842675                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           79                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5350.111230                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6273.021020                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.819613                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081636                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095719                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996968                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65169                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          498                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3501                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3328                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2420                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55422                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994400                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26963891                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26963891                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1019836                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       829079                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1848915                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       842396                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       842396                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           31                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           31                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           20                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           20                       # number of SCUpgradeReq hits
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+system.cpu.l2cache.ReadExReq_hits::total       186519                       # number of ReadExReq hits
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+system.cpu.l2cache.overall_hits::total        2035434                       # number of overall hits
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+system.cpu.l2cache.ReadReq_misses::total       288952                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           57                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           57                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            8                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            8                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       115376                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       115376                       # number of ReadExReq misses
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+system.cpu.l2cache.overall_misses::total       404328                       # number of overall misses
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+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       331495                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       331495                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           28                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total           28                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1026,80 +1030,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75929                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277050                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165724                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63767.269302                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1107,43 +1111,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2146647                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2146537                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2145159                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2145056                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       842675                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       842396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        41553                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           88                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq           28                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301933                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301933                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           93                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2072410                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3686471                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5758881                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66311616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143911276                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          210222892                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       42053                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3325984                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.012545                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.111300                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp          116                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       301895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       301895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           86                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2070119                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3685432                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5755551                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66237760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143868972                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          210106732                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       42071                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3324189                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        1.012552                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.111331                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            3284259     98.75%     98.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              41725      1.25%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            3282463     98.74%     98.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              41726      1.26%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3325984                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2497867498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3324189                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2496690997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1558461609                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1556745400                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2189866891                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2189304171                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1216,23 +1220,23 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           406221775                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           406216778                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42010536                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            42011283                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.260575                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.260535                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1709355371000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.260575                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078786                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078786                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1709356303000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.260535                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078783                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078783                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1248,8 +1252,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21133383                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21133383                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13648838856                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  13648838856                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide  13645647112                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  13645647112                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21133383                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21133383                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21133383                       # number of overall miss cycles
@@ -1272,17 +1276,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 122158.283237                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 122158.283237                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 122158.283237                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        206574                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs        206436                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                23538                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                23523                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.776192                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.775921                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1298,8 +1302,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136383                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     12136383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11488062928                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11488062928                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide  11484876678                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  11484876678                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     12136383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     12136383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     12136383                       # number of overall MSHR miss cycles
@@ -1314,60 +1318,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 70152.502890                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              296033                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295940                       # Transaction distribution
+system.membus.trans_dist::ReadReq              296054                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295968                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
-system.membus.trans_dist::Writeback            117441                       # Transaction distribution
+system.membus.trans_dist::Writeback            117450                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              186                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             192                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115233                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115233                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           93                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              203                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             211                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115230                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115230                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           86                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          186                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917416                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917499                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124804                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124804                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1042220                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1042303                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30702400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30746540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30704576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30748716                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5317056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      5317056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36063596                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36065772                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              435                       # Total snoops (count)
-system.membus.snoop_fanout::samples            563522                       # Request fanout histogram
+system.membus.snoop_fanout::samples            563568                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  563522    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  563568    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              563522                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            31470000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              563568                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            31570500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1857946999                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1858044250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              115000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              107000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3754266813                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3754720043                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           43145464                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           43142717                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -1401,28 +1405,28 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6441                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211003                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74662     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6440                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211002                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105561     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105562     57.93%    100.00% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::total               182233                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73295     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73295     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148600                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1817339213500     97.76%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                61863500      0.00%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               521835500      0.03%     97.79% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41125418500      2.21%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1859048331000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1817332157500     97.76%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                61952500      0.00%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               528077500      0.03%     97.79% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             41122369500      2.21%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1859044557000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694338                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815440                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694322                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815429                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1458,10 +1462,10 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4178      2.18%      2.18% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175118     91.22%     93.44% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175118     91.23%     93.44% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6783      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
@@ -1470,20 +1474,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.98% # nu
 system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191963                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5853                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1911                      
-system.cpu.kern.mode_good::user                  1741                      
+system.cpu.kern.callpal::total                 191962                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1743                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1913                      
+system.cpu.kern.mode_good::user                  1743                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326499                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326953                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394468                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29096339500      1.57%      1.57% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2660038000      0.14%      1.71% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827291945500     98.29%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394840                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29081819500      1.56%      1.56% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2655993500      0.14%      1.71% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1827306736000     98.29%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 3aeb0bbf5..b0cdac391 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,131 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.842592                       # Number of seconds simulated
-sim_ticks                                1842592129000                       # Number of ticks simulated
-final_tick                               1842592129000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1842591955000                       # Number of ticks simulated
+final_tick                               1842591955000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 226605                       # Simulator instruction rate (inst/s)
-host_op_rate                                   226605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6393875150                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320256                       # Number of bytes of host memory used
-host_seconds                                   288.18                       # Real time elapsed on the host
-sim_insts                                    65303087                       # Number of instructions simulated
-sim_ops                                      65303087                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 212167                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212167                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5858461865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 373744                       # Number of bytes of host memory used
+host_seconds                                   314.52                       # Real time elapsed on the host
+sim_insts                                    66730424                       # Number of instructions simulated
+sim_ops                                      66730424                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           480640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20073664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           146816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2246336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           292800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2554880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           480192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20072256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           146880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2246976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           294016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2555648                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25796096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       480640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       146816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       292800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          920256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7481536                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7481536                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7510                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            313651                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2294                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             35099                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4575                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39920                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25796928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       480192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       146880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       294016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          921088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7481920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7481920                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7503                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            313629                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2295                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             35109                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4594                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39932                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403064                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116899                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116899                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              260850                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10894253                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               79679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1219117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              158907                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1386568                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403077                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116905                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116905                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              260607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10893489                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1219465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              159567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1386985                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13999895                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         260850                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          79679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         158907                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             499436                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4060332                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4060332                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4060332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             260850                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10894253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              79679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1219117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             158907                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1386568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                14000348                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         260607                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79714                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         159567                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             499887                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4060541                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4060541                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4060541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             260607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10893489                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1219465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             159567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1386985                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18060227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         81903                       # Number of read requests accepted
-system.physmem.writeReqs                        62699                       # Number of write requests accepted
-system.physmem.readBursts                       81903                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      62699                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5240384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   3952512                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5241792                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4012736                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       22                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                     916                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             49                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5341                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4966                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4940                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5071                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5028                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5062                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5140                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5148                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5331                       # Per bank write bursts
+system.physmem.bw_total::total               18060889                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         81945                       # Number of read requests accepted
+system.physmem.writeReqs                        62218                       # Number of write requests accepted
+system.physmem.readBursts                       81945                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      62218                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5243136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   3931008                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5244480                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                3981952                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       21                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                     773                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs             65                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5216                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4952                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4966                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5032                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5011                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5077                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5139                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5153                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5336                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                5012                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5278                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5132                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4684                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5065                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5602                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5081                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                3943                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                3578                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                3780                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4114                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3703                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                3530                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4127                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                3704                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4410                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                3736                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4083                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3942                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3446                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               3846                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4153                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3663                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5284                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5137                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4814                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5083                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5582                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5130                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                3820                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                3672                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                3762                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4075                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3759                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                3520                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4123                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                3706                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4379                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                3471                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               3889                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3981                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3541                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               3879                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4169                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3676                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1841579852500                       # Total gap between requests
+system.physmem.totGap                    1841579678500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   81903                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   81945                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  62699                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     65847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      7163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        23                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  62218                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     65839                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7250                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      7148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1657                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -153,193 +153,216 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        43                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      947                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     3282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     3168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        37                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15                      918                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::32                     2265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       94                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::44                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       45                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        2                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        22200                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      414.094414                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     234.871610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     395.166984                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           6979     31.44%     31.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4758     21.43%     52.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1802      8.12%     60.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1018      4.59%     65.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          909      4.09%     69.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          488      2.20%     71.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          377      1.70%     73.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          379      1.71%     75.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5490     24.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          22200                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2135                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        38.346604                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1004.576162                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2133     99.91%     99.91% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        22279                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      411.784371                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     233.119875                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     394.569349                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7102     31.88%     31.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4721     21.19%     53.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1798      8.07%     61.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1010      4.53%     65.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          955      4.29%     69.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          478      2.15%     72.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          370      1.66%     73.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          364      1.63%     75.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5481     24.60%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          22279                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2129                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        38.475810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1006.180082                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2127     99.91%     99.91% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2135                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2135                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        28.926464                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.717874                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       36.556650                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                42      1.97%      1.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15                3      0.14%      2.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            1647     77.14%     79.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              96      4.50%     83.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             109      5.11%     88.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              21      0.98%     89.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              47      2.20%     92.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              14      0.66%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               5      0.23%     92.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               4      0.19%     93.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87               8      0.37%     93.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              8      0.37%     93.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             2      0.09%     93.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             2      0.09%     94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             1      0.05%     94.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            13      0.61%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            15      0.70%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            12      0.56%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             7      0.33%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            36      1.69%     97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            13      0.61%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             7      0.33%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             7      0.33%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             5      0.23%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.14%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.14%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.05%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.05%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::296-303             1      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2135                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      816878250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2352147000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    409405000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9976.41                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2129                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2129                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        28.850164                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.675931                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       36.499081                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                34      1.60%      1.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.33%      1.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.05%      1.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               1      0.05%      2.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1615     75.86%     77.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              35      1.64%     79.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              10      0.47%     79.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              84      3.95%     83.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              64      3.01%     86.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              45      2.11%     89.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               9      0.42%     89.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.52%     90.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              35      1.64%     91.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.23%     91.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              21      0.99%     92.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.09%     92.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               3      0.14%     93.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.09%     93.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.23%     93.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.05%     93.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.19%     93.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.05%     93.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.14%     93.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.19%     94.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.05%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.05%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.28%     94.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.09%     94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.05%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            15      0.70%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.14%     95.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.09%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.05%     95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.19%     95.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            43      2.02%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.05%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171            11      0.52%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.14%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.14%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.09%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             6      0.28%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             4      0.19%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             5      0.23%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             3      0.14%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             3      0.14%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             3      0.14%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.09%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             1      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2129                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      814366500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2350441500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    409620000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9940.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28726.41                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.15                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28690.51                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.85                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.13                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.85                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         8.28                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      70255                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51184                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.80                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  82.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12735507.48                       # Average gap between requests
-system.physmem.pageHitRate                      84.53                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     1767479155500                       # Time in different power states
-system.physmem.memoryStateTime::REF       61527960000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       13578075750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                  83696760                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                  84135240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  45667875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  45907125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                317428800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                321243000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               197503920                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               202687920                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          120348689760                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          120348689760                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           46124478945                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           45810126225                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1065091037250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1065366785250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1232208503310                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1232179574520                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.738964                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.723264                       # Core power per rank (mW)
+system.physmem.readRowHits                      70260                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50807                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.76                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  82.69                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12774287.98                       # Average gap between requests
+system.physmem.pageHitRate                      84.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   83779920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   45618375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 316258800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                197231760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89126157120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            35724246975                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           802806617250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             928299910200                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.726630                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1309959191250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45565260000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9222216250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                   84649320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   46030875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 322748400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                200782800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89126157120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35431940430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           799831550250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             925043859195                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.972279                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1310405285500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45565260000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      8771812500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4840766                       # DTB read hits
+system.cpu0.dtb.read_hits                     4841130                       # DTB read hits
 system.cpu0.dtb.read_misses                      6162                       # DTB read misses
 system.cpu0.dtb.read_acv                          126                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  429577                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3449248                       # DTB write hits
+system.cpu0.dtb.write_hits                    3448228                       # DTB write hits
 system.cpu0.dtb.write_misses                      688                       # DTB write misses
 system.cpu0.dtb.write_acv                          85                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 165228                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8290014                       # DTB hits
+system.cpu0.dtb.data_hits                     8289358                       # DTB hits
 system.cpu0.dtb.data_misses                      6850                       # DTB misses
 system.cpu0.dtb.data_acv                          211                       # DTB access violations
 system.cpu0.dtb.data_accesses                  594805                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2745005                       # ITB hits
+system.cpu0.itb.fetch_hits                    2744473                       # ITB hits
 system.cpu0.itb.fetch_misses                     3071                       # ITB misses
 system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2748076                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2747544                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -352,87 +375,87 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       930170502                       # number of cpu cycles simulated
+system.cpu0.numCycles                       929111283                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31084978                       # Number of instructions committed
-system.cpu0.committedOps                     31084978                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             28990115                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                165280                       # Number of float alu accesses
-system.cpu0.num_func_calls                     801354                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3884267                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    28990115                       # number of integer instructions
-system.cpu0.num_fp_insts                       165280                       # number of float instructions
-system.cpu0.num_int_register_reads           40144651                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21293303                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               85481                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86924                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8319976                       # number of memory refs
-system.cpu0.num_load_insts                    4862063                       # Number of load instructions
-system.cpu0.num_store_insts                   3457913                       # Number of store instructions
-system.cpu0.num_idle_cycles              907838728.357051                       # Number of idle cycles
-system.cpu0.num_busy_cycles              22331773.642949                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.024008                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.975992                       # Percentage of idle cycles
-system.cpu0.Branches                          4943919                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1583961      5.09%      5.09% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 20486094     65.89%     70.98% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31888      0.10%     71.09% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.09% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12950      0.04%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1606      0.01%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4993462     16.06%     87.19% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3461022     11.13%     98.32% # Class of executed instruction
-system.cpu0.op_class::IprAccess                521056      1.68%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   30392058                       # Number of instructions committed
+system.cpu0.committedOps                     30392058                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             28296981                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                165313                       # Number of float alu accesses
+system.cpu0.num_func_calls                     800920                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3653475                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    28296981                       # number of integer instructions
+system.cpu0.num_fp_insts                       165313                       # number of float instructions
+system.cpu0.num_int_register_reads           38988704                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          20831324                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               85482                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              86956                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8319320                       # number of memory refs
+system.cpu0.num_load_insts                    4862427                       # Number of load instructions
+system.cpu0.num_store_insts                   3456893                       # Number of store instructions
+system.cpu0.num_idle_cycles              905971177.002448                       # Number of idle cycles
+system.cpu0.num_busy_cycles              23140105.997552                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024906                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975094                       # Percentage of idle cycles
+system.cpu0.Branches                          4712544                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1584509      5.21%      5.21% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 19793641     65.11%     70.32% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31883      0.10%     70.43% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     70.43% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12951      0.04%     70.47% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     70.47% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     70.47% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     70.47% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1606      0.01%     70.48% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.48% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4993701     16.43%     86.90% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3459999     11.38%     98.29% # Class of executed instruction
+system.cpu0.op_class::IprAccess                520829      1.71%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  31092039                       # Class of executed instruction
+system.cpu0.op_class::total                  30399119                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6422                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211371                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6424                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211373                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   74797     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105691     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182570                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105693     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182572                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    73430     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   73430     49.30%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               148942                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1819773509500     98.76%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38545500      0.00%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              357643000      0.02%     98.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22421661500      1.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1842591359500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1819763275500     98.76%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38885000      0.00%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              357575500      0.02%     98.78% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22431449500      1.22%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1842591185500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.981724                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694761                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815808                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694748                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815799                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -471,7 +494,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175311     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175313     91.20%     93.41% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
@@ -480,266 +503,266 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # nu
 system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192226                       # number of callpals executed
+system.cpu0.kern.callpal::total                192228                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1740                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1908                      
-system.cpu0.kern.mode_good::user                 1738                      
+system.cpu0.kern.mode_good::kernel               1910                      
+system.cpu0.kern.mode_good::user                 1740                      
 system.cpu0.kern.mode_good::idle                  170                      
-system.cpu0.kern.mode_switch_good::kernel     0.322188                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.322526                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      0.081107                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29639680500      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2561811500      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1810389863000     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.391474                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29641344500      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2562591500      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1810387245000     98.25%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements          1393201                       # number of replacements
+system.cpu0.dcache.tags.replacements          1393017                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997818                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13277254                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393713                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.526534                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           13281490                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393529                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.530831                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   261.608452                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    74.750107                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   175.639259                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.510954                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.145996                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.343045                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   260.752731                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    75.043138                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.201949                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.509283                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.146569                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.344144                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63354718                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63354718                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4014926                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1052133                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2504051                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7571110                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3157714                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       807247                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1357321                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5322282                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114982                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18680                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        50783                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184445                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123850                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20650                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        54829                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199329                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7172640                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1859380                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3861372                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12893392                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7172640                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1859380                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3861372                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12893392                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       712217                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        95395                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       559235                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1366847                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       166399                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        43585                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       617129                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       827113                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9420                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2097                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7598                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19115                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         63366474                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63366474                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4014509                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1053432                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2506621                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7574562                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3156846                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       808200                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1357961                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5323007                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114880                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18791                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        50813                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184484                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123743                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20765                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        54820                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199328                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7171355                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1861632                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3864582                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12897569                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7171355                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1861632                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3864582                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12897569                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       713110                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        94552                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       558128                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1365790                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       166356                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        43595                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       617033                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       826984                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9412                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2104                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7556                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19072                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            8                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       878616                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       138980                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1176364                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2193960                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       878616                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       138980                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1176364                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2193960                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2203388500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9682985565                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11886374065                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1649926260                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19421964168                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  21071890428                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27653250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    126867246                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    154520496                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       104000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       104000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3853314760                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  29104949733                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  32958264493                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3853314760                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  29104949733                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  32958264493                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4727143                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1147528                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3063286                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8937957                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3324113                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       850832                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      1974450                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6149395                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124402                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20777                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58381                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203560                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123852                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20650                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        54837                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199339                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8051256                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      1998360                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5037736                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15087352                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8051256                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      1998360                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5037736                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15087352                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150665                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083131                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182560                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.152926                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050058                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051226                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.312557                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.134503                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075722                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100929                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130145                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093904                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            7                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       879466                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       138147                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1175161                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2192774                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       879466                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       138147                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1175161                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2192774                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2193347250                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9664547340                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11857894590                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1652894510                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19391335975                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  21044230485                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27729500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    125483249                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    153212749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        91000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        91000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3846241760                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  29055883315                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  32902125075                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3846241760                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  29055883315                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  32902125075                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4727619                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1147984                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3064749                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8940352                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3323202                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       851795                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1974994                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6149991                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124292                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203556                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123745                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20765                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        54827                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199337                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8050821                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      1999779                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5039743                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15090343                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8050821                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      1999779                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5039743                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15090343                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150839                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.082364                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182112                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152767                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.050059                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.051180                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.312423                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.134469                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075725                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100694                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.129452                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.093694                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000016                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000146                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000050                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109128                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069547                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.233510                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.145417                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109128                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069547                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.233510                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.145417                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23097.526076                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17314.698767                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8696.199403                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37855.369049                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31471.481924                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25476.434814                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13187.052933                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16697.452751                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8083.729846                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000128                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000045                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109239                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069081                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.233179                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.145310                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109239                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069081                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.233179                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.145310                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8682.077472                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8033.386588                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        10400                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27725.678227                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24741.448848                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15022.272281                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27725.678227                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24741.448848                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15022.272281                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       825872                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          866                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            61038                       # number of cycles access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       825255                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         1343                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            61465                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.530456                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    96.222222                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.426422                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   149.222222                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835902                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835902                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       293112                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       293112                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       524642                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       524642                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1568                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1568                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       817754                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       817754                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       817754                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       817754                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95395                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       266123                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       361518                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43585                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        92487                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       136072                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2097                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6030                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8127                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       138980                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       358610                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       497590                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       138980                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       358610                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       497590                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2005063500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4453995148                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6459058648                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1554433740                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2785719201                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4340152941                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23457750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72881252                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96339002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        88000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        88000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3559497240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7239714349                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10799211589                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3559497240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7239714349                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10799211589                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    248461000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342715000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    591176000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    319650500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    420043000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    739693500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    568111500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    762758000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1330869500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083131                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086875                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040447                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051226                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.046842                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022128                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100929                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.103287                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.039924                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000146                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069547                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071185                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032981                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069547                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071185                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032981                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       835667                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835667                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       292188                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       292188                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       524505                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       524505                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1570                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1570                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       816693                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       816693                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       816693                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       816693                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        94552                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       265940                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       360492                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43595                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        92528                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       136123                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2104                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5986                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8090                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       138147                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       358468                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       496615                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       138147                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       358468                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       496615                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1996702750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4449426882                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6446129632                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1557368490                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2781486410                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4338854900                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     23520500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     72740751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96261251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        77000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        77000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3554071240                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7230913292                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10784984532                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3554071240                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7230913292                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10784984532                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    249355000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    342279000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    591634000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    320316500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    419818000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    740134500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    569671500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    762097000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1331768500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.082364                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086774                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.040322                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.051180                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.046850                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022134                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100694                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.102554                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.039743                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000128                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069081                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.071128                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032909                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069081                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.071128                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032909                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21703.031791                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -750,163 +773,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           964194                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.195402                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           40365438                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           964705                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            41.842261                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10190503250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.118461                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    67.369800                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   180.707141                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.513903                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131582                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.352944                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998429                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           964323                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.193139                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           39678129                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           964834                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            41.124306                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10191163250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.937948                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.959779                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   181.295411                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.515504                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.128828                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.354093                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998424                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42311419                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42311419                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30577752                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7329263                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2458423                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       40365438                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     30577752                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7329263                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2458423                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        40365438                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     30577752                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7329263                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2458423                       # number of overall hits
-system.cpu0.icache.overall_hits::total       40365438                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       514287                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       123865                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       342932                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       981084                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       514287                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       123865                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       342932                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        981084                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       514287                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       123865                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       342932                       # number of overall misses
-system.cpu0.icache.overall_misses::total       981084                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1766313750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4813307095                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6579620845                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1766313750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4813307095                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6579620845                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1766313750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4813307095                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6579620845                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     31092039                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7453128                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2801355                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41346522                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     31092039                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7453128                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2801355                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41346522                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     31092039                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7453128                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2801355                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41346522                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016541                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016619                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122416                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023728                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016541                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016619                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122416                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023728                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016541                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016619                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122416                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023728                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14259.990716                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14035.747889                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6706.480633                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14259.990716                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14035.747889                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6706.480633                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14259.990716                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14035.747889                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6706.480633                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3823                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         41624427                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        41624427                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29884884                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7331949                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2461296                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       39678129                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29884884                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7331949                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2461296                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        39678129                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29884884                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7331949                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2461296                       # number of overall hits
+system.cpu0.icache.overall_hits::total       39678129                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       514235                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       124188                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       342842                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       981265                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       514235                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       124188                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       342842                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        981265                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       514235                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       124188                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       342842                       # number of overall misses
+system.cpu0.icache.overall_misses::total       981265                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1771676000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4819389197                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6591065197                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1771676000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4819389197                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6591065197                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1771676000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4819389197                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6591065197                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30399119                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7456137                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2804138                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40659394                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30399119                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7456137                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2804138                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     40659394                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30399119                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7456137                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2804138                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40659394                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016916                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016656                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122263                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.024134                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016916                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016656                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122263                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.024134                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016916                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016656                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122263                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.024134                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.080459                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14057.172683                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6716.906439                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.080459                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14057.172683                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6716.906439                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.080459                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14057.172683                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6716.906439                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         2709                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              153                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.892216                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.705882                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16187                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16187                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16187                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16187                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16187                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16187                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       123865                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       326745                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       450610                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       123865                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       326745                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       450610                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       123865                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       326745                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       450610                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1517675250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3982959026                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5500634276                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1517675250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3982959026                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5500634276                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1517675250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3982959026                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5500634276                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010898                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010898                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016619                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116638                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010898                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12207.084343                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12207.084343                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12252.656118                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12189.808646                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12207.084343                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16232                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16232                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16232                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16232                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16232                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16232                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       124188                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       326610                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       450798                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       124188                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       326610                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       450798                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       124188                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       326610                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       450798                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1522394000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3982795175                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5505189175                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1522394000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3982795175                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5505189175                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1522394000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3982795175                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5505189175                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016656                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116474                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011087                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016656                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116474                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011087                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016656                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116474                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011087                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1166206                       # DTB read hits
+system.cpu1.dtb.read_hits                     1166781                       # DTB read hits
 system.cpu1.dtb.read_misses                      1314                       # DTB read misses
 system.cpu1.dtb.read_acv                           34                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  141633                       # DTB read accesses
-system.cpu1.dtb.write_hits                     871808                       # DTB write hits
+system.cpu1.dtb.write_hits                     872888                       # DTB write hits
 system.cpu1.dtb.write_misses                      168                       # DTB write misses
 system.cpu1.dtb.write_acv                          22                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  57088                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2038014                       # DTB hits
+system.cpu1.dtb.data_hits                     2039669                       # DTB hits
 system.cpu1.dtb.data_misses                      1482                       # DTB misses
 system.cpu1.dtb.data_acv                           56                       # DTB access violations
 system.cpu1.dtb.data_accesses                  198721                       # DTB accesses
-system.cpu1.itb.fetch_hits                     847614                       # ITB hits
+system.cpu1.itb.fetch_hits                     848090                       # ITB hits
 system.cpu1.itb.fetch_misses                      662                       # ITB misses
 system.cpu1.itb.fetch_acv                          32                       # ITB acv
-system.cpu1.itb.fetch_accesses                 848276                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 848752                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -919,64 +942,64 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953409628                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953408444                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7451589                       # Number of instructions committed
-system.cpu1.committedOps                      7451589                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              6926409                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 43920                       # Number of float alu accesses
-system.cpu1.num_func_calls                     202937                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       904115                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     6926409                       # number of integer instructions
-system.cpu1.num_fp_insts                        43920                       # number of float instructions
-system.cpu1.num_int_register_reads            9636713                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5051586                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               23745                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24097                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2044932                       # number of memory refs
-system.cpu1.num_load_insts                    1170872                       # Number of load instructions
-system.cpu1.num_store_insts                    874060                       # Number of store instructions
-system.cpu1.num_idle_cycles              925046236.205368                       # Number of idle cycles
-system.cpu1.num_busy_cycles              28363391.794632                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.029749                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.970251                       # Percentage of idle cycles
-system.cpu1.Branches                          1171500                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               399169      5.36%      5.36% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4836084     64.89%     70.24% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8208      0.11%     70.35% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5096      0.07%     70.42% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.42% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.42% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.42% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    810      0.01%     70.43% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.43% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1198833     16.08%     86.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 875271     11.74%     98.26% # Class of executed instruction
-system.cpu1.op_class::IprAccess                129656      1.74%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7454598                       # Number of instructions committed
+system.cpu1.committedOps                      7454598                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              6929268                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 43953                       # Number of float alu accesses
+system.cpu1.num_func_calls                     203515                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       903765                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     6929268                       # number of integer instructions
+system.cpu1.num_fp_insts                        43953                       # number of float instructions
+system.cpu1.num_int_register_reads            9641119                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5054145                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               23746                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24129                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2046592                       # number of memory refs
+system.cpu1.num_load_insts                    1171450                       # Number of load instructions
+system.cpu1.num_store_insts                    875142                       # Number of store instructions
+system.cpu1.num_idle_cycles              924951081.946169                       # Number of idle cycles
+system.cpu1.num_busy_cycles              28457362.053831                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029848                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970152                       # Percentage of idle cycles
+system.cpu1.Branches                          1171881                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               398972      5.35%      5.35% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4837309     64.88%     70.23% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8193      0.11%     70.34% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5097      0.07%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     70.41% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    810      0.01%     70.42% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.42% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1199545     16.09%     86.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 876356     11.75%     98.26% # Class of executed instruction
+system.cpu1.op_class::IprAccess                129854      1.74%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7453127                       # Class of executed instruction
+system.cpu1.op_class::total                   7456136                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -994,35 +1017,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups                8975833                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          8240091                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           125146                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             6986744                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                4884457                       # Number of BTB hits
+system.cpu2.branchPred.lookups                9673449                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          8936896                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           125098                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             7569787                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                5584968                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            69.910347                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 298693                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7800                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            73.779725                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 299823                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7809                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3460113                       # DTB read hits
-system.cpu2.dtb.read_misses                     12059                       # DTB read misses
-system.cpu2.dtb.read_acv                          120                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  225843                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2120785                       # DTB write hits
-system.cpu2.dtb.write_misses                     2578                       # DTB write misses
-system.cpu2.dtb.write_acv                         111                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  84303                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5580898                       # DTB hits
-system.cpu2.dtb.data_misses                     14637                       # DTB misses
-system.cpu2.dtb.data_acv                          231                       # DTB access violations
-system.cpu2.dtb.data_accesses                  310146                       # DTB accesses
-system.cpu2.itb.fetch_hits                     534656                       # ITB hits
-system.cpu2.itb.fetch_misses                     5715                       # ITB misses
-system.cpu2.itb.fetch_acv                         156                       # ITB acv
-system.cpu2.itb.fetch_accesses                 540371                       # ITB accesses
+system.cpu2.dtb.read_hits                     3461968                       # DTB read hits
+system.cpu2.dtb.read_misses                     12174                       # DTB read misses
+system.cpu2.dtb.read_acv                          114                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  224881                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2122047                       # DTB write hits
+system.cpu2.dtb.write_misses                     2563                       # DTB write misses
+system.cpu2.dtb.write_acv                         106                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  83942                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5584015                       # DTB hits
+system.cpu2.dtb.data_misses                     14737                       # DTB misses
+system.cpu2.dtb.data_acv                          220                       # DTB access violations
+system.cpu2.dtb.data_accesses                  308823                       # DTB accesses
+system.cpu2.itb.fetch_hits                     534012                       # ITB hits
+system.cpu2.itb.fetch_misses                     5788                       # ITB misses
+system.cpu2.itb.fetch_acv                         158                       # ITB acv
+system.cpu2.itb.fetch_accesses                 539800                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1035,305 +1058,305 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        29309170                       # number of cpu cycles simulated
+system.cpu2.numCycles                        30013580                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9355872                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      35312418                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    8975833                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           5183150                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     17863271                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 408038                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles           9363383                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      37425902                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    9673449                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           5884791                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     18558568                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 408186                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.TlbCycles                       247                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                9336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1926                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       226509                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        98836                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          360                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2801357                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                93254                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          27760138                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.272055                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.388957                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.MiscStallCycles               10133                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1974                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       231517                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        99918                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          308                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2804138                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                92736                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          28469903                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.314578                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.374234                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                20067804     72.29%     72.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  312324      1.13%     73.42% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  471431      1.70%     75.11% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 3277065     11.80%     86.92% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  832356      3.00%     89.92% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  194310      0.70%     90.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  239050      0.86%     91.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  435621      1.57%     93.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1930177      6.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20072313     70.50%     70.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  312422      1.10%     71.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  471724      1.66%     73.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 3982470     13.99%     87.25% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  833365      2.93%     90.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  193345      0.68%     90.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  238464      0.84%     91.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  434747      1.53%     93.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1931053      6.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            27760138                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.306247                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.204825                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7663207                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             13056286                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  6071971                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               531660                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                191161                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              175121                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13218                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              31964587                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                42189                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                191161                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7944282                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4747926                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6306317                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  6292094                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2032514                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              31148031                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                68690                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                405455                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 57635                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents                961672                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           20857546                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             38489272                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        38429323                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56078                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             18957389                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1900157                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            527032                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         63032                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3906781                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3488819                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2211142                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           463556                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          329659                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  28630875                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             676639                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 28279580                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            16369                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2426454                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1141058                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        483735                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     27760138                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.018712                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.595651                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            28469903                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.322302                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.246966                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7673000                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13050358                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6778876                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               530616                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                191226                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              175016                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13225                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              34075356                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                43360                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                191226                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7953535                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4758129                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6310003                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  6998808                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2012380                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              33260601                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                68695                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                404029                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 57097                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents                943831                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           22264761                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             41311324                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        41251440                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56013                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             20369021                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1895740                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            527174                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         63098                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3903100                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3489643                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2214871                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           462169                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          329723                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  30742037                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             676819                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 30393110                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            17376                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2421658                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1144384                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        483915                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     28469903                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.067552                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.605150                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17419876     62.75%     62.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2765921      9.96%     72.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1372782      4.95%     77.66% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4034544     14.53%     92.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1009748      3.64%     95.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             570537      2.06%     97.89% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             383332      1.38%     99.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             154390      0.56%     99.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              49008      0.18%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17422923     61.20%     61.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2767864      9.72%     70.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1373994      4.83%     75.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4735624     16.63%     92.38% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1013556      3.56%     95.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             570411      2.00%     97.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             382804      1.34%     99.29% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             154533      0.54%     99.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              48194      0.17%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       27760138                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       28469903                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  83197     21.73%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                176333     46.06%     67.80% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               123266     32.20%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  82144     21.47%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                176872     46.24%     67.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               123495     32.29%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             22202311     78.51%     78.52% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21087      0.07%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     78.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20489      0.07%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     78.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3587142     12.68%     91.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2144327      7.58%     98.94% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            300564      1.06%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             24311305     79.99%     80.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21079      0.07%     80.07% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     80.07% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20485      0.07%     80.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     80.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     80.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     80.13% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     80.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3589842     11.81%     91.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2146129      7.06%     99.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            300610      0.99%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              28279580                       # Type of FU issued
-system.cpu2.iq.rate                          0.964871                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     382796                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.013536                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          84465202                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         31620396                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     27707676                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             253261                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            119445                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       116967                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              28524107                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 135829                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          206522                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              30393110                       # Type of FU issued
+system.cpu2.iq.rate                          1.012645                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     382511                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.012585                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          89403074                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         33727235                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     29817840                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             252936                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            119279                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       116815                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              30637549                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 135632                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          205530                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       435956                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1412                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6012                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       178431                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       436638                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1484                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6154                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       181627                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         5029                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       168380                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4994                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       170094                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                191161                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3997544                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               279888                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           30686163                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            51755                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3488819                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2211142                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            602233                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 15645                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               216255                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6012                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         63410                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       133827                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              197237                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             28083451                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3480678                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           196129                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                191226                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3996466                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               295299                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32798710                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            54858                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3489643                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2214871                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            602209                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 15595                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               231865                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6154                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         62873                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       134195                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              197068                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             30195469                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3482644                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           197641                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1378649                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5608668                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 5940571                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2127990                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.958180                       # Inst execution rate
-system.cpu2.iew.wb_sent                      27865492                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     27824643                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 15848860                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 19489990                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1379854                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5611883                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 6643679                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2129239                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.006060                       # Inst execution rate
+system.cpu2.iew.wb_sent                      29976342                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     29934655                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 17254819                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 20895222                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.949349                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.813179                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.997370                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.825778                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2662629                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitSquashedInsts        2658447                       # The number of squashed insts skipped by commit
 system.cpu2.commit.commitNonSpecStalls         192904                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           180156                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     27293607                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.025131                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.859726                       # Number of insts commited each cycle
+system.cpu2.commit.branchMispredicts           180111                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     28004103                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.074728                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.862098                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18211809     66.73%     66.73% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2232896      8.18%     74.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1177901      4.32%     79.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      3741262     13.71%     92.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       541174      1.98%     94.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       200137      0.73%     95.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       164418      0.60%     96.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       176928      0.65%     96.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       847082      3.10%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18216020     65.05%     65.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2235913      7.98%     73.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1176646      4.20%     77.23% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      4445185     15.87%     93.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       540129      1.93%     95.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       200547      0.72%     95.75% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       166033      0.59%     96.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       176455      0.63%     96.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       847175      3.03%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     27293607                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            27979525                       # Number of instructions committed
-system.cpu2.commit.committedOps              27979525                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     28004103                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            30096794                       # Number of instructions committed
+system.cpu2.commit.committedOps              30096794                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5085574                       # Number of memory references committed
-system.cpu2.commit.loads                      3052863                       # Number of loads committed
-system.cpu2.commit.membars                      67982                       # Number of memory barriers committed
-system.cpu2.commit.branches                   5768887                       # Number of branches committed
-system.cpu2.commit.fp_insts                    115191                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 26471742                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              239400                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1215445      4.34%      4.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        21266434     76.01%     80.35% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20635      0.07%     80.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     80.42% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20039      0.07%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.50% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3120845     11.15%     91.65% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2034343      7.27%     98.93% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       300564      1.07%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5086249                       # Number of memory references committed
+system.cpu2.commit.loads                      3053005                       # Number of loads committed
+system.cpu2.commit.membars                      67981                       # Number of memory barriers committed
+system.cpu2.commit.branches                   6474041                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115125                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 28589001                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              239427                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1215466      4.04%      4.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        23382957     77.69%     81.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20643      0.07%     81.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     81.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20037      0.07%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1220      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     81.87% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3120986     10.37%     92.24% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2034876      6.76%     99.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       300609      1.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         27979525                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               847082                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         30096794                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               847175                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    57015033                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   61749251                       # The number of ROB writes
-system.cpu2.timesIdled                         174924                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1549032                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1748451761                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   26766520                       # Number of Instructions Simulated
-system.cpu2.committedOps                     26766520                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.094994                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.094994                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.913247                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.913247                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                36812900                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               19756149                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    70792                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   70904                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                3635366                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                270473                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    59838509                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   65974697                       # The number of ROB writes
+system.cpu2.timesIdled                         175016                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1543677                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1747747743                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   28883768                       # Number of Instructions Simulated
+system.cpu2.committedOps                     28883768                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.039116                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.039116                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.962357                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.962357                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                39632695                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               21162382                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    70702                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   70843                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                4340126                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                270474                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1389,25 +1412,25 @@ system.iobus.reqLayer1.occupancy               102000                       # La
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5523000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5529000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             2073000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           169052512                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           166547212                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9350000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9356000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17532500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17276500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.262652                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.262651                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693890023000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.262652                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         1693890143000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.262651                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.078916                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.078916                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1425,8 +1448,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide      9417462                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total      9417462                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   5715176550                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   5715176550                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide   5628764250                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   5628764250                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide      9417462                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total      9417462                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide      9417462                       # number of overall miss cycles
@@ -1449,17 +1472,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 54436.196532                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 54436.196532                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 54436.196532                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         87544                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs         86158                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 9998                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9840                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.756151                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.755894                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1467,234 +1490,234 @@ system.iocache.writebacks::writebacks           41512                       # nu
 system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17280                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        17280                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide        17024                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        17024                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5776462                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      5776462                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   4816616550                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4816616550                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide   4743516250                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4743516250                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide      5776462                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total      5776462                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide      5776462                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total      5776462                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide     0.409704                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.409704                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278739.383681                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278739.383681                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 82520.885714                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   337552                       # number of replacements
-system.l2c.tags.tagsinuse                65418.667862                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2487006                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402715                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.175598                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337565                       # number of replacements
+system.l2c.tags.tagsinuse                65420.967844                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2486640                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402728                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.174490                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54698.574366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2340.440822                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2723.231256                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      572.328176                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      607.228358                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2274.234670                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2202.630214                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.834634                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_blocks::cpu0.data     2701.186077                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      572.371097                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      609.192683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2285.385373                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2195.901635                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.835044                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1015                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5951                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2685                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55344                       # Occupied blocks per task id
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 system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
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-system.l2c.Writeback_hits::writebacks          835902                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835902                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 26259538                       # Number of tag accesses
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 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
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-system.l2c.Writeback_accesses::total           835902                       # number of Writeback accesses(hits+misses)
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1703,97 +1726,97 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.overall_mshr_miss_rate::cpu1.data     0.249142                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.data     0.109693                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034773                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54217.672799                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54360.553324                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 55680.452710                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20600.800000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20600.800000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55982.467440                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70191.058410                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63740.086024                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55139.083589                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63095.116437                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59652.534196                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61889.821273                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55139.083589                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63109.781421                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63095.116437                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59652.534196                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               75393                       # number of writebacks
+system.l2c.writebacks::total                    75393                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2295                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data        16798                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         4594                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        17926                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           41613                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           29                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           29                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        18360                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        22084                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         40444                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2295                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        35158                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4594                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        40010                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            82057                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2295                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        35158                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4594                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        40010                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           82057                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    143128000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    911545250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    289854250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    972645250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2317172750                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       449026                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       449026                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1030142510                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1544955279                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2575097789                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    143128000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1941687760                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    289854250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2517600529                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4892270539                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    143128000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1941687760                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    289854250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2517600529                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4892270539                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    233455500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    320261000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    553716500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    302243500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    395601500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    697845000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    535699000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    715862500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1251561500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018480                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.173792                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014068                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.066007                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020243                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.805556                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.604167                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.421159                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.237872                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.133576                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018480                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.250681                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014068                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.109791                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034792                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018480                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.250681                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014068                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.109791                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034792                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62365.141612                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54265.105965                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63094.090118                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54258.911637                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55683.866820                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 15483.655172                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 15483.655172                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56107.979847                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69958.127106                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63670.699955                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62365.141612                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55227.480517                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63094.090118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62924.282154                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59620.392398                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59620.392398                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1804,91 +1827,91 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              294926                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294920                       # Transaction distribution
+system.membus.trans_dist::ReadReq              294932                       # Transaction distribution
+system.membus.trans_dist::ReadResp             294926                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9811                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9811                       # Transaction distribution
-system.membus.trans_dist::Writeback            116899                       # Transaction distribution
+system.membus.trans_dist::Writeback            116905                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        41552                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        41552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              147                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              163                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             149                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115717                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115717                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             165                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115724                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115724                       # Transaction distribution
 system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       882240                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       882304                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       916162                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       916226                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124907                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124907                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1041069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1041133                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30632000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30677576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30633216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30678792                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      5323648                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      5323648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                36001224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                36002440                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              140                       # Total snoops (count)
-system.membus.snoop_fanout::samples            562099                       # Request fanout histogram
+system.membus.snoop_fanout::samples            562134                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  562099    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  562134    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              562099                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11803000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              562134                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11832500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           659094000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           654960000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy                8000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          769927201                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          770434435                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           17910500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           17654500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq            2063113                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2063092                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2063004                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2062983                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq              9811                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp             9811                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           835902                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        17280                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              35                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             45                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302718                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302718                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           835667                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        17024                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              48                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             9                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             57                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302779                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302779                       # Transaction distribution
 system.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1929756                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3657397                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5587153                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61750976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142744520                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              204495496                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           41919                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3236289                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.012893                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.112812                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1930013                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3656818                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5586831                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61758720                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142717704                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              204476424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           41934                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3236018                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012894                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.112817                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3194564     98.71%     98.71% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3194293     98.71%     98.71% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                  41725      1.29%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3236289                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2206148499                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3236018                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2201638999                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           247500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2029921963                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2030846564                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2294082992                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2289452792                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 9cf124dc2..16f8b652d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,152 +1,152 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.844427                       # Number of seconds simulated
-sim_ticks                                2844427140500                       # Number of ticks simulated
-final_tick                               2844427140500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.845843                       # Number of seconds simulated
+sim_ticks                                2845842660500                       # Number of ticks simulated
+final_tick                               2845842660500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 150296                       # Simulator instruction rate (inst/s)
-host_op_rate                                   181972                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3416553864                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 612172                       # Number of bytes of host memory used
-host_seconds                                   832.54                       # Real time elapsed on the host
-sim_insts                                   125127935                       # Number of instructions simulated
-sim_ops                                     151499394                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 164712                       # Simulator instruction rate (inst/s)
+host_op_rate                                   199442                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3743328799                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 646452                       # Number of bytes of host memory used
+host_seconds                                   760.24                       # Real time elapsed on the host
+sim_insts                                   125221621                       # Number of instructions simulated
+sim_ops                                     151624712                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        10304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker        10368                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1349820                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     10836800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           503456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      1120064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3007420                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8732480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           774240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       399936                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13821980                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       416640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        27264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          443904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9404288                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12926236                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1722304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       153024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1875328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8977344                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.inst         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.inst            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9422032                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          161                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8995088                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          162                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             21616                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       169325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7890                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        17501                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             47516                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       136445                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             12121                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6249                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                216517                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          146942                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                202521                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          140271                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.inst             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.inst               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               151378                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              474549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3809836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           180                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              176997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       393775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4859319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         146476                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst           9585                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156061                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3306215                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst               6224                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               144707                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst             1056777                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3068504                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              272060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       140533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4542147                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         605200                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53771                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             658971                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3154547                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst               6221                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.inst                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3312453                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3306215                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             480773                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3809836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          180                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             177011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       393775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8171773                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        216517                       # Number of read requests accepted
-system.physmem.writeReqs                       187602                       # Number of write requests accepted
-system.physmem.readBursts                      216517                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     187602                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 13846784                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10304                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  11642944                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  13821980                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               11740368                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      161                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    5664                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          13644                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               13513                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13311                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14548                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               14027                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15548                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               13123                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13508                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               14039                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13183                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13181                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              13142                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11743                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              13238                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              14181                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              13272                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12799                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               11429                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               11725                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               12190                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               11854                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               10909                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               11199                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               11528                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               11643                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               11026                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               11436                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              11468                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              11022                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              11525                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              11398                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10974                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              10595                       # Per bank write bursts
+system.physmem.bw_write::total                3160782                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3154547                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3643                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst            1062998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3068504                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             272074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       140533                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7702929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        202521                       # Number of read requests accepted
+system.physmem.writeReqs                       180931                       # Number of write requests accepted
+system.physmem.readBursts                      202521                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     180931                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12951936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  11206784                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12926236                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11313424                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5797                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          13571                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12806                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12696                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13455                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               13223                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15141                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12251                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12720                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12666                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12396                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12410                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12030                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11077                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12224                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12978                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12239                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12062                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               11243                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               11520                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               11868                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               11342                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10753                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10659                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11197                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10854                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10720                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10780                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10917                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10553                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10892                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10850                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10512                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              10446                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2844424796500                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2845842079500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  215930                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  201934                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 183166                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     79055                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     63481                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     16932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12216                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     10702                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      9369                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      7427                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      6415                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      303                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      206                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      155                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       92                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 176495                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     98520                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     50579                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9843                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6337                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5553                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4965                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4352                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      300                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      250                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -176,173 +176,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8745                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    11015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    12070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    12267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    13080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    12741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    12428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    11920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    12228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    12238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    12014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    11495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    11369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8809                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      332                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        93322                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      273.137395                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     151.655882                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.256113                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45588     48.85%     48.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18736     20.08%     68.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6915      7.41%     76.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3558      3.81%     80.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3108      3.33%     83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2062      2.21%     85.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1352      1.45%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1057      1.13%     88.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10946     11.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          93322                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7762                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.873744                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      521.384620                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7761     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7762                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7762                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.437387                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.920909                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.626862                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6141     79.12%     79.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             490      6.31%     85.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              77      0.99%     86.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             208      2.68%     89.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             144      1.86%     90.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              54      0.70%     91.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              53      0.68%     92.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              34      0.44%     92.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             115      1.48%     94.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.19%     94.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              16      0.21%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.18%     94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              31      0.40%     95.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              17      0.22%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.12%     95.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.31%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              61      0.79%     96.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               9      0.12%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               4      0.05%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               7      0.09%     96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              74      0.95%     97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            12      0.15%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             8      0.10%     98.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            21      0.27%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             7      0.09%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            12      0.15%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             7      0.09%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            28      0.36%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             9      0.12%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.04%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             9      0.12%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             8      0.10%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.04%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             7      0.09%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             5      0.06%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             3      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             3      0.04%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             3      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7762                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7644398000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11701073000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1081780000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       35332.50                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        94139                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      256.627498                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.457232                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     317.924062                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          48795     51.83%     51.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18347     19.49%     71.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6488      6.89%     78.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3770      4.00%     82.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2738      2.91%     85.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1619      1.72%     86.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          964      1.02%     87.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1076      1.14%     89.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10342     10.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          94139                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7479                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.058430                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      520.327968                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7478     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7479                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7479                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.413023                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.870843                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.578889                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            6390     85.44%     85.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             248      3.32%     88.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             198      2.65%     91.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              77      1.03%     92.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             144      1.93%     94.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              30      0.40%     94.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              35      0.47%     95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              33      0.44%     95.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              72      0.96%     96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              21      0.28%     96.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             96      1.28%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            18      0.24%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            22      0.29%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            12      0.16%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            35      0.47%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             4      0.05%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            12      0.16%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             4      0.05%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             8      0.11%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.03%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.05%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.04%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7479                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5783977250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9578489750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1011870000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       28580.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  54082.50                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.87                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.09                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.86                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.13                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47330.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.55                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.94                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     183280                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    121675                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.71                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7038582.19                       # Average gap between requests
-system.physmem.pageHitRate                      76.57                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2710525028500                       # Time in different power states
-system.physmem.memoryStateTime::REF       94981640000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       38919724000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 365533560                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 339980760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 199447875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 185505375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                870612600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                816964200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               599250960                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               579597120                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          185784087840                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          185784087840                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           82151193285                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           81119552850                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1634593377000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1635498324750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1904563503120                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1904324012895                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.577359                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.493163                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     168404                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    114936                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  65.63                       # Row buffer hit rate for writes
+system.physmem.avgGap                      7421638.38                       # Average gap between requests
+system.physmem.pageHitRate                      75.06                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  372813840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  203420250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 818672400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                579545280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185876137200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83421293220                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634324841000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1905596723190                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.608836                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2718714861000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95028700000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32092142750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  338877000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  184903125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 759837000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                555141600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185876137200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82372109895                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635245177250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1905332183070                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.515879                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2720254769500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95028700000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30559102000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1216                       # Number of bytes read from this memory
@@ -352,31 +338,39 @@ system.realview.nvmem.bytes_inst_read::total         1216
 system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          158                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst          157                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst          270                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              428                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          158                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              427                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          157                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst          270                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          428                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          158                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          427                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          157                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          270                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             428                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             427                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               35736686                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         17706973                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1707657                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            20554340                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               14845557                       # Number of BTB hits
+system.cpu0.branchPred.lookups               35059389                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         17250705                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1579435                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            20094508                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               14609065                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.225900                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               10924417                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            815226                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.701780                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               10810171                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            733013                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -398,27 +392,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                    67889                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               67889                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44852                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        23037                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        67889                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          67889    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        67889                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6673                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean  8598.195564                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  7320.525431                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6106.619536                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6491     97.27%     97.27% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          168      2.52%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            6      0.09%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6673                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    287368000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      287368000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    287368000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5164     77.39%     77.39% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1509     22.61%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6673                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67889                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67889                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6673                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6673                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        74562                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24607000                       # DTB read hits
-system.cpu0.dtb.read_misses                     66402                       # DTB read misses
-system.cpu0.dtb.write_hits                   18455953                       # DTB write hits
-system.cpu0.dtb.write_misses                     6655                       # DTB write misses
+system.cpu0.dtb.read_hits                    23969568                       # DTB read hits
+system.cpu0.dtb.read_misses                     61820                       # DTB read misses
+system.cpu0.dtb.write_hits                   17946825                       # DTB write hits
+system.cpu0.dtb.write_misses                     6069                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3808                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1234                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2108                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3496                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1251                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2004                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      615                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24673402                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18462608                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      553                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24031388                       # DTB read accesses
+system.cpu0.dtb.write_accesses               17952894                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         43062953                       # DTB hits
-system.cpu0.dtb.misses                          73057                       # DTB misses
-system.cpu0.dtb.accesses                     43136010                       # DTB accesses
+system.cpu0.dtb.hits                         41916393                       # DTB hits
+system.cpu0.dtb.misses                          67889                       # DTB misses
+system.cpu0.dtb.accesses                     41984282                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -440,8 +473,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    71661808                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4142                       # ITB inst misses
+system.cpu0.itb.walker.walks                     3825                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3825                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          307                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3518                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3825                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3825    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3825                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2419                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean  8874.535345                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  7628.532351                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  4888.994435                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191         1491     61.64%     61.64% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383          888     36.71%     98.35% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575            4      0.17%     98.51% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.45%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2419                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    286941000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      286941000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    286941000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2119     87.60%     87.60% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          300     12.40%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2419                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3825                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3825                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2419                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2419                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6244                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    70462798                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3825                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -450,123 +513,123 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2456                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2222                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     8241                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7291                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                71665950                       # ITB inst accesses
-system.cpu0.itb.hits                         71661808                       # DTB hits
-system.cpu0.itb.misses                           4142                       # DTB misses
-system.cpu0.itb.accesses                     71665950                       # DTB accesses
-system.cpu0.numCycles                       235973632                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                70466623                       # ITB inst accesses
+system.cpu0.itb.hits                         70462798                       # DTB hits
+system.cpu0.itb.misses                           3825                       # DTB misses
+system.cpu0.itb.accesses                     70466623                       # DTB accesses
+system.cpu0.numCycles                       234985394                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  111703770                       # Number of instructions committed
-system.cpu0.committedOps                    135097839                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      8562554                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1855                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5452894525                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.112495                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.473374                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  109265327                       # Number of instructions committed
+system.cpu0.committedOps                    132114239                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8364757                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1821                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5456715361                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.150594                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.464988                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1855                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      199544848                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       36428784                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           751860                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.262864                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           41566353                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           752372                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.247076                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        306713000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   494.262864                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.965357                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.965357                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1824                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      195318282                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       39667112                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           718541                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.305697                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           40476936                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           719053                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            56.292006                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        306903000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   494.305697                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.965441                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.965441                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         86104149                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        86104149                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst     23403701                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23403701                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst     17336391                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      17336391                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       390425                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       390425                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       371566                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       371566                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst     40740092                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        40740092                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst     40740092                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       40740092                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst       564897                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       564897                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst       554409                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       554409                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6644                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6644                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        20340                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20340                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst      1119306                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1119306                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst      1119306                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1119306                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6887885459                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6887885459                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8219762503                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   8219762503                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    108110000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    108110000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    440070983                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    440070983                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       121000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       121000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  15107647962                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  15107647962                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  15107647962                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  15107647962                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23968598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23968598                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17890800                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17890800                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       397069                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       397069                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       391906                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       391906                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst     41859398                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     41859398                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst     41859398                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     41859398                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023568                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.023568                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030988                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.030988                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016733                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016733                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.051900                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051900                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026740                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026740                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026740                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.026740                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         83802985                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        83802985                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst     22808347                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22808347                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst     16863099                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      16863099                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       381264                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       381264                       # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total       362825                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst     39671446                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        39671446                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst     39671446                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       39671446                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst       540080                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       540080                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst       532227                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       532227                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         6489                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6489                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst        19898                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19898                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst      1072307                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1072307                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst      1072307                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1072307                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   6648434719                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6648434719                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst   8319872197                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8319872197                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst    104923750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    104923750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst    438142885                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    438142885                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst       309000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       309000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  14968306916                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  14968306916                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  14968306916                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  14968306916                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst     23348427                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23348427                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst     17395326                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17395326                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       387753                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       387753                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       382723                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       382723                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst     40743753                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     40743753                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst     40743753                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     40743753                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.023131                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.023131                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.030596                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.030596                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.016735                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.016735                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.051991                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051991                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.026318                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026318                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.026318                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.026318                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -575,74 +638,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       541643                       # number of writebacks
-system.cpu0.dcache.writebacks::total           541643                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        45094                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        45094                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       240822                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       240822                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst       285916                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       285916                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst       285916                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       285916                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       519803                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       519803                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       313587                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       313587                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6644                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6644                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        20340                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20340                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst       833390                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       833390                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst       833390                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       833390                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5323715430                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5323715430                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4366940170                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4366940170                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     94806000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94806000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    398879017                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    398879017                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       115000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       115000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9690655600                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9690655600                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9690655600                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   9690655600                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6196262496                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6196262496                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4811489492                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4811489492                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  11007751988                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11007751988                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021687                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021687                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017528                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017528                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016733                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016733                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.051900                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051900                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019909                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.019909                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019909                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.019909                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       523102                       # number of writebacks
+system.cpu0.dcache.writebacks::total           523102                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        42658                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        42658                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       230433                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       230433                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst       273091                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       273091                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst       273091                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       273091                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       497422                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       497422                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       301794                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       301794                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         6489                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6489                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst        19898                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19898                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst       799216                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       799216                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst       799216                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       799216                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   5149793898                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149793898                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   4423706193                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4423706193                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     91926250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     91926250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst    397751115                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    397751115                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst       291000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       291000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9573500091                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9573500091                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9573500091                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9573500091                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6190990749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6190990749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4804555500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4804555500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  10995546249                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10995546249                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.021304                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021304                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.017349                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017349                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.016735                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016735                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.051991                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051991                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.019616                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.019616                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.019616                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.019616                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -650,58 +713,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          2070442                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.797171                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           69582233                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          2070954                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            33.599121                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6297775000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.797171                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999604                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1982441                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.792915                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           68472197                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1982953                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.530419                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6378447750                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.792915                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999596                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999596                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          180                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          106                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        145377375                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       145377375                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     69582233                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       69582233                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     69582233                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        69582233                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     69582233                       # number of overall hits
-system.cpu0.icache.overall_hits::total       69582233                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      2070970                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2070970                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      2070970                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2070970                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      2070970                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2070970                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17258012980                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17258012980                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  17258012980                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17258012980                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  17258012980                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17258012980                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     71653203                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     71653203                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     71653203                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     71653203                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     71653203                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     71653203                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028903                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028903                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028903                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028903                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028903                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028903                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8333.299362                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8333.299362                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8333.299362                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8333.299362                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8333.299362                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8333.299362                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        142893294                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       142893294                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     68472197                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       68472197                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     68472197                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        68472197                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     68472197                       # number of overall hits
+system.cpu0.icache.overall_hits::total       68472197                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1982967                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1982967                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1982967                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1982967                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1982967                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1982967                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18641895952                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  18641895952                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  18641895952                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  18641895952                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  18641895952                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  18641895952                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     70455164                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     70455164                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     70455164                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     70455164                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     70455164                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     70455164                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028145                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028145                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028145                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028145                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028145                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028145                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9401.011692                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9401.011692                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9401.011692                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9401.011692                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9401.011692                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9401.011692                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -710,313 +773,323 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2070970                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      2070970                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      2070970                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      2070970                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      2070970                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      2070970                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  14149699520                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  14149699520                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  14149699520                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  14149699520                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  14149699520                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  14149699520                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    276493750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    276493750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    276493750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    276493750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028903                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028903                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028903                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028903                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6832.401976                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  6832.401976                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6832.401976                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  6832.401976                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1982967                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1982967                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1982967                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1982967                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1982967                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1982967                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  15657207046                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  15657207046                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  15657207046                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  15657207046                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  15657207046                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  15657207046                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    278031000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    278031000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    278031000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    278031000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028145                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028145                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028145                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028145                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7895.848517                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  7895.848517                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7895.848517                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  7895.848517                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     18115074                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       431506                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     17132776                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9283                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         6596                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       534910                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      1383846                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          428439                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16212.256950                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3152645                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          444682                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.089662                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle    2824980212500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4226.197620                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    50.775812                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065487                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2187.555983                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9747.662049                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.257947                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003099                       # Average percentage of cache occupancy
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      2292717                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      2293221                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          436                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage       284211                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          303376                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16141.726832                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           2969035                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          319611                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            9.289527                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle    2825848630000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  6310.295058                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    58.412646                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.063392                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  7791.524761                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1981.430976                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.385150                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003565                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.133518                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.594950                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989518                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8981                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7254                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           61                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          111                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2870                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5529                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          410                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.475557                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.120937                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.985213                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1941                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14280                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          509                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          923                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          497                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3049                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3651                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          230                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.548157                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.442749                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        57799798                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       57799798                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        84149                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4243                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2500411                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       2588803                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       541643                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       541643                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4674                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total         4674                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         2411                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2411                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       234433                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       234433                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        84149                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4243                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      2734844                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2823236                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        84149                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4243                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      2734844                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2823236                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          906                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          138                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        97001                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        98045                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        27960                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27960                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        17929                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        17929                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        46525                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        46525                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          906                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          138                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       143526                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       144570                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          906                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          138                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       143526                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       144570                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     31530500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3231999                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2954004148                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   2988766647                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    497244183                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    497244183                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    356127296                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    356127296                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       112000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       112000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   1936152477                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   1936152477                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     31530500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3231999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4890156625                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   4924919124                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     31530500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3231999                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4890156625                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   4924919124                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        85055                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2597412                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      2686848                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       541643                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       541643                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        32634                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        32634                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        20340                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20340                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       280958                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       280958                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        85055                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4381                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      2878370                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2967806                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        85055                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4381                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      2878370                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2967806                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.037345                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.036491                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.856775                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.856775                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.881465                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.881465                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.165594                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.165594                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.049864                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.048713                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010652                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.031500                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.049864                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.048713                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        25119                       # number of cycles access was blocked
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4022                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7455                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2494                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.118469                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.871582                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        55347065                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       55347065                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        80493                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4332                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      2344344                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total       2429169                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       523100                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       523100                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst         4781                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total         4781                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst         1890                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1890                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       226532                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       226532                       # number of ReadExReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        80493                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4332                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      2570876                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        2655701                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        80493                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4332                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      2570876                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       2655701                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          854                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          113                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst       142527                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total       143494                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst        26406                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26406                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst        18006                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18006                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.inst        44082                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        44082                       # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          854                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          113                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       186609                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       187576                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          854                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          113                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       186609                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       187576                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     30085500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2495499                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   5310554679                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   5343135678                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst    462181513                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    462181513                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst    354964789                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    354964789                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst       282000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       282000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   2099231484                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2099231484                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     30085500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2495499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   7409786163                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   7442367162                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     30085500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2495499                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   7409786163                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   7442367162                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        81347                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4445                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      2486871                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      2572663                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       523100                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       523100                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst        31187                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        31187                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst        19896                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        19896                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst       270614                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       270614                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        81347                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4445                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      2757485                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2843277                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        81347                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4445                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      2757485                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2843277                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.057312                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.055776                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.846699                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.846699                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.905006                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.905006                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.162896                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.162896                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.067674                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.065972                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.010498                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025422                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.067674                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.065972                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37259.990591                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17502.897561                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19713.694824                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst       141000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       141000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 47621.058119                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39707.549813                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39707.549813                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs             346                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    72.598266                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       220063                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          220063                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         8315                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total         8315                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3034                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         3034                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        11349                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        11349                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        11349                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        11349                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          906                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          138                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        88686                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        89730                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       534906                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       534906                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        27960                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27960                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        17929                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17929                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        43491                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        43491                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          906                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          138                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       132177                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       133221                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          906                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          138                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       132177                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       534906                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       668127                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2160848492                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2188282991                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21648732719                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21648732719                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    481473058                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    481473058                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    238593946                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    238593946                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst        91000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        91000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1198815233                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1198815233                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3359663725                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   3387098224                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     25168500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2265999                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3359663725                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21648732719                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  25035830943                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6180670251                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6180670251                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4594924508                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4594924508                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10775594759                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10775594759                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.034144                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.033396                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.writebacks::writebacks       201133                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          201133                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst          511                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          512                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         3265                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         3265                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         3776                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         3777                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         3776                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         3777                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          854                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          112                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       142016                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total       142982                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       280772                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       280772                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst        26406                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26406                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst        18006                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18006                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst        40817                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        40817                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          854                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          112                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       182833                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       183799                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          854                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          112                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       182833                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       280772                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       464571                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   4279514975                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   4305290474                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15488924735                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15488924735                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst    449600763                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    449600763                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst    240569359                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    240569359                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst       219000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       219000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   1467254248                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1467254248                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   5746769223                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   5772544722                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     24090000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1685499                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   5746769223                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15488924735                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  21261469457                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6177076991                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6177076991                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   4588309497                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4588309497                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  10765386488                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10765386488                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.057106                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.055577                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.856775                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.856775                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.881465                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.881465                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.154795                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.154795                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.045921                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.044889                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010652                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.031500                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.045921                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.846699                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.846699                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.905006                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.905006                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.150831                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.150831                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.066304                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.064643                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.010498                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.025197                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.066304                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.225125                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.163393                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst       109500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       109500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1024,67 +1097,75 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       2861093                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2792980                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28855                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28855                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       541643                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       731101                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq       2726808                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2669763                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28813                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28813                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       523100                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       388140                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        68486                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42622                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        93982                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       302729                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       293421                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      4148051                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2491359                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12339                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       183942                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6835691                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    132737600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     90757533                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17524                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       340220                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         223852877                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1093341                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4548807                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.213001                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.409428                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        64720                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42432                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        88655                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       299964                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       286773                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3972081                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2399294                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11788                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       172273                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6555436                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    127106560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     87442327                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17780                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       325388                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         214892055                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     732010                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4046250                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.152317                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.359328                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           3579907     78.70%     78.70% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            968900     21.30%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           3429939     84.77%     84.77% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            616311     15.23%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4548807                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2378574445                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4046250                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    2284841999                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    119537998                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    117254000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   3112636730                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2984852953                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1291088389                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1241569539                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7963988                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7347491                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     98908477                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     90940738                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                3448752                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          1941981                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           196391                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2221819                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1396869                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4088735                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2366310                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           253216                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2663045                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1651600                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            62.870513                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 715789                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             52420                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            62.019230                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 809555                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             58673                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1106,27 +1187,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                    25571                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               25571                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18521                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7050                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        25571                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          25571    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        25571                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2708                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean  8701.256278                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  7631.681902                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5745.938863                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         2093     77.29%     77.29% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383          481     17.76%     95.05% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575           65      2.40%     97.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.07%     99.52% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151            9      0.33%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-90111            4      0.15%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2708                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1108722264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1108722264    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1108722264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1997     73.74%     73.74% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          711     26.26%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2708                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        25571                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        25571                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2708                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2708                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        28279                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3432223                       # DTB read hits
-system.cpu1.dtb.read_misses                     19764                       # DTB read misses
-system.cpu1.dtb.write_hits                    2826731                       # DTB write hits
-system.cpu1.dtb.write_misses                     1392                       # DTB write misses
+system.cpu1.dtb.read_hits                     4075725                       # DTB read hits
+system.cpu1.dtb.read_misses                     23546                       # DTB read misses
+system.cpu1.dtb.write_hits                    3346999                       # DTB write hits
+system.cpu1.dtb.write_misses                     2025                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1674                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      101                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   224                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2069                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      121                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   325                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      209                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3451987                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2828123                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      279                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 4099271                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3349024                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6258954                       # DTB hits
-system.cpu1.dtb.misses                          21156                       # DTB misses
-system.cpu1.dtb.accesses                      6280110                       # DTB accesses
+system.cpu1.dtb.hits                          7422724                       # DTB hits
+system.cpu1.dtb.misses                          25571                       # DTB misses
+system.cpu1.dtb.accesses                      7448295                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1148,8 +1268,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     6653879                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1856                       # ITB inst misses
+system.cpu1.itb.walker.walks                     2243                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2243                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2062                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2243                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2243    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2243                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1122                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean  8831.106061                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  7825.020839                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4777.823788                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095          160     14.26%     14.26% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          676     60.25%     74.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287            3      0.27%     74.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          248     22.10%     96.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     96.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           13      1.16%     98.13% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.69%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1122                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1108154264                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1108154264    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1108154264                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          954     85.03%     85.03% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          168     14.97%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1122                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2243                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2243                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1122                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1122                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         3365                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     7772051                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2243                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1158,122 +1312,122 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     882                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1160                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1128                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1845                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 6655735                       # ITB inst accesses
-system.cpu1.itb.hits                          6653879                       # DTB hits
-system.cpu1.itb.misses                           1856                       # DTB misses
-system.cpu1.itb.accesses                      6655735                       # DTB accesses
-system.cpu1.numCycles                        36145472                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7774294                       # ITB inst accesses
+system.cpu1.itb.hits                          7772051                       # DTB hits
+system.cpu1.itb.misses                           2243                       # DTB misses
+system.cpu1.itb.accesses                      7774294                       # DTB accesses
+system.cpu1.numCycles                        42246986                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   13424165                       # Number of instructions committed
-system.cpu1.committedOps                     16401555                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1287407                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5652095397                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.692568                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.371393                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   15956294                       # Number of instructions committed
+system.cpu1.committedOps                     19510473                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1491389                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2792                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5648821854                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.647669                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.377691                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       26236459                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                        9909013                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           149765                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          476.829408                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5935391                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           150124                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            39.536590                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     107725830000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   476.829408                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.931307                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.931307                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12574886                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12574886                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst      3167382                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3167382                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst      2587127                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2587127                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        79870                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        79870                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        60510                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        60510                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst      5754509                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5754509                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst      5754509                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5754509                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst       151161                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       151161                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst       116953                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       116953                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5079                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         5079                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        22818                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        22818                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst       268114                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        268114                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst       268114                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       268114                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2359046468                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2359046468                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3063915205                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3063915205                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     93260000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     93260000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    534664798                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    534664798                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       106500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       106500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst   5422961673                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   5422961673                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst   5422961673                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   5422961673                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3318543                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3318543                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst      2704080                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2704080                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        84949                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        84949                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        83328                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        83328                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst      6022623                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6022623                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst      6022623                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6022623                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.045550                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.045550                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043251                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.043251                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.059789                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.059789                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.273834                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273834                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.044518                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.044518                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.044518                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044518                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2795                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       30354295                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       11892691                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           187758                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          478.493571                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            7034054                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           188124                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            37.390519                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     108317904000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   478.493571                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.934558                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.934558                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          366                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.714844                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         14914460                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        14914460                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst      3762812                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3762812                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst      3070723                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3070723                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        89288                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        89288                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        69262                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        69262                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst      6833535                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6833535                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst      6833535                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6833535                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst       181434                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       181434                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst       139542                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       139542                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst         5058                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5058                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        23425                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23425                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst       320976                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        320976                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst       320976                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       320976                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   2698134351                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2698134351                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   3673411367                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   3673411367                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     91654251                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     91654251                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst    540931813                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    540931813                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst       185500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       185500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst   6371545718                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6371545718                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst   6371545718                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6371545718                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst      3944246                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3944246                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst      3210265                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      3210265                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        94346                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        94346                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        92687                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92687                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst      7154511                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      7154511                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst      7154511                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      7154511                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.046000                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.046000                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.043467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.043467                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.053611                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.053611                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.252732                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.252732                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.044863                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.044863                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.044863                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044863                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1282,74 +1436,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        93707                       # number of writebacks
-system.cpu1.dcache.writebacks::total            93707                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        11593                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        11593                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        39187                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        39187                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst        50780                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        50780                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst        50780                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        50780                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       139568                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       139568                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        77766                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        77766                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5079                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5079                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        22818                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        22818                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst       217334                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       217334                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst       217334                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       217334                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   1914681986                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1914681986                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   1867013423                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1867013423                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     83091000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83091000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    487833202                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    487833202                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       100500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       100500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   3781695409                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3781695409                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   3781695409                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3781695409                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    327471996                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    327471996                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    198424999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    198424999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    525896995                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    525896995                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042057                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042057                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.028759                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028759                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.059789                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.059789                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.273834                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273834                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.036086                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.036086                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.036086                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.036086                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       113901                       # number of writebacks
+system.cpu1.dcache.writebacks::total           113901                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        15137                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        15137                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        49794                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        49794                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst        64931                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        64931                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst        64931                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        64931                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       166297                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       166297                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst        89748                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        89748                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst         5058                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5058                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        23425                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23425                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst       256045                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       256045                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst       256045                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       256045                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2162409829                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2162409829                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   2163633710                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2163633710                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     81526749                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     81526749                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst    492905187                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    492905187                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst       177500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       177500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   4326043539                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4326043539                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   4326043539                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4326043539                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    330271000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    330271000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    203208500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    203208500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst    533479500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    533479500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.042162                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042162                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027957                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027957                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.053611                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053611                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.252732                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.252732                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.035788                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.035788                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.035788                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035788                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1357,58 +1511,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           827152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.447245                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            5824947                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           827664                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             7.037816                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      71343314500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.447245                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975483                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975483                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           908016                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.415703                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6861520                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           908528                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.552348                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      71602668000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.415703                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975421                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975421                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          469                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14132886                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14132886                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      5824947                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5824947                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      5824947                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5824947                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      5824947                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5824947                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       827664                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       827664                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       827664                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        827664                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       827664                       # number of overall misses
-system.cpu1.icache.overall_misses::total       827664                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6712177482                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6712177482                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6712177482                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6712177482                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6712177482                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6712177482                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      6652611                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      6652611                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      6652611                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      6652611                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      6652611                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      6652611                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124412                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.124412                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124412                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.124412                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124412                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.124412                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8109.785471                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8109.785471                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8109.785471                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8109.785471                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8109.785471                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8109.785471                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         16448624                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        16448624                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6861520                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6861520                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6861520                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6861520                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6861520                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6861520                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       908528                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       908528                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       908528                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        908528                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       908528                       # number of overall misses
+system.cpu1.icache.overall_misses::total       908528                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7748571238                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7748571238                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7748571238                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7748571238                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7748571238                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7748571238                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7770048                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7770048                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7770048                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7770048                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7770048                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7770048                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.116927                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.116927                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.116927                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.116927                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.116927                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.116927                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8528.709339                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8528.709339                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8528.709339                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8528.709339                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8528.709339                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8528.709339                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1417,310 +1570,307 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       827664                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       827664                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       827664                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       827664                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       827664                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       827664                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5467532518                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5467532518                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5467532518                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5467532518                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5467532518                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5467532518                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10038000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10038000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10038000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10038000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124412                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.124412                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124412                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.124412                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6605.980830                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6605.980830                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6605.980830                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6605.980830                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       908528                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       908528                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       908528                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       908528                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       908528                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       908528                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6381932762                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   6381932762                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6381932762                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   6381932762                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6381932762                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   6381932762                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10331250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10331250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10331250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10331250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.116927                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.116927                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.116927                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.116927                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7024.475593                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  7024.475593                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7024.475593                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  7024.475593                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      6453687                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        29592                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      6340817                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          898                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         2376                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued        80004                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       668025                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           52740                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15520.178150                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1029232                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           68128                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           15.107327                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       255012                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       255045                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           26                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage        67427                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           54264                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15327.785502                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1131516                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           69292                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           16.329677                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6901.586978                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    27.255538                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.084140                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2337.993929                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6253.257565                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.421239                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001664                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.142700                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.381669                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.947276                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8859                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           87                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6442                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          153                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1624                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         7082                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8763.818423                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    26.824644                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.109281                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  5323.780218                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1213.252936                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.534901                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001637                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000007                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.324938                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.074051                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.935534                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         2056                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           45                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        12927                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           84                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          880                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1092                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           12                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           51                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          256                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1161                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5025                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.540710                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005310                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.393188                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        19285639                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       19285639                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        22569                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2289                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       905837                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        930695                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks        93707                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total        93707                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1549                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1549                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst          533                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          533                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.inst        18299                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        18299                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        22569                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2289                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       924136                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         948994                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        22569                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2289                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       924136                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        948994                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          704                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          245                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst        66474                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        67423                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst        27781                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        27781                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst        22285                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22285                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.inst        30137                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        30137                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          704                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          245                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        96611                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total        97560                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          704                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          245                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        96611                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total        97560                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14471499                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4810998                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   1464118881                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1483401378                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst    523592810                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    523592810                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst    437167020                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    437167020                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst        97500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total        97500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   1078871611                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1078871611                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14471499                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4810998                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   2542990492                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   2562272989                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14471499                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4810998                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   2542990492                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   2562272989                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        23273                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2534                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       972311                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       998118                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks        93707                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total        93707                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        29330                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29330                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        22818                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        22818                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst        48436                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        48436                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        23273                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2534                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      1020747                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1046554                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        23273                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2534                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      1020747                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1046554                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.068367                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.067550                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.947187                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.947187                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.976641                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.976641                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.622202                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.622202                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.094647                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.093220                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.030250                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.096685                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.094647                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.093220                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          271                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5756                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6900                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.125488                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002747                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.789001                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        21629208                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       21629208                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        28145                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2626                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst       993919                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total       1024690                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks       113900                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total       113900                       # number of Writeback hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst         1602                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         1602                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst          885                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total          885                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.inst        24979                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        24979                       # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        28145                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2626                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      1018898                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        1049669                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        28145                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2626                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      1018898                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       1049669                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          614                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          219                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst        85964                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        86797                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst        28133                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        28133                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst        22540                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22540                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.inst        35034                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        35034                       # number of ReadExReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          614                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          219                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       120998                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       121831                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          614                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          219                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       120998                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       121831                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     13117250                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4335498                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   2028659662                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   2046112410                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst    524558345                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    524558345                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst    440871540                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    440871540                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst       173000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       173000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   1316941950                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1316941950                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     13117250                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4335498                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst   3345601612                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3363054360                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     13117250                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4335498                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst   3345601612                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3363054360                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        28759                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2845                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      1079883                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total      1111487                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks       113900                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total       113900                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst        29735                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29735                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst        23425                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23425                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst        60013                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        60013                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        28759                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2845                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      1139896                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      1171500                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        28759                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2845                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      1139896                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1171500                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.079605                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.078091                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.946124                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.946124                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.962220                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962220                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.583774                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.583774                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.106148                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.103996                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021350                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.076977                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.106148                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.103996                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 23598.944465                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18645.659723                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19559.518190                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190                       # average SCUpgradeReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs         2801                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 37590.396472                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27650.057125                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27650.057125                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs              79                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    35.455696                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        30368                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           30368                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          950                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          950                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          295                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          295                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1245                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1245                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1245                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1245                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          704                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          245                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        65524                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        66473                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        80004                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        80004                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        27781                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27781                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22285                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22285                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        29842                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        29842                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          704                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          245                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        95366                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total        96315                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          704                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          245                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        95366                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        80004                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       176319                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    981688737                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    994327236                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2522312930                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   2522312930                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    396174942                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    396174942                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    306073762                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306073762                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst        76500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total        76500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst    831450098                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    831450098                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1813138835                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   1825777334                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      9542501                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3095998                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1813138835                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2522312930                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4348090264                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    313994504                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    313994504                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    182561501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    182561501                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    496556005                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    496556005                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.067390                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.066598                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks        33019                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           33019                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          106                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          106                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst          284                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          284                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          390                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          390                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          390                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          390                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          614                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          219                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        85858                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        86691                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25785                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        25785                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst        28133                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28133                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst        22540                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22540                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst        34750                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        34750                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          614                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          219                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       120608                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       121441                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          614                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          219                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       120608                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25785                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       147226                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   1423893692                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1435514940                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1025770621                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1025770621                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst    399929245                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    399929245                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst    306606785                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306606785                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst       145000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       145000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   1042779776                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1042779776                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   2466673468                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2478294716                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      8818750                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2802498                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   2466673468                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1025770621                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   3504065337                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    316947250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    316947250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    187186000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    187186000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst    504133250                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    504133250                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.079507                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.077996                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.947187                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.947187                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.976641                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.976641                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.616112                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.616112                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.093428                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.092031                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.030250                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.096685                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.093428                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.946124                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.946124                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.962220                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962220                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.579041                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.579041                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.105806                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103663                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021350                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.076977                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.105806                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.168476                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.125673                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492                       # average SCUpgradeReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average SCUpgradeFailReq mshr miss latency
 system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1728,64 +1878,64 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1502965                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1041469                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2098                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2098                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback        93707                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       114724                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq       1492249                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1157222                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2126                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2126                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       113900                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        36842                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        83933                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40744                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84523                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        65298                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        52790                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1655558                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       667978                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6105                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        48641                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2378282                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     52977856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     21039827                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        93092                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          74120911                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     816365                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1934720                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.382054                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.485890                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        74786                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41424                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85596                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        82199                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        64364                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1817284                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       767101                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7150                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        61380                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2652915                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58153088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24793955                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11380                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       115036                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          83073459                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     610470                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1874725                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.283158                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.450533                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5           1195552     61.79%     61.79% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            739168     38.21%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1343882     71.68%     71.68% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            530843     28.32%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1934720                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     695166718                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1874725                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     789561722                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     78719500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79017500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1243267482                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1364909988                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    322631890                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    381206023                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      3571998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4307495                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     25370995                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     32623745                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31020                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31020                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59447                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              23223                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59440                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              23216                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56686                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -1806,11 +1956,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       108000                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71630                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180904                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -1831,11 +1981,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162880                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40158000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2484026                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1875,23 +2025,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347075142                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347036169                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84777000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36822606                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36822569                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36433                       # number of replacements
-system.iocache.tags.tagsinuse                0.995239                       # Cycle average of tags in use
+system.iocache.tags.replacements                36417                       # number of replacements
+system.iocache.tags.tagsinuse                0.997930                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36433                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         269184120000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.995239                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062202                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062202                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         269849823000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.997930                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062371                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062371                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1905,14 +2055,14 @@ system.iocache.demand_misses::realview.ide          243                       #
 system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          243                       # number of overall misses
 system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     30315377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     30315377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9644186159                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9644186159                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     30315377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     30315377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     30315377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     30315377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     30354377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     30354377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9625347223                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9625347223                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     30354377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     30354377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     30354377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     30354377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1929,24 +2079,24 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124754.637860                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124754.637860                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124754.637860                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124754.637860                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124754.637860                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         57278                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124915.131687                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124915.131687                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124915.131687                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124915.131687                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124915.131687                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56938                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7269                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7266                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.879763                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.836224                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.writebacks::writebacks           36174                       # number of writebacks
+system.iocache.writebacks::total                36174                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
@@ -1955,14 +2105,14 @@ system.iocache.demand_mshr_misses::realview.ide          243
 system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17678377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17678377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7760326371                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7760326371                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17678377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17678377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17678377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17678377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17717377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17717377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7741561361                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7741561361                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17717377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17717377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17717377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17717377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1971,264 +2121,264 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72750.522634                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72750.522634                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72911.016461                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72911.016461                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   150396                       # number of replacements
-system.l2c.tags.tagsinuse                64479.883220                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     522727                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   215317                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.427709                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   139153                       # number of replacements
+system.l2c.tags.tagsinuse                64176.379405                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     380612                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   203608                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.869337                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12469.492368                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    93.733463                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.999899                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3818.005633                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.718540                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      732.215158                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4549.115372                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001430                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.069414                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1022::2          475                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6086                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        40896                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   11502.485032                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    90.401142                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.038214                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst    12425.194881                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.683124                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1856.879628                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1880.036266                       # Average occupied blocks per requestor
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 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           67                       # Occupied blocks per task id
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 system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::2          270                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::4        14797                       # Occupied blocks per task id
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-system.l2c.ReadReq_hits::total                 294426                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          250431                       # number of Writeback hits
-system.l2c.Writeback_hits::total               250431                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.inst           11782                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst             481                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               12263                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst           184                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst           192                       # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu0.inst             3646                       # number of ReadExReq hits
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-system.l2c.demand_hits::cpu1.inst                7808                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher        25945                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  298980                       # number of demand (read+write) hits
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-system.l2c.ReadReq_misses::cpu0.dtb.walker          161                       # number of ReadReq misses
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 system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
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-system.l2c.Writeback_accesses::writebacks       250431                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           250431                       # number of Writeback accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::total          0.404371                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.448460                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.823292                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.490824                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.753275                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.806014                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.764967                       # miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.871062                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.850353                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.796500                       # miss rate for ReadExReq accesses
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+system.l2c.demand_miss_rate::total           0.520261                       # miss rate for demand accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 106384.709543                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1069.898121                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  1066.442660                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1069.243042                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  2496.111954                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   885.465404                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1373.007467                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 79973.477310                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913                       # average overall miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst   786.487291                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst   580.809437                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   738.441900                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  1516.935275                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst   431.436501                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85130.213992                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74625                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 76041.247748                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 104725.610180                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79652.173913                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 77013.239218                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74743.670164                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 96387.400856                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74625                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 104725.610180                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 77013.239218                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74743.670164                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 96387.400856                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2237,155 +2387,158 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              110752                       # number of writebacks
-system.l2c.writebacks::total                   110752                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          161                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks              104097                       # number of writebacks
+system.l2c.writebacks::total                   104097                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             3                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          162                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11256                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       169616                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            8                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1341                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        17501                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          199884                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst         9580                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2241                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11821                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          527                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1214                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1741                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst         6969                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.inst         6429                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         13398                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker          161                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        32540                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::total          178984                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.inst         8970                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.inst         2734                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11704                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          618                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         1189                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1807                       # number of SCUpgradeReq MSHR misses
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+system.l2c.ReadExReq_mshr_misses::cpu1.inst         8676                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         20251                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker          162                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        18225                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       169616                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         7770                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        17501                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           213282                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu0.inst        44115                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu1.inst        12006                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) MSHR misses
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+system.l2c.overall_mshr_misses::cpu0.dtb.walker          162                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        18225                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       169616                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            8                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         7770                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        17501                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          213282                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10828000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst        44115                       # number of overall MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    817788246                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16174111957                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       500000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     96492250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1701029964                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  18800812917                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     97817994                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     22626723                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    120444717                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      5423023                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     12163710                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     17586733                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst    506879094                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst    396754755                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total    903633849                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10828000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2034453239                       # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     27532715                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    119295119                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6310115                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     11917186                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     18227301                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst    807808323                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::total   1337979335                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1324667340                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  16174111957                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       500000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    493247005                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1701029964                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  19704446766                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10828000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   2842261562                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  12379828891                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       810750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    746381011                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    749741791                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16730077755                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     10991250                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1324667340                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16174111957                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       500000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    493247005                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1701029964                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  19704446766                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5522428749                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    260648000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5783076749                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4102579499                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    146450000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4249029499                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   9625008248                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    407098000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10032106248                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.007576                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.221684                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.433957                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.078431                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.162723                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.402822                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.404369                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.448460                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.823292                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.490824                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.741210                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.863442                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.822390                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.656524                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.876244                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.746324                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.007576                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.296872                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.433957                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.078431                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.498780                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.402822                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.416353                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.218453                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.007576                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.296872                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.433957                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.078431                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.498780                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.402822                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.416353                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2842261562                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  12379828891                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       810750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    746381011                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    749741791                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16730077755                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5519244498                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    263262750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5782507248                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4096891000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    150604000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4247495000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   9616135498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    413866750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10030002248                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.315304                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.121800                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.500587                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.753275                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.806014                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.764967                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.813158                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.871062                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.850353                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.750795                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.866906                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.796500                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.371905                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.321463                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.520232                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.275510                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.015625                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.371905                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.643235                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.092308                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.321463                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.456531                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.520232                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 92386.824795                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 83971.580069                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 92386.824795                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 83971.580069                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2396,57 +2549,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              238185                       # Transaction distribution
-system.membus.trans_dist::ReadResp             238185                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30953                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30953                       # Transaction distribution
-system.membus.trans_dist::Writeback            146942                       # Transaction distribution
+system.membus.trans_dist::ReadReq              217279                       # Transaction distribution
+system.membus.trans_dist::ReadResp             217279                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30939                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30939                       # Transaction distribution
+system.membus.trans_dist::Writeback            140271                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78292                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          39832                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13662                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             30241                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            13298                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       108000                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq            75080                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40217                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13603                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40948                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            20159                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13634                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       701758                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       823430                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 932326                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13590                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       668031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       789629                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 898509                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27268                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     20926892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     21118256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                25753712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           122070                       # Total snoops (count)
-system.membus.snoop_fanout::samples            531658                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27180                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19605228                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19796474                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4634432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      4634432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                24430906                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123136                       # Total snoops (count)
+system.membus.snoop_fanout::samples            511969                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  531658    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  511969    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              531658                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88755994                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              511969                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88887000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11894500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11855500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1935574499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1869891749                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2123782192                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2005520473                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38517394                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38480431                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2479,44 +2632,44 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             658320                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            658305                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30953                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30953                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           250431                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             516876                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            516861                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30939                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30939                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           234152                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           90455                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40208                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         130663                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp            6                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            38633                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           38633                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1411505                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       304961                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1716466                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     43486557                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5753747                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               49240304                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          287552                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1076220                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.033884                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.180932                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeReq           78584                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40535                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         119119                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           13                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51536                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51536                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1131248                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       290761                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1422009                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34509719                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5415139                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39924858                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          285546                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           919868                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.039644                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.195121                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1039753     96.61%     96.61% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36467      3.39%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 883401     96.04%     96.04% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36467      3.96%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1076220                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1573537018                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             919868                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1489301846                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy          1026000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2438104006                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1891845782                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         680349684                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         645358377                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 1c98029fc..8068ce076 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,116 +1,116 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.852850                       # Number of seconds simulated
-sim_ticks                                2852849954000                       # Number of ticks simulated
-final_tick                               2852849954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.852858                       # Number of seconds simulated
+sim_ticks                                2852857543000                       # Number of ticks simulated
+final_tick                               2852857543000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160685                       # Simulator instruction rate (inst/s)
-host_op_rate                                   194286                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4092855045                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 562916                       # Number of bytes of host memory used
-host_seconds                                   697.03                       # Real time elapsed on the host
-sim_insts                                   112002684                       # Number of instructions simulated
-sim_ops                                     135423332                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 169259                       # Simulator instruction rate (inst/s)
+host_op_rate                                   204656                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4303403710                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 619600                       # Number of bytes of host memory used
+host_seconds                                   662.93                       # Real time elapsed on the host
+sim_insts                                   112207125                       # Number of instructions simulated
+sim_ops                                     135672670                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         8192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10823844                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10837924                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10832740                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1658560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1658560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7967296                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10847140                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1662912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1662912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7962752                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.inst          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7984820                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7980276                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          128                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             169642                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             169862                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                169781                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124489                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170006                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124418                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.inst              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128870                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2759                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               128799                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2872                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              3794046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3798971                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3797164                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          581370                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             581370                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2792750                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3802202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          582893                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             582893                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2791150                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.inst                6143                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2798892                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2792750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2797292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2791150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2872                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3800189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3805114                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6596057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        169781                       # Number of read requests accepted
-system.physmem.writeReqs                       165094                       # Number of write requests accepted
-system.physmem.readBursts                      169781                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     165094                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10858880                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10194112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10832740                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10303156                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    5787                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4592                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10675                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10570                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10940                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10884                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12996                       # Per bank write bursts
+system.physmem.bw_total::total                6599494                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170006                       # Number of read requests accepted
+system.physmem.writeReqs                       165023                       # Number of write requests accepted
+system.physmem.readBursts                      170006                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     165023                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10873728                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10175104                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10847140                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10298612                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6006                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4596                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10656                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10651                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10704                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10614                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13356                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               10666                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11098                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10877                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10287                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10457                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10268                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9318                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10425                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10908                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9678                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9623                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10097                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10006                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10747                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               10511                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9282                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9914                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10247                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10166                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               10178                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10302                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              10037                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9553                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              10068                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              10279                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8984                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8912                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11042                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10972                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10208                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10672                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10509                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9657                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10109                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10747                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9757                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9582                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10072                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10092                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10491                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10304                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9538                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9899                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10133                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10134                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10091                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10380                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10169                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9697                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9799                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10201                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9040                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8946                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2852849531000                       # Total gap between requests
+system.physmem.totGap                    2852857119000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169226                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169451                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 160713                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    162999                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        40                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 160642                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163533                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -155,134 +155,134 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7745                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     8889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     9997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    10332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    11185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9441                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3913                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7826                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8811                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7662                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62892                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      334.747313                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.220308                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     348.895470                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22415     35.64%     35.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14531     23.10%     58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6612     10.51%     69.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3482      5.54%     74.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2506      3.98%     78.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1581      2.51%     81.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1054      1.68%     82.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1133      1.80%     84.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9578     15.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62892                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6668                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.444061                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      561.318574                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6666     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6668                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6668                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.887672                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.937507                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.272912                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5557     83.34%     83.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              39      0.58%     83.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              24      0.36%     84.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             223      3.34%     87.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             119      1.78%     89.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              51      0.76%     90.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              29      0.43%     90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              45      0.67%     91.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             120      1.80%     93.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              12      0.18%     93.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              15      0.22%     93.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.21%     93.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              30      0.45%     94.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              19      0.28%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.12%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              35      0.52%     95.08% # Writes before turning the bus around for reads
+system.physmem.bytesPerActivate::samples        62962                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      334.308059                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     193.690406                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     348.894179                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22562     35.83%     35.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14454     22.96%     58.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6551     10.40%     69.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3518      5.59%     74.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2542      4.04%     78.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1533      2.43%     81.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1128      1.79%     83.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1127      1.79%     84.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9547     15.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62962                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6648                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.554603                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      562.154464                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6646     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6648                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6648                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.914862                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.938842                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.611148                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5537     83.29%     83.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              45      0.68%     83.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              19      0.29%     84.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             242      3.64%     87.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             123      1.85%     89.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              53      0.80%     90.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              26      0.39%     90.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              33      0.50%     91.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             114      1.71%     93.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              19      0.29%     93.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              14      0.21%     93.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              11      0.17%     93.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              33      0.50%     94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              20      0.30%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              10      0.15%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              22      0.33%     95.08% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::80-83              60      0.90%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               9      0.13%     96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               6      0.09%     96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              14      0.21%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             100      1.50%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            13      0.19%     98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             8      0.12%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            22      0.33%     98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.04%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            10      0.15%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.04%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            27      0.40%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             9      0.13%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.03%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.06%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             8      0.12%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             5      0.07%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.04%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6668                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1702635750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4883948250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    848350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10034.98                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::84-87              16      0.24%     96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               7      0.11%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              13      0.20%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              84      1.26%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.08%     97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             9      0.14%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             9      0.14%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            15      0.23%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.05%     98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            10      0.15%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.05%     98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            37      0.56%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             8      0.12%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.06%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.14%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.08%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.06%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.06%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             5      0.08%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             4      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6648                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1659710000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4845372500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849510000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9768.63                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28784.98                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28518.63                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.57                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
@@ -291,37 +291,42 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139924                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    126136                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.18                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8519147.54                       # Average gap between requests
-system.physmem.pageHitRate                      80.87                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2713515031250                       # Time in different power states
-system.physmem.memoryStateTime::REF       95262700000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       44072132750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 246765960                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 228697560                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 134644125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 124785375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                691906800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                631511400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               524685600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               507468240                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          186333841200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          186333841200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           83199782385                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           82045768365                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1638723732000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1639736025000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1909855358070                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1909608097140                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.456797                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.370126                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.33                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     140084                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    125841                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.14                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8515254.26                       # Average gap between requests
+system.physmem.pageHitRate                      80.85                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  246909600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134722500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 691555800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                522696240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186334349760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83503223595                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638462219000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1909895676495                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.469106                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2725585905000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95262960000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32002250000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  229083120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  124995750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 633664200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                507533040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186334349760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82044200295                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1639742072250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1909615898415                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.371033                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2727729306000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95262960000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     29860939000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          448                       # Number of instructions bytes read from this memory
@@ -340,16 +345,24 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31051775                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16857996                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2519060                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18534749                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13337392                       # Number of BTB hits
+system.cpu.branchPred.lookups                31058702                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16880390                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2530392                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18557624                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13376459                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.958849                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7856975                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1512712                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.080666                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7810096                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1523796                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -371,27 +384,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                     66845                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                66845                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43967                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22878                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        66845                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           66845    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        66845                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7791                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7513.505454                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7923.201613                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767         7786     99.94%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303            2      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-131071            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7791                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    234495500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       234495500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    234495500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6429     82.52%     82.52% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1362     17.48%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7791                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66845                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66845                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7791                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7791                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        74636                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24746159                       # DTB read hits
-system.cpu.dtb.read_misses                      60199                       # DTB read misses
-system.cpu.dtb.write_hits                    19443156                       # DTB write hits
-system.cpu.dtb.write_misses                      6950                       # DTB write misses
+system.cpu.dtb.read_hits                     24793006                       # DTB read hits
+system.cpu.dtb.read_misses                      59858                       # DTB read misses
+system.cpu.dtb.write_hits                    19468400                       # DTB write hits
+system.cpu.dtb.write_misses                      6987                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4352                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1306                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1783                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4357                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1289                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1775                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       751                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24806358                       # DTB read accesses
-system.cpu.dtb.write_accesses                19450106                       # DTB write accesses
+system.cpu.dtb.perms_faults                       757                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24852864                       # DTB read accesses
+system.cpu.dtb.write_accesses                19475387                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44189315                       # DTB hits
-system.cpu.dtb.misses                           67149                       # DTB misses
-system.cpu.dtb.accesses                      44256464                       # DTB accesses
+system.cpu.dtb.hits                          44261406                       # DTB hits
+system.cpu.dtb.misses                           66845                       # DTB misses
+system.cpu.dtb.accesses                      44328251                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -413,8 +464,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     57672689                       # ITB inst hits
-system.cpu.itb.inst_misses                       5411                       # ITB inst misses
+system.cpu.itb.walker.walks                      5440                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5440                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          316                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5124                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5440                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5440    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5440                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3188                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10236.198243                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7641.069075                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7067.497935                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1310     41.09%     41.09% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383         1157     36.29%     77.38% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          720     22.58%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::73728-81919            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3188                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    234126500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       234126500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    234126500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2879     90.31%     90.31% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           309      9.69%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3188                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5440                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5440                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3188                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3188                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8628                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57692911                       # ITB inst hits
+system.cpu.itb.inst_misses                       5440                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -423,119 +503,119 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2970                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2976                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8383                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8340                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57678100                       # ITB inst accesses
-system.cpu.itb.hits                          57672689                       # DTB hits
-system.cpu.itb.misses                            5411                       # DTB misses
-system.cpu.itb.accesses                      57678100                       # DTB accesses
-system.cpu.numCycles                        314966932                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57698351                       # ITB inst accesses
+system.cpu.itb.hits                          57692911                       # DTB hits
+system.cpu.itb.misses                            5440                       # DTB misses
+system.cpu.itb.accesses                      57698351                       # DTB accesses
+system.cpu.numCycles                        314937774                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112002684                       # Number of instructions committed
-system.cpu.committedOps                     135423332                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7762811                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3036                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5390780993                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.812137                       # CPI: cycles per instruction
-system.cpu.ipc                               0.355601                       # IPC: instructions per cycle
+system.cpu.committedInsts                   112207125                       # Number of instructions committed
+system.cpu.committedOps                     135672670                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7783589                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5390825701                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.806754                       # CPI: cycles per instruction
+system.cpu.ipc                               0.356283                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3036                       # number of quiesce instructions executed
-system.cpu.tickCycles                       228185661                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        86781271                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            843230                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.953176                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42691062                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            843742                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.597294                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
+system.cpu.tickCycles                       228221487                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        86716287                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            841983                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.953279                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42762284                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            842495                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.756721                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         281436250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953176                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953279                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176134397                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176134397                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     23488260                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23488260                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     18281937                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18281937                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457712                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457712                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       460238                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460238                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      41770197                       # number of demand (read+write) hits
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-system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8359                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8359                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176413277                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176413277                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     23536274                       # number of ReadReq hits
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 system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1126149                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1126149                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1126149                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1126149                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8658802092                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8658802092                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21460434801                       # number of WriteReq miss cycles
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-system.cpu.dcache.LoadLockedReq_miss_latency::total    117977250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       152000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       152000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  30119236893                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30119236893                       # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total  30119236893                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     24072877                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24072877                       # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total     18823469                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466071                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466071                       # number of LoadLockedReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses::total       460240                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     42896346                       # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total     42896346                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024285                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.024285                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028769                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.028769                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017935                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017935                       # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.overall_miss_latency::total  30044200646                       # number of overall miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017582                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.026253                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026253                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.026253                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026253                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14811.067916                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14811.067916                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39629.116656                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39629.116656                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14113.799498                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14113.799498                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        76000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        76000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26745.339110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26745.339110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26745.339110                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.026187                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026187                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.026187                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026187                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14828.793522                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39489.183729                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.426480                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        75250                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75250                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26702.609403                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26702.609403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26702.609403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26702.609403                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -544,70 +624,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       699279                       # number of writebacks
-system.cpu.dcache.writebacks::total            699279                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45143                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        45143                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242778                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       242778                       # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total       287921                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       287921                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       287921                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       539474                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       539474                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298754                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298754                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8359                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8359                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       698310                       # number of writebacks
+system.cpu.dcache.writebacks::total            698310                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45149                       # number of ReadReq MSHR hits
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 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       838228                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       838228                       # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total       838228                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6896325139                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6896325139                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11211804160                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11211804160                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    101230750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    101230750                       # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       148000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18108129299                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18108129299                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total  18108129299                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439577500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439577500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230574500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230574500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022410                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022410                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015871                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015871                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017935                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017935                       # mshr miss rate for LoadLockedReq accesses
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146500                       # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total  18060007796                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18060007796                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18060007796                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790998000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790998000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439562500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439562500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230560500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230560500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022316                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022316                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015860                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015860                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017582                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017582                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.019541                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019541                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019541                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        74000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        74000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019484                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.019484                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019484                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019484                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12806.801640                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37357.981406                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.253813                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        73250                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73250                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21572.997924                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -615,58 +695,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2898546                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.424366                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54764882                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2899058                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.890578                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       15302672250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.424366                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           2900110                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.424371                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54783568                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2900622                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.886835                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       15309705250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.424371                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998876                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998876                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60563021                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60563021                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54764882                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54764882                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54764882                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54764882                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54764882                       # number of overall hits
-system.cpu.icache.overall_hits::total        54764882                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2899070                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2899070                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2899070                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2899070                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2899070                       # number of overall misses
-system.cpu.icache.overall_misses::total       2899070                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  39144211468                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  39144211468                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  39144211468                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  39144211468                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  39144211468                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  39144211468                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57663952                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57663952                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57663952                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57663952                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57663952                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57663952                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050275                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050275                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050275                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050275                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050275                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050275                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13502.334013                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13502.334013                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13502.334013                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13502.334013                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13502.334013                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60584835                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60584835                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54783568                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54783568                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54783568                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54783568                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54783568                       # number of overall hits
+system.cpu.icache.overall_hits::total        54783568                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2900634                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2900634                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2900634                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2900634                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2900634                       # number of overall misses
+system.cpu.icache.overall_misses::total       2900634                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39169046291                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39169046291                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39169046291                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39169046291                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39169046291                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39169046291                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57684202                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57684202                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57684202                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57684202                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57684202                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57684202                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050285                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050285                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050285                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050285                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050285                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050285                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.615517                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13503.615517                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.615517                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13503.615517                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.615517                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13503.615517                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -675,176 +755,176 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2899070                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2899070                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2899070                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2899070                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2899070                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2899070                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33336586532                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  33336586532                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33336586532                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  33336586532                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33336586532                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  33336586532                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2900634                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      2900634                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      2900634                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      2900634                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      2900634                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      2900634                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33358375709                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  33358375709                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33358375709                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  33358375709                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33358375709                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  33358375709                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    222066250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    222066250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    222066250                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    222066250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050275                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050275                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050275                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050275                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11499.062297                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11499.062297                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11499.062297                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050285                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050285                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050285                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.050285                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050285                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.050285                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96693                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65074.721793                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4049393                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161936                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            25.006132                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96921                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65071.012008                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4047776                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162169                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            24.960233                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47626.273785                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.769943                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.489031                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000365                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 17377.677699                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.726719                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001080                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 17501.014446                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.724770                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001091                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.265162                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992961                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000656                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        74500                       # number of ReadReq miss cycles
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 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        74500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  11956741678                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        74500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  11956741678                       # number of overall miss cycles
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000223                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010803                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.982612                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982612                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001799                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981285                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.443071                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.443071                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000223                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.044982                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044118                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001717                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000223                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.044982                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.044118                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average ReadReq miss latency
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 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74016.496133                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74027.549518                       # average ReadReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   303.345612                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        73000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        73000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.188861                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.188861                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   284.622526                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   284.622526                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        72250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71023.976769                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77369.918699                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70752.498446                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71019.319894                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71023.976769                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70752.498446                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -853,92 +933,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88299                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88299                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          156                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total          156                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst          156                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          156                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst          156                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          156                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          123                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        88228                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88228                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          162                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total          162                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst          162                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          162                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst          162                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          162                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          128                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37080                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        37204                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2769                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2769                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37248                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        37377                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2779                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2779                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131123                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       131123                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          123                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131168                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131168                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          128                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       168203                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168327                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          123                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       168416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168545                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          128                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       168203                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168327                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       168416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168545                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2281616000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2289681000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27874769                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27874769                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       122000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       122000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7547217572                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7547217572                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2295827000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2304530750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27979779                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27979779                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7500556317                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7500556317                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9828833572                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9836898572                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8002500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9796383317                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9805087067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        62500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9828833572                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9836898572                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545306500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545306500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4107046000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107046000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652352500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652352500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010758                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010560                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.982612                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9796383317                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9805087067                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545301250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545301250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4107025000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107025000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652326250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652326250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010806                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010611                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.981285                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981285                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.443071                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443071                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044077                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000223                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.044940                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044077                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.443005                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443005                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.044993                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044136                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.044993                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044136                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        61000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        61000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -946,54 +1026,54 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3581708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3581608                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        3581727                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3581627                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27607                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27607                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       699279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       698310                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2818                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2832                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2820                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5804102                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2510082                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14997                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161563                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8490744                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185730048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98946845                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17972                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       286516                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          284981381                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       60946                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4581834                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.007957                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.088847                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296087                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296087                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5807240                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2506645                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160889                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8489768                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185830784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98804957                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        17720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       284664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          284938125                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       61311                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4581044                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.007958                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.088854                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            4545376     99.20%     99.20% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            4544586     99.20%     99.20% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::6              36458      0.80%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4581834                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3016682672                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4581044                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3015323412                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       202500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4358543218                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4360848041                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1342977701                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1341145704                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10504000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10564000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      89938750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      89727250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
@@ -1090,23 +1170,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347024164                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347055145                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36804504                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36804505                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.033420                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.033413                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         270180945000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.033420                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064589                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064589                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270192614000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.033413                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064588                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064588                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1122,8 +1202,8 @@ system.iocache.overall_misses::realview.ide          234                       #
 system.iocache.overall_misses::total              234                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     27950377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     27950377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9603131283                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9603131283                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9592588263                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9592588263                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     27950377                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     27950377                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     27950377                       # number of overall miss cycles
@@ -1146,17 +1226,17 @@ system.iocache.overall_miss_rate::realview.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119446.055556                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 119446.055556                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 119446.055556                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 119446.055556                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         56022                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs         55542                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7210                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7161                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.770042                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.756179                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1172,8 +1252,8 @@ system.iocache.overall_mshr_misses::realview.ide          234
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     15781377                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     15781377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7719475291                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7708930273                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7708930273                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ide     15781377                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     15781377                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ide     15781377                       # number of overall MSHR miss cycles
@@ -1188,64 +1268,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 67441.782051                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               71576                       # Transaction distribution
-system.membus.trans_dist::ReadResp              71576                       # Transaction distribution
+system.membus.trans_dist::ReadReq               71749                       # Transaction distribution
+system.membus.trans_dist::ReadResp              71749                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27607                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27607                       # Transaction distribution
-system.membus.trans_dist::Writeback            124489                       # Transaction distribution
+system.membus.trans_dist::Writeback            124418                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4592                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4594                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129300                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129300                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4598                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129351                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129351                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446065                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       553697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446451                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554083                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 662584                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 662970                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16500440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16664221                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16510296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16674077                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21299677                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              507                       # Total snoops (count)
-system.membus.snoop_fanout::samples            332045                       # Request fanout histogram
+system.membus.pkt_size::total                21309533                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              506                       # Total snoops (count)
+system.membus.snoop_fanout::samples            332202                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  332045    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  332202    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              332045                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87455500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              332202                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87413000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1699000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1709000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1675329000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1674431500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1688631909                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1690391904                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38334496                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38335495                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index d32247ca8..c276b537b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827042                       # Number of seconds simulated
-sim_ticks                                2827042159500                       # Number of ticks simulated
-final_tick                               2827042159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827025                       # Number of seconds simulated
+sim_ticks                                2827025397500                       # Number of ticks simulated
+final_tick                               2827025397500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73670                       # Simulator instruction rate (inst/s)
-host_op_rate                                    89358                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1840258315                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 564112                       # Number of bytes of host memory used
-host_seconds                                  1536.22                       # Real time elapsed on the host
-sim_insts                                   113173742                       # Number of instructions simulated
-sim_ops                                     137273263                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  71679                       # Simulator instruction rate (inst/s)
+host_op_rate                                    86943                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1789973688                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 620632                       # Number of bytes of host memory used
+host_seconds                                  1579.37                       # Real time elapsed on the host
+sim_insts                                   113206948                       # Number of instructions simulated
+sim_ops                                     137314363                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1324048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9496932                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1324240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9499748                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10823604                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8116352                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10826676                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1324240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1324240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8118016                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8133876                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8135540                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           20                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22933                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             148909                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22936                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             148953                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                171883                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126818                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                171931                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126844                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               131199                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            430                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               131225                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            453                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468351                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3359317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               468422                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3360333                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3828597                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468351                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468351                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2870970                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3829706                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          468422                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             468422                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2871575                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2877168                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2870970                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2877774                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2871575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           453                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468351                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3365516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              468422                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3366532                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6705765                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        171884                       # Number of read requests accepted
-system.physmem.writeReqs                       167423                       # Number of write requests accepted
-system.physmem.readBursts                      171884                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     167423                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10992576                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10315392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10823668                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10452212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    6228                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4543                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10965                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10116                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11197                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11389                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13120                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10535                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11120                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11540                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10348                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11053                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10478                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9244                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10124                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10758                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10029                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9743                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10407                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9909                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10642                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               10446                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9703                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               10218                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10399                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10626                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               10202                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10761                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9802                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9030                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9755                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              10443                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9720                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9115                       # Per bank write bursts
+system.physmem.bw_total::total                6707480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        171932                       # Number of read requests accepted
+system.physmem.writeReqs                       167449                       # Number of write requests accepted
+system.physmem.readBursts                      171932                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     167449                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10995584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10340800                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10826740                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10453876                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5856                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4542                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11320                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10283                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11137                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11363                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13028                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10237                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10954                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11381                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10407                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11232                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10729                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9386                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9853                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10909                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9951                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9636                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10810                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10132                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10502                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10558                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9654                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9978                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10358                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10535                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10309                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10935                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10009                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9154                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9556                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10555                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9521                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9009                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827041948500                       # Total gap between requests
+system.physmem.totGap                    2827025186500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2993                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  168336                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  168384                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 163042                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151765                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15965                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 163068                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151696                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,137 +159,134 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     8655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    10433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    11221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7956                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64399                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      330.873212                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     190.977516                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     347.816153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23539     36.55%     36.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14785     22.96%     59.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6319      9.81%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3687      5.73%     75.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2636      4.09%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1562      2.43%     81.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1140      1.77%     83.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1107      1.72%     85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9624     14.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64399                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6814                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.206340                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      540.339482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6812     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        64517                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.708495                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     190.901316                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.828879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23555     36.51%     36.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14820     22.97%     59.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6443      9.99%     69.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3645      5.65%     75.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2568      3.98%     79.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1574      2.44%     81.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1131      1.75%     83.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1187      1.84%     85.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9594     14.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64517                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6820                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.190762                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      540.107379                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6818     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6814                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6814                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.653948                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.805353                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.459775                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5702     83.68%     83.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              39      0.57%     84.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              26      0.38%     84.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             231      3.39%     88.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             131      1.92%     89.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              61      0.90%     90.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              35      0.51%     91.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              27      0.40%     91.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             123      1.81%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              13      0.19%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              19      0.28%     94.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              11      0.16%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              31      0.45%     94.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              13      0.19%     94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              13      0.19%     95.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.38%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              61      0.90%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              10      0.15%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               9      0.13%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              11      0.16%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              89      1.31%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             7      0.10%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            18      0.26%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             4      0.06%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             5      0.07%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.06%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            26      0.38%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             4      0.06%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             4      0.06%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.07%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            11      0.16%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151            11      0.16%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6820                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.691349                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.848646                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.179127                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5682     83.31%     83.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              64      0.94%     84.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              25      0.37%     84.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             208      3.05%     87.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             139      2.04%     89.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              55      0.81%     90.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              46      0.67%     91.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.54%     91.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             121      1.77%     93.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              14      0.21%     93.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              20      0.29%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              15      0.22%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              20      0.29%     94.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              19      0.28%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              10      0.15%     94.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              21      0.31%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              67      0.98%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              14      0.21%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               7      0.10%     96.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              14      0.21%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              85      1.25%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             5      0.07%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            15      0.22%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            16      0.23%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             5      0.07%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.37%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             8      0.12%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            12      0.18%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.07%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.60% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::156-159             2      0.03%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             3      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             3      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             9      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             4      0.06%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.03%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6814                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2084525750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5305007000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    858795000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12136.34                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            6820                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2011805750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5233168250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    859030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11709.75                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30886.34                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30459.75                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.66                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.83                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -297,36 +294,41 @@ system.physmem.busUtil                           0.06                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.50                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     141721                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    126816                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8331811.45                       # Average gap between requests
-system.physmem.pageHitRate                      80.65                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2694668588500                       # Time in different power states
-system.physmem.memoryStateTime::REF       94401060000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37972497000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 254499840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 232356600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 138864000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 126781875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                701859600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                637852800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               533628000                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               510805440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184648473360                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184648473360                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           80377758270                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           79142156730                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625717004000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1626800865000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1892372087070                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1892099291805                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.382923                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.286428                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        27.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     141825                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    127038                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.55                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8329945.36                       # Average gap between requests
+system.physmem.pageHitRate                      80.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  254462040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  138843375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 699683400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                534774960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184647456240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80304363360                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625772042000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892351625375                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.379373                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704495478000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94400540000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28128105750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  233286480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  127289250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 640395600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                512231040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184647456240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79168609575                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626768325500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892097593685                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.289511                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2706163008250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94400540000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26461835250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
@@ -345,16 +347,24 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46933448                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24039449                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1232882                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29542848                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21360620                       # Number of BTB hits
+system.cpu.branchPred.lookups                46965884                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24051171                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232760                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29570934                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21375571                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.303862                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11754095                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33720                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.285749                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11765533                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33715                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -376,27 +386,53 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.dtb.walker.walks              9687                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9687                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9687                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9687    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9687                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples    207947000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0    207947000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total    207947000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6190     82.28%     82.28% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1333     17.72%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7523                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9687                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9687                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7523                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7523                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17210                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24594187                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8246                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19641862                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1441                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24601959                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8249                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19645805                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1438                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             4296                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             4297                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1766                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1738                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24602433                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19643303                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24610208                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19647243                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44236049                       # DTB hits
+system.cpu.checker.dtb.hits                  44247764                       # DTB hits
 system.cpu.checker.dtb.misses                    9687                       # DTB misses
-system.cpu.checker.dtb.accesses              44245736                       # DTB accesses
+system.cpu.checker.dtb.accesses              44257451                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -418,7 +454,25 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits            115876249                       # ITB inst hits
+system.cpu.checker.itb.walker.walks              4826                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksShort         4826                       # Table walker walks initiated with short descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples         4826                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0         4826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total         4826                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples    207571000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0    207571000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total    207571000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K         2798     88.24%     88.24% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::1M          373     11.76%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total         3171                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst         4826                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total         4826                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3171                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3171                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total         7997                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            115911347                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4826                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -435,13 +489,21 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115881075                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115876249                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115916173                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115911347                       # DTB hits
 system.cpu.checker.itb.misses                    4826                       # DTB misses
-system.cpu.checker.itb.accesses             115881075                       # DTB accesses
-system.cpu.checker.numCycles                139127814                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115916173                       # DTB accesses
+system.cpu.checker.numCycles                139170806                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -463,27 +525,89 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                     69937                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                69937                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29497                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22737                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        17703                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52234                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   334.025730                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  1986.195905                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50803     97.26%     97.26% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          591      1.13%     98.39% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          521      1.00%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383           84      0.16%     99.55% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479          102      0.20%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          114      0.22%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52234                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        16206                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9699.278169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7212.227669                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7791.284796                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        16044     99.00%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          159      0.98%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-131071            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        16206                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 116899920224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.624364                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489854                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  116858057224     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      29153000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       6015500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       4000000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9        926000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       658000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13       874000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       231500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17         5000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 116899920224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6318     82.14%     82.14% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1374     17.86%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7692                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        69937                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        69937                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7692                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7692                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        77629                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25465003                       # DTB read hits
-system.cpu.dtb.read_misses                      60438                       # DTB read misses
-system.cpu.dtb.write_hits                    19916425                       # DTB write hits
-system.cpu.dtb.write_misses                      9382                       # DTB write misses
+system.cpu.dtb.read_hits                     25472400                       # DTB read hits
+system.cpu.dtb.read_misses                      60528                       # DTB read misses
+system.cpu.dtb.write_hits                    19920178                       # DTB write hits
+system.cpu.dtb.write_misses                      9409                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4324                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       344                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2309                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4326                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       345                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2281                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25525441                       # DTB read accesses
-system.cpu.dtb.write_accesses                19925807                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1305                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25532928                       # DTB read accesses
+system.cpu.dtb.write_accesses                19929587                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45381428                       # DTB hits
-system.cpu.dtb.misses                           69820                       # DTB misses
-system.cpu.dtb.accesses                      45451248                       # DTB accesses
+system.cpu.dtb.hits                          45392578                       # DTB hits
+system.cpu.dtb.misses                           69937                       # DTB misses
+system.cpu.dtb.accesses                      45462515                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -505,8 +629,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     66294026                       # ITB inst hits
-system.cpu.itb.inst_misses                      11939                       # ITB inst misses
+system.cpu.itb.walker.walks                     11957                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11957                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         4035                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7756                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          166                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11791                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   476.931558                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2426.619854                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        11573     98.15%     98.15% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          164      1.39%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575           47      0.40%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767            2      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11791                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3494                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10252.862049                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7229.260491                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7922.738250                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1610     46.08%     46.08% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          989     28.31%     74.38% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          844     24.16%     98.54% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           31      0.89%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959           18      0.52%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::73728-81919            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3494                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  22130705712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.982067                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.132922                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       397376500      1.80%      1.80% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     21732921212     98.20%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          337000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           44500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           26500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  22130705712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3007     90.35%     90.35% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           321      9.65%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15285                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66242388                       # ITB inst hits
+system.cpu.itb.inst_misses                      11957                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -522,91 +693,91 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                      2177                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66305965                       # ITB inst accesses
-system.cpu.itb.hits                          66294026                       # DTB hits
-system.cpu.itb.misses                           11939                       # DTB misses
-system.cpu.itb.accesses                      66305965                       # DTB accesses
-system.cpu.numCycles                        260580731                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66254345                       # ITB inst accesses
+system.cpu.itb.hits                          66242388                       # DTB hits
+system.cpu.itb.misses                           11957                       # DTB misses
+system.cpu.itb.accesses                      66254345                       # DTB accesses
+system.cpu.numCycles                        260505842                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104873538                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184739295                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46933448                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33114715                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     145635789                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6158762                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     168952                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8750                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        338958                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       503648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.icacheStallCycles          104910536                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184564437                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46965884                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33141104                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     145523967                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6162316                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     169075                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        338609                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       504254                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66294321                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1128854                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4994                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          254609122                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.884999                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.237560                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  66242687                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1039458                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5021                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          254536314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.884658                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.237297                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                155317216     61.00%     61.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29235163     11.48%     72.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14076452      5.53%     78.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55980291     21.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                155286067     61.01%     61.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29244712     11.49%     72.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14083759      5.53%     78.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55921776     21.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            254609122                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.180111                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.708952                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78085586                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             105431733                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64660886                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3829260                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2601657                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422216                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                485978                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157447803                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3691485                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2601657                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83925210                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10033565                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74541150                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62655394                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              20852146                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146807646                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                950357                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                437123                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  62766                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16447                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               18089237                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150492315                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678770164                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164434086                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            254536314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.180287                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.708485                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78110854                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             105310937                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64681837                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3829276                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2603410                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422230                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485999                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157498066                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3692054                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2603410                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83952319                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10018441                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74493030                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62674544                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              20794570                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146849554                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                949739                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                436543                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62719                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16684                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               18031839                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150536032                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678970726                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164476932                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10967                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141835122                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8657190                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2845976                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2649716                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13845319                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26411369                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21300781                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1686386                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2189128                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143541895                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2120957                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143337283                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            269192                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6251828                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14653372                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125306                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     254609122                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.562970                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.882443                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             141878160                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8657869                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2847901                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2651576                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13851577                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26418729                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21304216                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1685996                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2099557                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143583180                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2120928                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143378875                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            268933                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6250249                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14652310                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125244                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     254536314                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.563294                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.882192                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           166344309     65.33%     65.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45117660     17.72%     83.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32035421     12.58%     95.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10298180      4.04%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              813519      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           166156595     65.28%     65.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45308451     17.80%     83.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31957183     12.56%     95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10300315      4.05%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813737      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -614,9 +785,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       254609122                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       254536314                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7370311     32.63%     32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7371563     32.63%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.63% # attempts to use FU when none available
@@ -645,13 +816,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5632420     24.93%     57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9586874     42.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5632608     24.93%     57.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9585974     42.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96009315     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113982      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              96039761     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113980      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -679,96 +850,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc           8594      0.01%     67.07% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26194290     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21008765     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26201849     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21012354     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143337283                       # Type of FU issued
-system.cpu.iq.rate                           0.550069                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22589637                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157598                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          564106761                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         151919680                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140223084                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35756                       # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total              143378875                       # Type of FU issued
+system.cpu.iq.rate                           0.550386                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22590177                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157556                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          564117476                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         151959359                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140262857                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35698                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes              13217                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11431                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165901147                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23436                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           324147                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165943337                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23378                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323934                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1490308                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1489912                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          533                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18251                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       701176                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18252                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       700651                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88081                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6304                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87937                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6369                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2601657                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  950737                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                291154                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145863821                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2603410                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  946501                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                282988                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145905073                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26411369                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21300781                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096076                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17895                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                256263                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18251                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317548                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471732                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789280                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142394540                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25793108                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            873030                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26418729                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21304216                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096059                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17893                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                248042                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18252                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317390                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471834                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789224                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142436087                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25800504                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            872964                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200969                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46672402                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26533167                       # Number of branches executed
-system.cpu.iew.exec_stores                   20879294                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.546451                       # Inst execution rate
-system.cpu.iew.wb_sent                      142007306                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140234515                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63283849                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95860591                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200965                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46683536                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26544582                       # Number of branches executed
+system.cpu.iew.exec_stores                   20883032                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.546767                       # Inst execution rate
+system.cpu.iew.wb_sent                      142049013                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140274288                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63301991                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95888204                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.538161                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.538469                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.660165                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7591533                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995651                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755158                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    251674404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.546055                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.146686                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7591203                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995684                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755012                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    251600015                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.546380                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.145616                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    178222235     70.81%     70.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43294364     17.20%     88.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15476639      6.15%     94.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4357303      1.73%     95.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6369018      2.53%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1679088      0.67%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       777340      0.31%     99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       414271      0.16%     99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1084146      0.43%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    178032532     70.76%     70.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43398742     17.25%     88.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15483585      6.15%     94.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4358404      1.73%     95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6462138      2.57%     98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1589340      0.63%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       777430      0.31%     99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       414440      0.16%     99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1083404      0.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    251674404                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113328647                       # Number of instructions committed
-system.cpu.commit.committedOps              137428168                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    251600015                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113361853                       # Number of instructions committed
+system.cpu.commit.committedOps              137469268                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45520666                       # Number of memory references committed
-system.cpu.commit.loads                      24921061                       # Number of loads committed
-system.cpu.commit.membars                      814701                       # Number of memory barriers committed
-system.cpu.commit.branches                   26049415                       # Number of branches committed
+system.cpu.commit.refs                       45532382                       # Number of memory references committed
+system.cpu.commit.loads                      24928817                       # Number of loads committed
+system.cpu.commit.membars                      814713                       # Number of memory barriers committed
+system.cpu.commit.branches                   26060941                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120247607                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4892692                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120284813                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4896517                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91785919     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91815303     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112990      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -797,210 +968,210 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8593      0.01%     66.88% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24921061     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20599605     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24928817     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20603565     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137428168                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1084146                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         137469268                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1083404                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    373381031                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292971684                       # The number of ROB writes
-system.cpu.timesIdled                          892930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5971609                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5393503589                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113173742                       # Number of Instructions Simulated
-system.cpu.committedOps                     137273263                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.302484                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.302484                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.434314                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.434314                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155831391                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88636025                       # number of integer regfile writes
+system.cpu.rob.rob_reads                    373323554                       # The number of ROB reads
+system.cpu.rob.rob_writes                   293054802                       # The number of ROB writes
+system.cpu.timesIdled                          892910                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5969528                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5393544954                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113206948                       # Number of Instructions Simulated
+system.cpu.committedOps                     137314363                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.301147                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.301147                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.434566                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.434566                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155872747                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88664447                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      9607                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 503020698                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53185327                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               444130548                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521619                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837995                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.958491                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40159583                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838507                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.894154                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 503168369                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53197006                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               443775049                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521649                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837844                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.958421                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40169385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838356                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.914472                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         244924250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.958491                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.958421                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179379502                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179379502                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23322864                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23322864                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15584894                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15584894                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346636                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346636                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       442009                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       442009                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460310                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460310                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38907758                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38907758                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39254394                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39254394                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       700618                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        700618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3574058                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3574058                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177109                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177109                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26740                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26740                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4274676                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4274676                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4451785                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4451785                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9939142148                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9939142148                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 135148977049                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    356483749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    356483749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       189500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       189500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145088119197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145088119197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145088119197                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145088119197                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24023482                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24023482                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19158952                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19158952                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523745                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523745                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468749                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468749                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460315                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460315                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43182434                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43182434                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43706179                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43706179                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029164                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029164                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186548                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.186548                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338159                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.338159                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.098991                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.098991                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.101857                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.101857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        37900                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        37900                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33941.313727                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32590.998711                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       505021                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179425849                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179425849                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23330547                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23330547                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15587007                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15587007                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       346674                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        346674                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441974                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441974                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460321                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460321                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38917554                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38917554                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39264228                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39264228                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       700623                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        700623                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3575875                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3575875                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177079                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177079                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26763                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26763                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      4276498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4276498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4453577                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4453577                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9909110648                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9909110648                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 134775393563                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    355748499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    355748499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       176500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       176500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144684504211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144684504211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144684504211                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144684504211                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24031170                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24031170                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19162882                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19162882                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523753                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523753                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468737                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468737                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460325                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460325                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43194052                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43194052                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43717805                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43717805                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029155                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029155                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186604                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.186604                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338096                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.338096                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057096                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057096                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099007                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099007                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.101871                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.101871                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        44125                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        44125                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33832.473255                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32487.257818                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       491325                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6926                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6982                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.916691                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    70.370238                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695574                       # number of writebacks
-system.cpu.dcache.writebacks::total            695574                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286297                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       286297                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3274736                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18417                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18417                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3561033                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3561033                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3561033                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3561033                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414321                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414321                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299322                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299322                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119334                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119334                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8323                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8323                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713643                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713643                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832977                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832977                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5358688665                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5358688665                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11888843709                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11888843709                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1476460251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1476460251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110246000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110246000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       179500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       179500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17247532374                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17247532374                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18723992625                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18723992625                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792718250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792718250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440457453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440457453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233175703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233175703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017247                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017247                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017756                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017756                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016526                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019059                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019059                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        35900                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        35900                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       695426                       # number of writebacks
+system.cpu.dcache.writebacks::total            695426                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286545                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       286545                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3276416                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3276416                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18452                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18452                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3562961                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3562961                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3562961                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3562961                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414078                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414078                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299459                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299459                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119308                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119308                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8311                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8311                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       713537                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       713537                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832845                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832845                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5351526415                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5351526415                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11825722463                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11825722463                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1475435001                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1475435001                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109426500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109426500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       168500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       168500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17177248878                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17177248878                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18652683879                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18652683879                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792686500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792686500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440468453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440468453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233154953                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233154953                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017231                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017231                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015627                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015627                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227794                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227794                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017731                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017731                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016519                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016519                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019050                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019050                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        42125                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        42125                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1008,265 +1179,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1894210                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.373832                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64309690                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1894722                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.941491                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1894041                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.373863                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64258114                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1894553                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.917296                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       13186180250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.373832                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.373863                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68186062                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68186062                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64309690                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64309690                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64309690                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64309690                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64309690                       # number of overall hits
-system.cpu.icache.overall_hits::total        64309690                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981630                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981630                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981630                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981630                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981630                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981630                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26770075875                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26770075875                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26770075875                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26770075875                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26770075875                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26770075875                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66291320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66291320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66291320                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66291320                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66291320                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66291320                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029893                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029893                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029893                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029893                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029893                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029893                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13509.119197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13509.119197                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1592                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68134254                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68134254                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64258114                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64258114                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64258114                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64258114                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64258114                       # number of overall hits
+system.cpu.icache.overall_hits::total        64258114                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1981572                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1981572                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total        1981572                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1981572                       # number of overall misses
+system.cpu.icache.overall_misses::total       1981572                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26765848354                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26765848354                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26765848354                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26765848354                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  26765848354                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26765848354                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66239686                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::cpu.inst     66239686                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66239686                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66239686                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66239686                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029915                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029915                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029915                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029915                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029915                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029915                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13507.381187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13507.381187                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2017                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               104                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               103                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    15.307692                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.582524                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86886                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        86886                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        86886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        86886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        86886                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        86886                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894744                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1894744                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1894744                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1894744                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1894744                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1894744                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22166113097                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  22166113097                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22166113097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  22166113097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22166113097                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  22166113097                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        87002                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        87002                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        87002                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        87002                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        87002                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        87002                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894570                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1894570                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1894570                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1894570                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1894570                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1894570                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22163460869                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  22163460869                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22163460869                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  22163460869                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22163460869                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  22163460869                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    202549500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    202549500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028582                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028582                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028582                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.737717                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028602                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028602                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028602                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            98615                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65077.693225                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3021592                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           163828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.443685                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            98730                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65075.133005                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3019277                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           163872                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            18.424606                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218373                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798544                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5192.626837                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756260                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000156                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.158546                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798547                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5229.614939                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.757349                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000170                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157315                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.079233                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.993007                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7003                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55048                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         28442992                       # Number of tag accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000372                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000597                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010541                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.179613                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060957                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97237.500000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76678.571429                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75263.181613                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79696.746324                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77071.202155                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   211.802771                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   211.802771                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72250                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72500.302635                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72500.302635                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77513.157895                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75315.204327                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73183.370581                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73433.597435                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77513.157895                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75315.204327                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73183.370581                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73433.597435                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72004.640695                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72004.640695                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97237.500000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76678.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75263.181613                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72699.353524                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73002.555668                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97237.500000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76678.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75263.181613                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72699.353524                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1275,8 +1446,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        90628                       # number of writebacks
-system.cpu.l2cache.writebacks::total            90628                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        90654                       # number of writebacks
+system.cpu.l2cache.writebacks::total            90654                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
@@ -1286,98 +1457,98 @@ system.cpu.l2cache.demand_mshr_hits::total          137                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          137                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           20                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19943                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        13504                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        33473                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2734                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2734                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        19946                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        13488                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        33461                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2743                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2743                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       136934                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       136934                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           19                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       136984                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       136984                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           20                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19943                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       150438                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       170407                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           19                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19946                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       150472                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19943                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       150438                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       170407                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1696750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       451250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1251787750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    914145000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2167621250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27559234                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27559234                       # number of UpgradeReq MSHR miss cycles
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 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8214311559                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8214311559                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       451250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1251787750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9128456559                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10381932809                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of overall MSHR miss cycles
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 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       451250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1251787750                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total  10381932809                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387474750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545351750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107339500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107339500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157877000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494814250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652691250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024922                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013377                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987004                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987004                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461548                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461548                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060884                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060884                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1250973750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9058246549                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10311368299                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157876500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387443500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545320000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107345000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107345000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157876500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494788500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652665000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000372                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010528                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013376                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988468                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988468                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461519                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461519                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000372                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003                       # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1387,31 +1558,31 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2565344                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2565278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2565017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2564966                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27608                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27608                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       695574                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       695426                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296684                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296684                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795456                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495832                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31236                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128794                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6451318                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121309456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98375777                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215684                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219947773                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       65392                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3562462                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        9.010230                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.100625                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2779                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296811                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296811                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495409                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31281                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128693                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6450497                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121298704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98357729                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219918257                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       65703                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3562118                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        9.010231                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.100630                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
@@ -1422,23 +1593,23 @@ system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Re
 system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9            3526018     98.98%     98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9            3525674     98.98%     98.98% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::10             36444      1.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3562462                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2503396529                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3562118                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2503082512                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       256500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2849706150                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2849465378                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1334755109                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1334578357                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19527240                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19552240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74897454                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74992959                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
@@ -1535,23 +1706,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347066130                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347066125                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36776516                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36776514                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                1.000725                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000670                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         251942535000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.000725                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062545                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062545                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         251936772000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000670                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062542                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062542                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1565,14 +1736,14 @@ system.iocache.demand_misses::realview.ide          220                       #
 system.iocache.demand_misses::total               220                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          220                       # number of overall misses
 system.iocache.overall_misses::total              220                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     26411377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     26411377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9622478237                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9622478237                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     26411377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     26411377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     26411377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     26411377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     26427377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     26427377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9617153234                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9617153234                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     26427377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     26427377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     26427377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     26427377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1589,19 +1760,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120051.713636                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120051.713636                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120051.713636                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         56749                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120124.440909                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120124.440909                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120124.440909                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120124.440909                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120124.440909                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56312                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7275                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7225                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.800550                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.794048                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1615,14 +1786,14 @@ system.iocache.demand_mshr_misses::realview.ide          220
 system.iocache.demand_mshr_misses::total          220                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          220                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          220                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     14970377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     14970377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     14970377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     14970377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     14970377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     14970377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     14986377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     14986377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7733477262                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7733477262                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     14986377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     14986377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     14986377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     14986377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1631,66 +1802,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68119.895455                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68119.895455                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               67832                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67831                       # Transaction distribution
+system.membus.trans_dist::ReadReq               67820                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67819                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
-system.membus.trans_dist::Writeback            126818                       # Transaction distribution
+system.membus.trans_dist::Writeback            126844                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4543                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4542                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4545                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135125                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135125                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4544                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135185                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135185                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452492                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560248                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108873                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108873                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 669001                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 669121                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16640360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16803825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16645096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16808561                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21439281                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21444017                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              484                       # Total snoops (count)
-system.membus.snoop_fanout::samples            336405                       # Request fanout histogram
+system.membus.snoop_fanout::samples            336478                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  336405    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  336478    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              336405                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            94190000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              336478                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            94194499                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1701500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1683660499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1683962999                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1677935457                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1678430208                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38220484                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38218486                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 8bea05f5e..f860bb1f1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,165 +1,165 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.824570                       # Number of seconds simulated
-sim_ticks                                2824570221000                       # Number of ticks simulated
-final_tick                               2824570221000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.825254                       # Number of seconds simulated
+sim_ticks                                2825254262000                       # Number of ticks simulated
+final_tick                               2825254262000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42227                       # Simulator instruction rate (inst/s)
-host_op_rate                                    51230                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              992732164                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 776620                       # Number of bytes of host memory used
-host_seconds                                  2845.25                       # Real time elapsed on the host
-sim_insts                                   120145307                       # Number of instructions simulated
-sim_ops                                     145762315                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  94727                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114921                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2228089891                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 647304                       # Number of bytes of host memory used
+host_seconds                                  1268.02                       # Real time elapsed on the host
+sim_insts                                   120114928                       # Number of instructions simulated
+sim_ops                                     145721614                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           286752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1037180                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     10498560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1295328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1287356                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8203456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            31952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           549024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      1342912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           192592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           613216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       685312                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13750604                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       286752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        31952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          318704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9574272                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12280396                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1295328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       192592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1487920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8689216                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9592016                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6726                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             16731                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       164040                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8706960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           25                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20640                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       128179                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               566                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8602                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher        20983                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3076                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9605                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher        10708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                217714                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149598                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                194742                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          135769                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               154034                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              101521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              367199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3716870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               140205                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              458482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              455660                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2903617                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           113                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               11312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              194374                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       475439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               68168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              217048                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       242566                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4868211                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         101521                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          11312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112833                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3389639                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6268                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4346652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         458482                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          68168                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             526650                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3075552                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6266                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3395921                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3389639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          770                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             101521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             373467                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3716870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3081832                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3075552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             458482                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             461927                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2903617                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              11312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             194389                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       475439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              68168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             217062                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       242566                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8264132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        217714                       # Number of read requests accepted
-system.physmem.writeReqs                       190258                       # Number of write requests accepted
-system.physmem.readBursts                      217714                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     190258                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 13924352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  11782272                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  13750604                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               11910352                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    6131                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          13778                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               13720                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13621                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14360                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               14230                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15917                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12969                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13917                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13922                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13602                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13356                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12792                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11688                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              13275                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              14168                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              13342                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12689                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               11837                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               11937                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               12245                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               12130                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               11220                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               11075                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               11642                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               11554                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               11490                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               11375                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              11404                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              11050                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              11716                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              11527                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              11100                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              10796                       # Per bank write bursts
+system.physmem.bw_total::total                7428484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        194742                       # Number of read requests accepted
+system.physmem.writeReqs                       176429                       # Number of write requests accepted
+system.physmem.readBursts                      194742                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     176429                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12454272                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10909824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12280396                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               11025296                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5937                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          13544                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12112                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11748                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12331                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12396                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14329                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12174                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12464                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12653                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12280                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12648                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12320                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11195                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11560                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11958                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11562                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10868                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10717                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10772                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               11107                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               11182                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10467                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10805                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10968                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10867                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10652                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               11077                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              11118                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              10634                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10720                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10162                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9784                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9434                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2824568625000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2825253981000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3083                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  214044                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  191072                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 185822                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     53286                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     76786                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     20725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     15275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     11050                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      9711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8821                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      8169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      7162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1453                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1085                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      636                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      453                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      285                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      205                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 171993                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     63499                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     64318                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     19752                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7342                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4663                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1232                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      932                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      716                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      303                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      246                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -188,172 +188,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     9675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    10762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    11991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    12258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    13286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    12907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    12909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    12445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    12840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    10190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    10077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     9379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    11881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    11813                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    11317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    11573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      557                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::37                      349                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::39                      269                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::43                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      182                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::48                      125                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::50                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        95193                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      270.047419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.647814                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.885603                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          47290     49.68%     49.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18811     19.76%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6810      7.15%     76.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3608      3.79%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3189      3.35%     83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2125      2.23%     85.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1286      1.35%     87.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1091      1.15%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10983     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          95193                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7956                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.345777                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      514.192665                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7955     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7956                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7956                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.139517                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.869319                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.452539                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6216     78.13%     78.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             561      7.05%     85.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              92      1.16%     86.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             246      3.09%     89.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             152      1.91%     91.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              55      0.69%     92.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              34      0.43%     92.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              37      0.47%     92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             126      1.58%     94.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.23%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              19      0.24%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               9      0.11%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              35      0.44%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              15      0.19%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.11%     95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              35      0.44%     96.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              47      0.59%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              11      0.14%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               5      0.06%     97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               9      0.11%     97.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              88      1.11%     98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.04%     98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             8      0.10%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            17      0.21%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             6      0.08%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             8      0.10%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.04%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            29      0.36%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            10      0.13%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.03%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.05%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             7      0.09%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             7      0.09%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             5      0.06%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             6      0.08%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.01%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             3      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             5      0.06%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             2      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7956                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8935367250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               13014767250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1087840000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       41069.31                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        89336                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      261.529865                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     143.433799                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.548299                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46507     52.06%     52.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17145     19.19%     71.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5910      6.62%     77.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3229      3.61%     81.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2663      2.98%     84.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1401      1.57%     86.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          977      1.09%     87.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1056      1.18%     88.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10448     11.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          89336                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7194                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.049903                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      528.366464                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7192     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7194                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7194                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.695580                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.063476                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.872294                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            6078     84.49%     84.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             276      3.84%     88.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             196      2.72%     91.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              78      1.08%     92.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             140      1.95%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              36      0.50%     94.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              37      0.51%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              44      0.61%     95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              68      0.95%     96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              17      0.24%     96.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             97      1.35%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            14      0.19%     98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            17      0.24%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            12      0.17%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            42      0.58%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             4      0.06%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            10      0.14%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             3      0.04%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             8      0.11%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.06%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             1      0.01%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             1      0.01%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.03%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-343             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7194                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6681295250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10330007750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    972990000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34333.83                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  59819.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.93                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.22                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53083.83                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.41                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.35                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.90                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.29                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.31                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     184937                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    121536                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.00                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.01                       # Row buffer hit rate for writes
-system.physmem.avgGap                      6923437.45                       # Average gap between requests
-system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2697464747500                       # Time in different power states
-system.physmem.memoryStateTime::REF       94318380000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       32780541250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 374477040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 345182040                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 204327750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 188343375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                878716800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                818313600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               606787200                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               586167840                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184486751280                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184486751280                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           79037968995                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           78368155155                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625406641250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1625994197250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1890995670315                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1890787110540                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.482406                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.408568                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.38                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     162654                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    113073                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.58                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                      7611731.47                       # Average gap between requests
+system.physmem.pageHitRate                      75.52                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  347571000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  189646875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 781614600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                563014800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184531504560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            79272493785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625612031750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1891297877370                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.427007                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704246406250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94341260000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     26661192500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  327809160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  178864125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 736242000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                541604880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184531504560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            78684430770                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626127876500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1891128331995                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.366996                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705112983500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94341260000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     25799982000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
@@ -378,16 +367,24 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               24032454                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         15719473                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           977282                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            14661590                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               10774814                       # Number of BTB hits
+system.cpu0.branchPred.lookups               23750953                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         15527618                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           965372                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            14472059                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               10661692                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.490078                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3879582                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             32449                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            73.670872                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3843618                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             32002                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -409,27 +406,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                    61986                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               61986                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26264                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18370                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        17352                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        44634                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   336.413945                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  2220.174334                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        43963     98.50%     98.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          507      1.14%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575           73      0.16%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767           64      0.14%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           21      0.05%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        44634                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        13427                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean  7972.648842                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  6416.497879                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  8239.915942                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        13383     99.67%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           25      0.19%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            6      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           10      0.07%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        13427                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  89356407948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.591290                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.497127                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    36606156956     40.97%     40.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    52714291992     58.99%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2       18812000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3        8121500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4        2346000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5        1919500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6        1535000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7         979500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8         384000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9         515500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10        241000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11        224500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12        422000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::13        109500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14         86500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15        262500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  89356407948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         4894     78.56%     78.56% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1336     21.44%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6230                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        61986                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        61986                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6230                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6230                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        68216                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    17723797                       # DTB read hits
-system.cpu0.dtb.read_misses                     56461                       # DTB read misses
-system.cpu0.dtb.write_hits                   14648555                       # DTB write hits
-system.cpu0.dtb.write_misses                     8741                       # DTB write misses
+system.cpu0.dtb.read_hits                    17554590                       # DTB read hits
+system.cpu0.dtb.read_misses                     54209                       # DTB read misses
+system.cpu0.dtb.write_hits                   14392399                       # DTB write hits
+system.cpu0.dtb.write_misses                     7777                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3527                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      309                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2355                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3403                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      317                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2330                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      868                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                17780258                       # DTB read accesses
-system.cpu0.dtb.write_accesses               14657296                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      789                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17608799                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14400176                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         32372352                       # DTB hits
-system.cpu0.dtb.misses                          65202                       # DTB misses
-system.cpu0.dtb.accesses                     32437554                       # DTB accesses
+system.cpu0.dtb.hits                         31946989                       # DTB hits
+system.cpu0.dtb.misses                          61986                       # DTB misses
+system.cpu0.dtb.accesses                     32008975                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -451,8 +516,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    37754755                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10287                       # ITB inst misses
+system.cpu0.itb.walker.walks                    10002                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               10002                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3947                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5990                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore           65                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         9937                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   314.380598                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  1718.762352                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-2047         9514     95.74%     95.74% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::2048-4095           89      0.90%     96.64% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-6143           92      0.93%     97.56% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::6144-8191          156      1.57%     99.13% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-10239           23      0.23%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::10240-12287           21      0.21%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-14335           10      0.10%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::14336-16383            9      0.09%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-18431            7      0.07%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::18432-20479            4      0.04%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-22527            2      0.02%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::22528-24575            4      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-26623            2      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::26624-28671            3      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-30719            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         9937                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2600                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean  9117.887308                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  7551.234816                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5655.414847                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191         1525     58.65%     58.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383          976     37.54%     96.19% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575           32      1.23%     97.42% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           60      2.31%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            5      0.19%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2600                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  20627596212                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.981751                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.134001                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      376836000      1.83%      1.83% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    20250383712     98.17%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         360000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          16500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  20627596212                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2218     87.50%     87.50% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          317     12.50%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2535                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10002                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10002                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2535                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2535                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        12537                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    37321844                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10002                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -461,500 +580,500 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2369                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2308                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1949                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1915                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                37765042                       # ITB inst accesses
-system.cpu0.itb.hits                         37754755                       # DTB hits
-system.cpu0.itb.misses                          10287                       # DTB misses
-system.cpu0.itb.accesses                     37765042                       # DTB accesses
-system.cpu0.numCycles                       126967483                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                37331846                       # ITB inst accesses
+system.cpu0.itb.hits                         37321844                       # DTB hits
+system.cpu0.itb.misses                          10002                       # DTB misses
+system.cpu0.itb.accesses                     37331846                       # DTB accesses
+system.cpu0.numCycles                       127490392                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          18140354                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     112726031                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   24032454                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          14654396                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    104803073                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2823208                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    134368                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               38414                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       364228                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       430065                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        37874                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 37755386                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               265155                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3922                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         125359980                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.084816                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.263057                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          18416586                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     111347815                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   23750953                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          14505310                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    103542853                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2791794                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    127823                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               53549                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       359263                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       418714                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles        68477                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 37322509                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               269100                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3836                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         124383162                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.079346                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.261981                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                62797458     50.09%     50.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                21463892     17.12%     67.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 8767294      6.99%     74.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                32331336     25.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                62596919     50.33%     50.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                21226112     17.07%     67.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 8654044      6.96%     74.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                31906087     25.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           125359980                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.189280                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.887834                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                19213877                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58702572                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 41417912                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4958150                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1067469                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3055480                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               348347                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             110732586                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3998245                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1067469                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                24964892                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12028946                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      36555738                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 40486723                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10256212                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             105650222                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1060720                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1433198                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                161272                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 61252                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6057790                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          109732658                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            482396625                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       120923658                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9389                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             98143798                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                11588857                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1229050                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1087734                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12319550                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            18736791                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           16202841                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1700720                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2277601                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 102690318                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1694621                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                100676052                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           483863                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9017764                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     22481770                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        122874                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    125359980                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.803096                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.034807                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           124383162                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.186296                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.873382                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                19346102                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             58140113                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 40971754                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4869688                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1055505                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3027271                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               344448                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             109400605                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3934770                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1055505                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                25005985                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               11977086                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      36202111                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 40046327                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10096148                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             104386948                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1045357                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1411792                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                159433                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 59086                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               5966912                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          108436619                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            476371377                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       119317721                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             9226                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             97033193                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11403415                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1211111                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1071444                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12097609                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            18549268                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           15931724                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1681801                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2123013                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 101474466                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1673346                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 99505309                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           475979                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        8870309                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     22101778                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        120255                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    124383162                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.799990                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.034146                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           69212985     55.21%     55.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           23181797     18.49%     73.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           22515986     17.96%     91.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            9334603      7.45%     99.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1114571      0.89%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 38      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           68905319     55.40%     55.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           22874220     18.39%     73.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           22288669     17.92%     91.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            9206102      7.40%     99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1108815      0.89%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 37      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      125359980                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      124383162                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                9379077     40.75%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    80      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5582793     24.26%     65.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8054863     35.00%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                9283826     40.69%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    70      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5520798     24.20%     64.89% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8011764     35.11%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             66413118     65.97%     65.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               93141      0.09%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8113      0.01%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            18432239     18.31%     84.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           15727166     15.62%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2266      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             65682798     66.01%     66.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               92825      0.09%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8012      0.01%     66.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            18253823     18.34%     84.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           15465584     15.54%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             100676052                       # Type of FU issued
-system.cpu0.iq.rate                          0.792928                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   23016813                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228623                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         350180984                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        113410550                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     98587478                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              31776                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11293                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9721                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             123670062                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  20530                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          365459                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              99505309                       # Type of FU issued
+system.cpu0.iq.rate                          0.780493                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   22816458                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.229299                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         346654844                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        112025701                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     97442801                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              31372                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             11049                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         9514                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             122299120                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  20381                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          360751                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2006136                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2602                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        19208                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1021760                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1973339                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2498                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18704                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1001610                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       106419                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       336961                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       104951                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       329906                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1067469                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1620814                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               189225                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          104559654                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               1055505                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1579113                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               185823                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          103314574                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             18736791                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            16202841                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            876235                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 27148                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               138418                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         19208                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        291783                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       400552                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              692335                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             99578675                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             17975392                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1032310                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             18549268                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            15931724                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            862014                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 26297                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               136520                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18704                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        287591                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       395520                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              683111                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             98423737                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             17803606                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1019712                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       174715                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    33511345                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                16844732                       # Number of branches executed
-system.cpu0.iew.exec_stores                  15535953                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.784285                       # Inst execution rate
-system.cpu0.iew.wb_sent                      99047596                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     98597199                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 51323656                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 84802398                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       166762                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    33081779                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                16674739                       # Number of branches executed
+system.cpu0.iew.exec_stores                  15278173                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.772009                       # Inst execution rate
+system.cpu0.iew.wb_sent                      97898733                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     97452315                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 50771632                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 83764488                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.776555                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.605215                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.764389                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.606124                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        8524425                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1571747                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           633147                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    123606126                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.768066                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.480848                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        8390139                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1553091                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           624980                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    122653513                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.765118                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.477688                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     79269760     64.13%     64.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     24721020     20.00%     84.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      8248963      6.67%     90.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3214548      2.60%     93.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      3440916      2.78%     96.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      1523839      1.23%     97.42% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1135185      0.92%     98.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       534039      0.43%     98.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1517856      1.23%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     78804860     64.25%     64.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     24438835     19.93%     84.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      8183554      6.67%     90.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3164514      2.58%     93.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      3412948      2.78%     96.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      1509244      1.23%     97.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1121963      0.91%     98.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       525683      0.43%     98.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1491912      1.22%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    123606126                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            78906627                       # Number of instructions committed
-system.cpu0.commit.committedOps              94937680                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    122653513                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            78072085                       # Number of instructions committed
+system.cpu0.commit.committedOps              93844352                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      31911736                       # Number of memory references committed
-system.cpu0.commit.loads                     16730655                       # Number of loads committed
-system.cpu0.commit.membars                     647181                       # Number of memory barriers committed
-system.cpu0.commit.branches                  16206992                       # Number of branches committed
-system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 81886422                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             1929931                       # Number of function calls committed.
+system.cpu0.commit.refs                      31506042                       # Number of memory references committed
+system.cpu0.commit.loads                     16575928                       # Number of loads committed
+system.cpu0.commit.membars                     642248                       # Number of memory barriers committed
+system.cpu0.commit.branches                  16047033                       # Number of branches committed
+system.cpu0.commit.fp_insts                      9500                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 80932371                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             1914804                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        62927104     66.28%     66.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          90727      0.10%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8113      0.01%     66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       16730655     17.62%     84.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      15181081     15.99%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        62239958     66.32%     66.32% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          90340      0.10%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8012      0.01%     66.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       16575928     17.66%     84.09% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      14930114     15.91%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         94937680                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1517856                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         93844352                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1491912                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   221365586                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  208677314                       # The number of ROB writes
-system.cpu0.timesIdled                         109557                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        1607503                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5522172985                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   78784576                       # Number of Instructions Simulated
-system.cpu0.committedOps                     94815629                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.611578                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.611578                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.620510                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.620510                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               110621221                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               59741549                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8143                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                350793071                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                41074475                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              246484638                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1224545                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           712867                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          493.083932                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28844186                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           713379                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            40.433186                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        256881000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.083932                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.963055                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.963055                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   219244998                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  206197797                       # The number of ROB writes
+system.cpu0.timesIdled                         126478                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3107230                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5523018391                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   77956509                       # Number of Instructions Simulated
+system.cpu0.committedOps                     93728776                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.635404                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.635404                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.611470                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.611470                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               109237443                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               59093647                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     8049                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                    2136                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                346833598                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                40564465                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              243214174                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1207250                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           702516                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          497.143728                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28480758                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           703028                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            40.511556                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        256726000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.143728                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970984                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.970984                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63487140                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63487140                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15590249                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       15590249                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12072536                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12072536                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       311110                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       311110                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363193                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       363193                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360660                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       360660                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27662785                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27662785                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     27973895                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       27973895                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       638253                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       638253                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1832121                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1832121                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       146008                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       146008                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25001                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        25001                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20609                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20609                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2470374                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2470374                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2616382                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2616382                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8112547038                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8112547038                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24972133492                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  24972133492                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    394969003                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    394969003                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    454279790                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    454279790                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       381000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       381000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  33084680530                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  33084680530                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  33084680530                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  33084680530                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     16228502                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     16228502                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13904657                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13904657                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457118                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       457118                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388194                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       388194                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381269                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381269                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     30133159                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     30133159                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     30590277                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     30590277                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039329                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.039329                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.131763                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.131763                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.319410                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.319410                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064403                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064403                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054054                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054054                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081982                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.081982                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085530                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.085530                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.550578                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.550578                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13630.176987                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 13630.176987                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15798.128195                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15798.128195                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22042.786647                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22042.786647                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         62650967                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        62650967                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15440226                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15440226                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     11830536                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      11830536                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306667                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       306667                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       359893                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       359893                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       358331                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       358331                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27270762                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27270762                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     27577429                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       27577429                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       630655                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       630655                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1827082                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1827082                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147933                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       147933                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25364                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25364                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20059                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20059                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2457737                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2457737                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2605670                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2605670                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8272706723                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   8272706723                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  25439418868                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  25439418868                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    389472743                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    389472743                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    444610334                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    444610334                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       421500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       421500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  33712125591                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  33712125591                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  33712125591                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  33712125591                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16070881                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16070881                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13657618                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13657618                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       454600                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       454600                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       385257                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       385257                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       378390                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       378390                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     29728499                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     29728499                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30183099                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30183099                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039242                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.039242                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.133778                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.133778                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.325414                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.325414                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065837                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065837                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053011                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053011                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082673                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.082673                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086329                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086329                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13117.642329                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13117.642329                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13923.523338                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 13923.523338                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15355.336027                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15355.336027                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22165.129568                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22165.129568                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1345                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      3372122                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               71                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         191319                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.943662                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    17.625651                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13716.734374                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12937.987386                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12937.987386                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          953                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      3495034                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               56                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         184351                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.017857                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    18.958584                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       512814                       # number of writebacks
-system.cpu0.dcache.writebacks::total           512814                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       248043                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       248043                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1519569                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1519569                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18426                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18426                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1767612                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1767612                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1767612                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1767612                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       390210                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       390210                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312552                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312552                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101508                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       101508                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6575                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6575                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20609                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20609                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       702762                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       702762                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       804270                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       804270                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4184101504                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4184101504                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5001279356                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5001279356                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1410085492                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1410085492                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97668747                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97668747                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    412365210                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    412365210                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       359000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       359000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9185380860                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9185380860                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10595466352                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10595466352                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4216928747                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4216928747                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3186876498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3186876498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7403805245                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7403805245                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024045                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024045                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.022478                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022478                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222061                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222061                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016937                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016937                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054054                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054054                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023322                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023322                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026292                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026292                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       508420                       # number of writebacks
+system.cpu0.dcache.writebacks::total           508420                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       245938                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       245938                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1508738                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1508738                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18883                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18883                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1754676                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1754676                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1754676                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1754676                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       384717                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       384717                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       318344                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       318344                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102343                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       102343                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6481                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6481                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20059                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20059                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       703061                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       703061                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       805404                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       805404                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4089649462                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4089649462                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4952590494                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4952590494                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1562592504                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1562592504                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94643501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94643501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    403849666                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    403849666                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       399500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       399500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9042239956                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9042239956                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10604832460                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10604832460                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4215061000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4215061000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3183836000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3183836000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7398897000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7398897000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023939                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023939                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023309                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023309                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225128                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225128                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016823                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016823                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053011                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053011                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023649                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023649                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026684                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026684                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12861.245263                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12861.245263                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13167.096836                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13167.096836                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -962,420 +1081,429 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1263628                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.774293                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           36451354                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1264140                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            28.834903                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6311559000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774293                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999559                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999559                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1252930                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.771234                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36023030                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1253442                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            28.739287                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6360261750                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.771234                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999553                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999553                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          133                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         76768570                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        76768570                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     36451354                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       36451354                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     36451354                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        36451354                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     36451354                       # number of overall hits
-system.cpu0.icache.overall_hits::total       36451354                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1300843                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1300843                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1300843                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1300843                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1300843                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1300843                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11016228057                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11016228057                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11016228057                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11016228057                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11016228057                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11016228057                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     37752197                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     37752197                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     37752197                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     37752197                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     37752197                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     37752197                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034457                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.034457                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034457                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.034457                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034457                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.034457                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8468.530066                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8468.530066                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8468.530066                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8468.530066                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       721640                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs            96102                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.509105                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets           42                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses         75891509                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        75891509                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36023030                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36023030                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36023030                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36023030                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36023030                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36023030                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1295987                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1295987                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1295987                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1295987                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1295987                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1295987                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12767063333                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  12767063333                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  12767063333                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  12767063333                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  12767063333                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  12767063333                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     37319017                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     37319017                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     37319017                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     37319017                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     37319017                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     37319017                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034727                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.034727                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034727                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.034727                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034727                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.034727                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9851.227931                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9851.227931                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9851.227931                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9851.227931                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9851.227931                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9851.227931                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1314207                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          320                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           107284                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.249795                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets           32                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        36666                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        36666                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        36666                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        36666                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        36666                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        36666                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264177                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1264177                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264177                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1264177                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264177                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1264177                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8917861032                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8917861032                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8917861032                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8917861032                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8917861032                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8917861032                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    244130748                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    244130748                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033486                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.033486                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.033486                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7054.281981                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42511                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        42511                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        42511                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        42511                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        42511                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        42511                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1253476                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1253476                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1253476                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1253476                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1253476                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1253476                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10355026178                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10355026178                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10355026178                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10355026178                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10355026178                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10355026178                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    243898498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    243898498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    243898498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    243898498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033588                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033588                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033588                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.033588                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033588                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.033588                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8261.048618                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8261.048618                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8261.048618                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8261.048618                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8261.048618                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8261.048618                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     11568415                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       525589                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     10417206                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       118474                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit        25510                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       481631                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       881553                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements          396536                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16205.751344                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2245612                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          412784                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.440162                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle    2809249850500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  4624.087674                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    10.817381                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.808377                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   942.420690                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1398.445665                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9228.171558                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.282232                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000660                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000110                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.057521                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.085354                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.563243                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989121                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8089                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8146                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           44                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          199                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3272                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4134                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          440                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          478                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3751                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3581                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          270                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.493713                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.497192                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        43591487                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       43591487                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        54584                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12527                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1242350                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data       407474                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total       1716935                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       512814                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       512814                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        15317                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        15317                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2112                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2112                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       216670                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       216670                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        54584                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12527                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1242350                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       624144                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1933605                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        54584                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12527                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1242350                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       624144                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1933605                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          547                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          204                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst        21799                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data        90709                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       113259                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27943                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27943                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18497                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18497                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        52796                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        52796                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          547                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          204                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        21799                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       143505                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       166055                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          547                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          204                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        21799                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       143505                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       166055                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     14446999                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4916500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    810567190                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2703489870                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   3533420559                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    501086453                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    501086453                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    362300280                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    362300280                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       348000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       348000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2600330023                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2600330023                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     14446999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4916500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst    810567190                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   5303819893                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   6133750582                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     14446999                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4916500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst    810567190                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   5303819893                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   6133750582                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        55131                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12731                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1264149                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data       498183                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total      1830194                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       512814                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       512814                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        43260                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        43260                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20609                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20609                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269466                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269466                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        55131                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12731                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1264149                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       767649                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2099660                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        55131                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12731                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1264149                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       767649                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2099660                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.017244                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.182080                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.061884                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.645932                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.645932                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.897521                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.897521                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.195928                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.195928                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.017244                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.186941                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.079087                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.017244                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.186941                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.079087                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.686866                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29803.987146                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31197.702249                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17932.450095                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17932.450095                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19586.975185                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19586.975185                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49252.405921                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49252.405921                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 36938.066195                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 36938.066195                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs        63742                       # number of cycles access was blocked
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1786740                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1791804                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         4513                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage       232652                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          271541                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16114.824240                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           2179855                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          287784                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            7.574622                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  7401.476938                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.779155                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.071208                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5022.663817                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1991.190162                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1686.642960                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.451750                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000780                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.306559                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.121533                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.102945                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983571                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1106                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15123                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           20                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          157                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          467                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          462                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          483                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4242                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5796                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4505                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.067505                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.923035                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        43185169                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       43185169                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        51927                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        11921                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1199916                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.data       396490                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total       1660254                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks       508419                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total       508419                       # number of Writeback hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28435                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        28435                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1750                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total         1750                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       214572                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       214572                       # number of ReadExReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        51927                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker        11921                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1199916                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       611062                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1874826                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        51927                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker        11921                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1199916                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       611062                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1874826                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          385                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          135                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst        53537                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.data        96948                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total       151005                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26067                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26067                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18308                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18308                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        49454                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        49454                       # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          385                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          135                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        53537                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       146402                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       200459                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          385                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          135                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        53537                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       146402                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       200459                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     10304000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3078250                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2513333739                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2834189427                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   5360905416                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    466106536                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    466106536                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    359161772                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    359161772                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       388500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       388500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2526024290                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2526024290                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     10304000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3078250                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2513333739                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   5360213717                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   7886929706                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     10304000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3078250                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2513333739                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   5360213717                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   7886929706                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        52312                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12056                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1253453                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data       493438                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total      1811259                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks       508419                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total       508419                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        54502                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20058                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20058                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       264026                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       264026                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        52312                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12056                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1253453                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       757464                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2075285                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        52312                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12056                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1253453                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       757464                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2075285                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007360                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.011198                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.042712                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.196475                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.083370                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.478276                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.478276                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.912753                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.912753                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.187307                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.187307                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007360                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.011198                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042712                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.193279                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.096593                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007360                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.011198                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042712                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.193279                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.096593                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26763.636364                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22801.851852                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46945.733586                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29234.119600                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35501.509328                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17881.096252                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17881.096252                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19617.750273                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.750273                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       388500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       388500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51078.260404                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51078.260404                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26763.636364                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22801.851852                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46945.733586                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36612.981496                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 39344.353239                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26763.636364                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22801.851852                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46945.733586                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36612.981496                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 39344.353239                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           65                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            1448                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    44.020718                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    16.250000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       211838                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          211838                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       194082                       # number of writebacks
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 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
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-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         3181                       # number of ReadReq MSHR hits
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-system.cpu0.l2cache.ReadExReq_mshr_hits::total         8830                       # number of ReadExReq MSHR hits
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 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         5563                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        12011                       # number of demand (read+write) MSHR hits
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 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         5563                       # number of overall MSHR hits
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-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        87528                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total       104514                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       481628                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       481628                       # number of HardPFReq MSHR misses
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-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27943                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18497                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18497                       # number of SCUpgradeReq MSHR misses
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10612999                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21954581331                       # number of HardPFReq MSHR miss cycles
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-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    482225838                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    249631743                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    249631743                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       271000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       271000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1320074621                       # number of ReadExReq MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10612999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3482500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26067                       # number of UpgradeReq MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    218480000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4052038481                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4270518481                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3037285940                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7089324421                       # number of overall MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007321                       # mshr miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.042686                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.194809                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.082897                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.645932                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.645932                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.897521                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.897521                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163160                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163160                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.070716                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.478276                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.478276                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.912753                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.912753                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.157375                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.157375                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007321                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.011115                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042686                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.181760                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.092372                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007321                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.011115                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042686                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.181760                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.300100                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207616                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39830.534698                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22013.107099                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28351.226403                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62677.901511                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17152.067442                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17152.067442                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13390.146166                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13390.146166                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       311500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       311500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36393.851676                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1385,67 +1513,76 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq       2021847                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1920670                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        19105                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19105                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       512814                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       646384                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq       1959682                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1897898                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19079                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19079                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback       508419                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       329547                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp          131                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        80933                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43154                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       104914                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       291875                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       281146                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2534329                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2360353                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29069                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       120916                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          5044667                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80953504                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86188042                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50924                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       220524                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         167412994                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1039110                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3610193                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.254626                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.435651                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        88597                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42717                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       112274                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       292255                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       279169                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2512932                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2353027                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        27983                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       115316                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5009258                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80268960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     85221321                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        48224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       209248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         165747753                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     677561                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3234113                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.173543                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.378716                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5           2690945     74.54%     74.54% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6            919248     25.46%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5           2672856     82.65%     82.65% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6            561257     17.35%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3610193                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    1889992000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3234113                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    1876283497                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    117303500                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    114853000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1901297082                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1888093495                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1220075844                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1210751284                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     16351973                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     15934735                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     65816442                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     63036190                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               33910806                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         11562772                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           305112                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            18755942                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               14959399                       # Number of BTB hits
+system.cpu1.branchPred.lookups               34134097                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         11727075                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           316019                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            18898892                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               15069568                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            79.758185                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               12490105                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              7221                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            79.737839                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               12517859                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7561                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1467,27 +1604,99 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                    23600                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               23600                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8914                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6871                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         7815                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        15785                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   672.093760                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3265.172364                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        14984     94.93%     94.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          394      2.50%     97.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287           71      0.45%     97.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383          205      1.30%     99.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           14      0.09%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           30      0.19%     99.45% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671           46      0.29%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           19      0.12%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863           16      0.10%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::45056-49151            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-53247            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        15785                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5984                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean  7948.780916                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  6651.023666                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5565.886785                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         4665     77.96%     77.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383          897     14.99%     92.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          299      5.00%     97.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           93      1.55%     99.50% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959            7      0.12%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           21      0.35%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495            2      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         5984                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  71907287764                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.149161                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.363512                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    61231753172     85.15%     85.15% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    10656881592     14.82%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       10600500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        3048000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4        1243000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         909500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         707500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         390500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8         165000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9         220500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         87000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11        114500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12        127500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         62500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14        410000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        567000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  71907287764                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         2101     76.21%     76.21% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          656     23.79%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2757                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        23600                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        23600                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2757                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2757                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        26357                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    10163643                       # DTB read hits
-system.cpu1.dtb.read_misses                     18794                       # DTB read misses
-system.cpu1.dtb.write_hits                    6541990                       # DTB write hits
-system.cpu1.dtb.write_misses                     2867                       # DTB write misses
+system.cpu1.dtb.read_hits                    10322903                       # DTB read hits
+system.cpu1.dtb.read_misses                     19223                       # DTB read misses
+system.cpu1.dtb.write_hits                    6788033                       # DTB write hits
+system.cpu1.dtb.write_misses                     4377                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2050                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       58                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   373                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2089                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       54                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   392                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      409                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                10182437                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6544857                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      398                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                10342126                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6792410                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         16705633                       # DTB hits
-system.cpu1.dtb.misses                          21661                       # DTB misses
-system.cpu1.dtb.accesses                     16727294                       # DTB accesses
+system.cpu1.dtb.hits                         17110936                       # DTB hits
+system.cpu1.dtb.misses                          23600                       # DTB misses
+system.cpu1.dtb.accesses                     17134536                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1509,8 +1718,65 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    43641889                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7003                       # ITB inst misses
+system.cpu1.itb.walker.walks                     7135                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7135                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4170                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2894                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore           71                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7064                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   161.877123                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1382.094776                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-2047         6918     97.93%     97.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::2048-4095           45      0.64%     98.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-6143           37      0.52%     99.09% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::6144-8191           22      0.31%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-10239           14      0.20%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::10240-12287            9      0.13%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-14335            4      0.06%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::14336-16383            3      0.04%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::18432-20479            2      0.03%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-22527            1      0.01%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::22528-24575            2      0.03%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-26623            4      0.06%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::26624-28671            2      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-30719            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7064                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1280                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean  9064.455469                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  7676.805908                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5570.114480                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095          198     15.47%     15.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          721     56.33%     71.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287           25      1.95%     73.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          272     21.25%     95.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479            5      0.39%     95.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575           10      0.78%     96.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           21      1.64%     97.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.48%     99.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.08%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.47%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.08%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1280                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  16042620916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.990716                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.095951                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      149006264      0.93%      0.93% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    15893540152     99.07%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2          74500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  16042620916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1033     85.44%     85.44% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          176     14.56%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1209                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7135                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7135                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1209                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1209                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         8344                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    43998995                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7135                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1519,98 +1785,98 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1205                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1239                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      544                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      569                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                43648892                       # ITB inst accesses
-system.cpu1.itb.hits                         43641889                       # DTB hits
-system.cpu1.itb.misses                           7003                       # DTB misses
-system.cpu1.itb.accesses                     43648892                       # DTB accesses
-system.cpu1.numCycles                       104622935                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                44006130                       # ITB inst accesses
+system.cpu1.itb.hits                         43998995                       # DTB hits
+system.cpu1.itb.misses                           7135                       # DTB misses
+system.cpu1.itb.accesses                     44006130                       # DTB accesses
+system.cpu1.numCycles                       106356723                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           9986788                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     109166158                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   33910806                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          27449504                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     91794015                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3775656                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     78908                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               31556                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       200392                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       294710                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         7499                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 43641278                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               116202                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2270                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         104281696                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.296833                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.339781                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          10248604                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     110247468                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   34134097                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          27587427                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     92894950                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3804096                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     79886                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               35043                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       199386                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       306315                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        18555                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 43998345                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               120822                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2367                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         105684787                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.292794                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.339203                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                47334317     45.39%     45.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                14034977     13.46%     58.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 7536210      7.23%     66.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                35376192     33.92%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                48118877     45.53%     45.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                14213464     13.45%     58.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 7642144      7.23%     66.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                35710302     33.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           104281696                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.324124                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.043425                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                13018026                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             61674095                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 26725105                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1111367                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1753103                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              754241                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               137598                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              68060945                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1169140                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1753103                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                17450583                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2252903                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      56981552                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 23380155                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2463400                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              55156301                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               230486                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               263427                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 35391                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 18241                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1436172                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           55002320                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            260520543                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        58679791                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1657                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             52223668                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 2778652                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1878098                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1805410                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 13101415                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            10456972                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6914054                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           629493                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          831483                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  54264321                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             589116                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 53908666                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           111755                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2291961                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      5808692                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         48780                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    104281696                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.516952                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.852554                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           105684787                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.320940                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.036582                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                13299736                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             62299682                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 27136759                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1184524                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1764086                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              778297                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               140897                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              69265057                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1207807                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1764086                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                17799261                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2243721                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      57294733                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 23798018                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2784968                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              56317455                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               239325                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               267963                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 37417                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 15706                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1709289                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           56195584                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            266063253                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        60158486                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             1810                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             53296548                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2899036                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1893782                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1819648                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 13269922                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            10622155                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            7171113                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           643276                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          895479                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  55388735                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             607798                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 55019063                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           118019                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2383882                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      6031867                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         50125                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    105684787                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.520596                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.855641                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           71029795     68.11%     68.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           16529290     15.85%     83.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           13075763     12.54%     96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3359554      3.22%     99.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             287282      0.28%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           71804994     67.94%     67.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           16804413     15.90%     83.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           13307202     12.59%     96.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3472478      3.29%     99.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             295688      0.28%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
@@ -1618,400 +1884,400 @@ system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Nu
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      104281696                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      105684787                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2925282     45.12%     45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   677      0.01%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1673331     25.81%     70.93% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1884639     29.07%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3013223     44.49%     44.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   670      0.01%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1729221     25.53%     70.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              2029703     29.97%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             36727327     68.13%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               46544      0.09%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3339      0.01%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            10380092     19.25%     87.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            6751298     12.52%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               73      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             37421348     68.02%     68.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               46238      0.08%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3333      0.01%     68.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            10544210     19.16%     87.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            7003861     12.73%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              53908666                       # Type of FU issued
-system.cpu1.iq.rate                          0.515266                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    6483929                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.120276                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         218688932                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         57153517                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     51920276                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               5780                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              60388837                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   3692                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           91402                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              55019063                       # Type of FU issued
+system.cpu1.iq.rate                          0.517307                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    6772817                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.123099                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         222607082                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         58388753                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     53008185                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               6667                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              2258                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         1929                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              61787450                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   4357                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           94839                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       490292                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          689                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10197                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       355874                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       509093                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          756                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        10627                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       368944                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        52006                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        70534                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        52621                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        79740                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1753103                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 547921                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               114364                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           54905583                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               1764086                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 541667                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               103172                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           56056220                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             10456972                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6914054                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            301613                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  9861                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                97001                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10197                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         54939                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       127326                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              182265                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             53638641                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             10278143                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           248381                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             10622155                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             7171113                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            314475                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  9900                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                85548                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         10627                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         58910                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       131027                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              189937                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             54736921                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             10438101                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           258564                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        52146                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    16965109                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                11808008                       # Number of branches executed
-system.cpu1.iew.exec_stores                   6686966                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.512685                       # Inst execution rate
-system.cpu1.iew.wb_sent                      53497702                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     51922060                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 25229975                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 38490431                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        59687                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    17373742                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                11974777                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6935641                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.514654                       # Inst execution rate
+system.cpu1.iew.wb_sent                      54589285                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     53010114                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 25746768                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 39490922                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.496278                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.655487                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.498418                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.651967                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        3657476                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         540336                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           170387                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    102349842                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.498091                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.159102                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        3744166                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         557673                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           178057                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    103735818                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.501583                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.163784                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     76769313     75.01%     75.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     14290135     13.96%     88.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6080073      5.94%     94.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       704006      0.69%     95.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1980080      1.93%     97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      1566587      1.53%     99.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       444714      0.43%     99.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       123770      0.12%     99.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       391164      0.38%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     77652029     74.86%     74.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     14577800     14.05%     88.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6160967      5.94%     94.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       757264      0.73%     95.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      2015553      1.94%     97.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      1576437      1.52%     99.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       460071      0.44%     99.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       129756      0.13%     99.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       405941      0.39%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    102349842                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            41393585                       # Number of instructions committed
-system.cpu1.commit.committedOps              50979540                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    103735818                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            42197750                       # Number of instructions committed
+system.cpu1.commit.committedOps              52032169                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      16524860                       # Number of memory references committed
-system.cpu1.commit.loads                      9966680                       # Number of loads committed
-system.cpu1.commit.membars                     209721                       # Number of memory barriers committed
-system.cpu1.commit.branches                  11640060                       # Number of branches committed
-system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 45829312                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             3366651                       # Number of function calls committed.
+system.cpu1.commit.refs                      16915231                       # Number of memory references committed
+system.cpu1.commit.loads                     10113062                       # Number of loads committed
+system.cpu1.commit.membars                     214317                       # Number of memory barriers committed
+system.cpu1.commit.branches                  11798243                       # Number of branches committed
+system.cpu1.commit.fp_insts                      1928                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 46741115                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             3380053                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        34405704     67.49%     67.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          45637      0.09%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.58% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3339      0.01%     67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        9966680     19.55%     87.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       6558180     12.86%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        35068266     67.40%     67.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          45339      0.09%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3333      0.01%     67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       10113062     19.44%     86.93% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       6802169     13.07%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         50979540                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               391164                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         52032169                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               405941                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   136558924                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  111202252                       # The number of ROB writes
-system.cpu1.timesIdled                          53311                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         341239                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5543976372                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   41360731                       # Number of Instructions Simulated
-system.cpu1.committedOps                     50946686                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.529523                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.529523                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.395331                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.395331                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                56284724                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               35740870                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1381                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                191161936                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                15560884                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              205876605                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                388900                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           191071                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.564441                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           15741519                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           191395                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            82.246239                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     102871508500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.564441                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922977                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.922977                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         32983738                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        32983738                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      9574548                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        9574548                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      5910552                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       5910552                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49554                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        49554                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79147                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        79147                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71001                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        71001                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     15485100                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        15485100                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     15534654                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       15534654                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       219354                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       219354                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       398461                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       398461                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30111                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30111                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18127                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        18127                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23403                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23403                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       617815                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        617815                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       647926                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       647926                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3453063988                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3453063988                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8746670918                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8746670918                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363087750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    363087750                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    542334299                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    542334299                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       511000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       511000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  12199734906                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12199734906                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  12199734906                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12199734906                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9793902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9793902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      6309013                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      6309013                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79665                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79665                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97274                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        97274                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94404                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        94404                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     16102915                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     16102915                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     16182580                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     16182580                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022397                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.063157                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.063157                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377970                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377970                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186350                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186350                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.247903                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.247903                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038367                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038367                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040038                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.040038                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456                       # average StoreCondReq miss latency
+system.cpu1.rob.rob_reads                   139039973                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  113498046                       # The number of ROB writes
+system.cpu1.timesIdled                          59982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         671936                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5543606797                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   42158419                       # Number of Instructions Simulated
+system.cpu1.committedOps                     51992838                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.522787                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.522787                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.396387                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.396387                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                57596911                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               36337307                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     1495                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                     580                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                194912842                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                16071052                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              208513912                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                404751                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           201045                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          470.607708                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           16083620                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           201364                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            79.873364                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      93308892000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   470.607708                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.919156                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.919156                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          319                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          304                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.623047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         33778764                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        33778764                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      9715738                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        9715738                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      6106545                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       6106545                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50809                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50809                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81509                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81509                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        73252                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        73252                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     15822283                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        15822283                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     15873092                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       15873092                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       224637                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       224637                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       441375                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       441375                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        31038                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        31038                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18294                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        18294                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23669                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23669                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       666012                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        666012                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       697050                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       697050                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3524459329                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3524459329                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10055246312                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  10055246312                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    359810249                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    359810249                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    545166265                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    545166265                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       431000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       431000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  13579705641                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  13579705641                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  13579705641                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  13579705641                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9940375                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9940375                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6547920                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6547920                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        81847                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        81847                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        99803                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        99803                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        96921                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        96921                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     16488295                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     16488295                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     16570142                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     16570142                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022598                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.022598                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.067407                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.067407                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.379220                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.379220                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.183301                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.183301                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.244209                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.244209                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040393                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040393                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.042067                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.042067                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          358                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1116392                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               38                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          39638                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.421053                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    28.164690                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          432                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1443381                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               46                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          45166                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.391304                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    31.957247                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       117580                       # number of writebacks
-system.cpu1.dcache.writebacks::total           117580                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79511                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        79511                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306644                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       306644                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13188                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13188                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       386155                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       386155                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       386155                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       386155                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139843                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       139843                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91817                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        91817                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28628                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        28628                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4939                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4939                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23403                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23403                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       231660                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       231660                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       260288                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       260288                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1827288064                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1827288064                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2196971984                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2196971984                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494563997                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494563997                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87258999                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87258999                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    494349701                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    494349701                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       489000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       489000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4024260048                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4024260048                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4518824045                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4518824045                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298813494                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298813494                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826635494                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826635494                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125448988                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125448988                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014279                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014279                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014553                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014553                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359355                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359355                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050774                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050774                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.247903                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.247903                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014386                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.014386                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016084                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.016084                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       125175                       # number of writebacks
+system.cpu1.dcache.writebacks::total           125175                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        81304                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        81304                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       345063                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       345063                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13214                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13214                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       426367                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       426367                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       426367                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       426367                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143333                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       143333                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        96312                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        96312                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29478                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29478                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5080                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5080                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23669                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23669                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       239645                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       239645                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       269123                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       269123                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1836231651                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1836231651                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2306828153                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2306828153                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    473894752                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    473894752                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     85053999                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     85053999                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    496613735                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    496613735                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       413000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       413000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4143059804                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4143059804                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4616954556                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4616954556                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298741750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298741750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826982999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826982999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125724749                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125724749                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014419                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014419                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014709                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014709                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.360160                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.360160                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050900                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050900                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.244209                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.244209                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014534                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.014534                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016241                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.016241                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2019,425 +2285,425 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           607210                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.525690                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           43016771                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           607722                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            70.783633                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      78589984500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.525690                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975636                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975636                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           614958                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.494107                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           43363824                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           615470                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            70.456438                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      78768329500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.494107                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975574                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975574                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          493                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         87889967                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        87889967                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     43016771                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       43016771                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     43016771                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        43016771                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     43016771                       # number of overall hits
-system.cpu1.icache.overall_hits::total       43016771                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       624350                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       624350                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       624350                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        624350                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       624350                       # number of overall misses
-system.cpu1.icache.overall_misses::total       624350                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5095278041                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5095278041                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5095278041                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5095278041                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5095278041                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5095278041                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     43641121                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     43641121                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     43641121                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     43641121                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     43641121                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     43641121                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014306                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014306                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014306                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014306                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014306                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014306                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8160.932235                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8160.932235                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8160.932235                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8160.932235                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       275120                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            36110                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.618942                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses         88611673                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        88611673                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     43363824                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       43363824                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     43363824                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        43363824                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     43363824                       # number of overall hits
+system.cpu1.icache.overall_hits::total       43363824                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       634277                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       634277                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       634277                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        634277                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       634277                       # number of overall misses
+system.cpu1.icache.overall_misses::total       634277                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5597748699                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5597748699                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5597748699                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5597748699                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5597748699                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5597748699                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     43998101                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     43998101                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     43998101                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     43998101                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     43998101                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     43998101                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014416                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014416                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014416                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014416                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014416                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014416                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8825.400730                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8825.400730                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8825.400730                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8825.400730                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8825.400730                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8825.400730                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       423261                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets           12                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            39865                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    10.617359                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           12                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16625                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        16625                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        16625                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        16625                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        16625                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        16625                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       607725                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       607725                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       607725                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       607725                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       607725                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       607725                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4103508232                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4103508232                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4103508232                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4103508232                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4103508232                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4103508232                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8190250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8190250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013926                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.013926                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.013926                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6752.245229                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        18806                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        18806                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        18806                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        18806                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        18806                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        18806                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       615471                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       615471                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       615471                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       615471                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       615471                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       615471                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4523939883                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4523939883                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4523939883                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4523939883                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4523939883                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4523939883                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8397000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8397000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8397000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8397000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013989                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013989                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013989                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013989                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013989                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013989                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7350.370502                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7350.370502                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7350.370502                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  7350.370502                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7350.370502                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  7350.370502                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4841883                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43038                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4641023                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        42756                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         5990                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       109076                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       564189                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements           85682                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15604.887972                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs            847212                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs          100795                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.405298                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       229039                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       229849                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          714                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage        59807                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           55576                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15296.446244                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            851759                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           70922                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           12.009799                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6001.492372                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     7.158596                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.882758                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   688.413448                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1964.460870                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6940.479928                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.366302                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000437                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000176                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.042017                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.119901                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.423613                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.952447                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9541                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5548                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          308                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         8077                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1156                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4190                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          941                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.582336                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001465                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.338623                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        16881821                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       16881821                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16379                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7476                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst       601754                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data       101261                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        726870                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       117580                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       117580                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2286                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         2286                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          847                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          847                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28888                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        28888                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16379                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7476                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       601754                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       130149                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         755758                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16379                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7476                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       601754                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       130149                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        755758                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          463                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5968                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data        72129                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        78837                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28394                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28394                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22555                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22555                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_blocks::writebacks  8246.965221                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    13.312576                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     3.835357                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3924.928701                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2437.613409                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   669.790981                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.503355                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000813                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000234                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.239559                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.148780                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040881                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.933621                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          766                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14561                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          628                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          120                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          646                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3        10959                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2956                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.046753                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.888733                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        17259149                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       17259149                       # Number of data accesses
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+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1610                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         1610                       # number of UpgradeReq hits
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-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32933                       # number of ReadExReq misses
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-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          463                       # number of overall misses
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-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5804000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    182703951                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1611916890                       # number of ReadReq miss cycles
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-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537388904                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    537388904                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    442240538                       # number of SCUpgradeReq miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10162748                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5804000                       # number of overall miss cycles
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-system.cpu1.l2cache.Writeback_accesses::writebacks       117580                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       117580                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30680                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        30680                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23402                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61821                       # number of ReadExReq accesses(hits+misses)
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-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        16842                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.035728                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009820                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.415993                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.097848                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.925489                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.925489                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963807                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963807                       # miss rate for SCUpgradeReq accesses
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+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.946055                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.957707                       # miss rate for SCUpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532715                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532715                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.035728                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009820                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.446671                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.128837                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for overall accesses
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-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009820                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.446671                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.128837                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30613.932808                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22347.694963                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22966.216231                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.142988                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.142988                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19607.206296                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19607.206296                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       477999                       # average SCUpgradeFailReq miss latency
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-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38910.570188                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38910.570188                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30613.932808                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27539.535684                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 27664.215773                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30613.932808                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27539.535684                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 27664.215773                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs        21207                       # number of cycles access was blocked
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+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.029511                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.432141                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.140791                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20803.944316                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19991.197183                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34515.029621                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22036.558826                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24549.532101                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18771.838994                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18771.838994                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19518.839811                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19518.839811                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       404000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       404000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39491.381533                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39491.381533                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20803.944316                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19991.197183                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34515.029621                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27808.565572                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 28742.907616                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20803.944316                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19991.197183                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34515.029621                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27808.565572                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 28742.907616                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          213                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs             485                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               9                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    43.725773                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    23.666667                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        40787                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           40787                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           14                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1333                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total         1422                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1248                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1248                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           14                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1333                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1323                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         2670                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           14                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1333                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1323                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         2670                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          463                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          263                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4635                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72054                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        77415                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       109072                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       109072                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28394                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28394                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22555                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22555                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        33017                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           33017                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total          925                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1008                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1028                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1008                       # number of overall MSHR hits
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+system.cpu1.l2cache.HardPFReq_mshr_misses::total        28351                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28235                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28235                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22667                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22667                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31685                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31685                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          463                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          263                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4635                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103739                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       109100                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103739                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total       218172                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    124690282                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1106071688                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1241469220                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3463800362                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3463800362                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    417384045                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    417384045                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308383273                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308383273                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       400999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       400999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    945118400                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    945118400                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    124690282                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.demand_mshr_miss_latency::total   2186587620                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2051190088                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total   5650387982                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2182174505                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189515255                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737462500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737462500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3919637005                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3926977755                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.415560                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.096083                       # mshr miss rate for ReadReq accesses
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+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    410729057                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    410729057                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308678233                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308678233                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       341000                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7547000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189812750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737917999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737917999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7547000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3920183749                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3927730749                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024297                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.034050                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.029501                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.397966                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.109457                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.925489                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.925489                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963807                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963807                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.946055                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.946055                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.957707                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.957707                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.512528                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.512528                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.125760                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.507655                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.507655                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024297                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.034050                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.029501                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.428027                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139631                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024297                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.034050                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.029501                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.428027                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.251487                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       400999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       400999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.171625                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       341000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       341000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2447,60 +2713,61 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq       1294463                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       865156                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        11871                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11871                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       117580                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       157134                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq       1181364                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       879041                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        11863                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11863                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback       125175                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        39550                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        84893                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41888                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        87131                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        75362                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41966                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        86419                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        79541                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66364                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1215649                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       825187                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17442                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37966                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2096244                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38895824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25442442                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        31012                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        67368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          64436646                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     834109                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1797203                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.418253                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.493272                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        89279                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        71717                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1231143                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       850974                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17917                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        40354                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2140388                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     39391696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     26549567                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        31836                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          66043891                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     585425                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1574316                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.319194                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.466164                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5           1045518     58.17%     58.17% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6            751685     41.83%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5           1071804     68.08%     68.08% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6            502512     31.92%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1797203                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy     659823435                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1574316                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy     680504524                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     81245999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     81017999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    912982594                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    924938756                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    403842731                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    418581676                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      9829718                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy     10092231                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     21193613                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     22735342                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31016                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31016                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59439                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              23215                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
@@ -2526,9 +2793,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107968                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72942                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180910                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180920                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71598                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
@@ -2551,9 +2818,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484096                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             40134000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
@@ -2594,52 +2861,52 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347117122                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347085145                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84753000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36830633                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36840554                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36453                       # number of replacements
-system.iocache.tags.tagsinuse               14.560350                       # Cycle average of tags in use
+system.iocache.tags.replacements                36458                       # number of replacements
+system.iocache.tags.tagsinuse               14.558041                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36469                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         254140746000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.560350                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.910022                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.910022                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         254609644000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.558041                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909878                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909878                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328239                       # Number of tag accesses
-system.iocache.tags.data_accesses              328239                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          247                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              247                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
+system.iocache.tags.data_accesses              328284                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ide          247                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               247                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          247                       # number of overall misses
-system.iocache.overall_misses::total              247                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     30846377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     30846377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9649955112                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9649955112                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     30846377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     30846377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     30846377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     30846377                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          247                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            247                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          252                       # number of overall misses
+system.iocache.overall_misses::total              252                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31425377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31425377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9633411214                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9633411214                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31425377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31425377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31425377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31425377                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          247                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             247                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          247                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            247                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
@@ -2648,40 +2915,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124884.117409                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124884.117409                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124884.117409                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         57106                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124703.876984                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124703.876984                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124703.876984                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124703.876984                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124703.876984                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56535                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7195                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7211                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.936901                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.840105                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          247                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          247                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          252                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          247                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          247                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          247                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          247                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18001377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18001377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18001377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18001377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18001377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18001377                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          252                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18320377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18320377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7749655322                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7749655322                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18320377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18320377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18320377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18320377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -2690,524 +2957,521 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72699.908730                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72699.908730                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   153362                       # number of replacements
-system.l2c.tags.tagsinuse                64452.240621                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     520061                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   218026                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.385316                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   131156                       # number of replacements
+system.l2c.tags.tagsinuse                63989.320892                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     352673                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   195503                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.803926                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   14085.588040                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.542715                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     2.877015                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1413.412167                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2156.075780                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.498933                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000005                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      294.129683                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      883.808465                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6297.115959                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.214929                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000222                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.021567                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.032899                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.599658                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000084                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004488                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.013486                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.096086                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.983463                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        44393                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   11841.549695                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.064672                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     2.035376                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7520.794001                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2869.625937                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     4.624339                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909611                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1925.336025                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      701.530072                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1779.513002                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.180688                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000215                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000031                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.114758                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.043787                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.569600                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000071                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.029378                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.010704                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.027153                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.976400                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        31812                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        20252                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          411                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         7759                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        36223                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        32516                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          220                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         6391                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        25201                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4616                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        15266                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.677383                       # Percentage of cache occupancy per task id
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 system.l2c.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.309021                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6595512                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6595512                       # Number of data accesses
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-system.l2c.demand_accesses::cpu0.dtb.walker          331                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker          132                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           16277                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           58974                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       346313                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker           87                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker           47                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst            4647                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           21492                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        65096                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              513396                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          331                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker          132                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          16277                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          58974                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       346313                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           87                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           47                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst           4647                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          21492                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        65096                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             513396                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.229342                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.181994                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.103077                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.105852                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.322616                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.404365                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.431183                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800224                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.485814                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.800213                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.878261                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.846618                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.677064                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.854670                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.752427                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.399777                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.322616                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.417843                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.229342                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.278072                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.103077                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.399777                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.417843                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94187.782748                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 89373.005202                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76225                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       318000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99678.496868                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 88397.069465                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 114447.983043                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   789.346939                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1132.645455                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   873.056868                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1859.159363                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1031.722772                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1348.801527                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92113.134598                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78138.416505                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85377.542817                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu0.data 90667.795292                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.itb.walker       318000                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 79788.493133                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::total 112420.821275                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 90667.795292                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        76225                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 79788.493133                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 112420.821275                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               117                       # number of cycles access was blocked
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+system.l2c.UpgradeReq_miss_latency::cpu1.data      2228405                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      7321692                       # number of UpgradeReq miss cycles
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+system.l2c.ReadReq_accesses::total             328617                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       227099                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           227099                       # number of Writeback accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data         3627                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.125628                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::total          0.523412                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.748237                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.814447                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.764130                       # miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_miss_rate::total     0.847623                       # miss rate for SCUpgradeReq accesses
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+system.l2c.demand_miss_rate::cpu1.inst       0.164849                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.452973                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.686983                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.541568                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.125628                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.043478                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.364358                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.286919                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.737915                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.062500                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.164849                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.452973                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.686983                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.541568                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        94230                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79416.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75156.051962                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 84614.813253                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        80500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78299.531240                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 85646.247320                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 106330.746468                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   592.794111                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   754.368653                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   634.132340                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1403.824143                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   660.036378                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total   921.609539                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87901.688210                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75627.014093                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 82672.874801                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        94230                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79416.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 75156.051962                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 86424.640990                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        80500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 78299.531240                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 76988.912365                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 103922.966150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        94230                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79416.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 75156.051962                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 86424.640990                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        80500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 78299.531240                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 76988.912365                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 103922.966150                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     19.500000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              113392                       # number of writebacks
-system.l2c.writebacks::total                   113392                       # number of writebacks
+system.l2c.writebacks::writebacks               99563                       # number of writebacks
+system.l2c.writebacks::total                    99563                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                24                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 9                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 24                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                24                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            6                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         3733                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         8649                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           25                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::cpu0.inst        19493                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         9129                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          477                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1382                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        20983                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          199536                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         8869                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2860                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11729                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          753                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1212                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1965                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data         7749                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         7210                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         14959                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           34                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         3733                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        16398                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2987                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1306                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        10708                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          171993                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         8592                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2954                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11546                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          671                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1237                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1908                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11187                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8302                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         19489                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           25                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128336                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          477                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         8592                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        20983                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           214495                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           34                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu0.inst         3733                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        16398                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of overall MSHR misses
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+system.l2c.demand_mshr_misses::cpu1.inst         2987                       # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        10708                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           191482                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total          214495                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       375000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    305475493                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    665719995                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     41657500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    104989750                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::total  20385228496                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     90096780                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28958843                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    119055623                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7837704                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     12202201                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     20039905                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    617896318                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    472413013                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1090309331                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       375000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    305475493                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   1283616313                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  16992433103                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst     41657500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    577402763                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2271307905                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  21475537827                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       375000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    305475493                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   1283616313                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16992433103                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       305500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     41657500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    577402763                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2271307905                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  21475537827                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3686294748                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919867500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   5770594748                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2713847001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1535209500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4249056501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6400141749                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3455077000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10019651249                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.181973                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.105852                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.404316                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.431183                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800224                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.485814                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.800213                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.878261                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.846618                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.677064                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.854670                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.752427                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.417796                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.417796                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76970.747485                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75969.428365                       # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10125.469580                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10150.534828                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10408.637450                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.822607                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10198.424936                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65521.915811                       # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 100121.391300                       # average overall mshr miss latency
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.364321                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.115842                       # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.814447                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.764130                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62600.073514                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72210.099135                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        68000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65789.670907                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73214.777182                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 94027.774700                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10087.586010                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10066.837508                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10082.277585                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10193.962742                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10049.089733                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10100.038260                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75462.216144                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63008.133823                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70156.977731                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        81790                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62600.073514                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74000.876501                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        68000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65789.670907                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64395.506453                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 91598.209717                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        81790                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62600.073514                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74000.876501                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        68000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65789.670907                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64395.506453                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 91598.209717                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -3222,57 +3486,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              237783                       # Transaction distribution
-system.membus.trans_dist::ReadResp             237783                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30976                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30976                       # Transaction distribution
-system.membus.trans_dist::Writeback            149598                       # Transaction distribution
+system.membus.trans_dist::ReadReq              210212                       # Transaction distribution
+system.membus.trans_dist::ReadResp             210211                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30942                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30942                       # Transaction distribution
+system.membus.trans_dist::Writeback            135769                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            79558                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40675                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13780                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             31194                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14873                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            76140                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40614                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13546                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39344                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19397                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107968                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       708374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       830114                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 939030                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13598                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       648466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       770072                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 878993                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21024476                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     21215108                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27196                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18669148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18859512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4636480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4636480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                25851588                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           123388                       # Total snoops (count)
-system.membus.snoop_fanout::samples            537032                       # Request fanout histogram
+system.membus.pkt_size::total                23495992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123727                       # Total snoops (count)
+system.membus.snoop_fanout::samples            500337                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  537032    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  500337    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              537032                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81237991                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              500337                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81279500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               26500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               26000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11614997                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11516000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1967612498                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1822464250                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2113693587                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1904793274                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38580367                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38546446                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -3305,48 +3569,48 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq             659684                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            659669                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30976                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30976                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           252625                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             489006                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            488990                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30942                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30942                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           227099                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           91886                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41031                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         132917                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            40129                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           40129                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1298615                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       426559                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1725174                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     40738026                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8562330                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               49300356                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          291348                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1083611                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.033657                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.180345                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeReq           79612                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         40957                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         120569                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           20                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50358                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50358                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1016462                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       341372                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1357834                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31696041                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5742799                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               37438840                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          287500                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           885309                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.041201                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.198756                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                1047140     96.63%     96.63% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  36471      3.37%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 848833     95.88%     95.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  36476      4.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1083611                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1586551162                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             885309                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1431615961                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1044000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1066500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2272414912                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1714942226                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         846278221                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         674969400                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1853                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1858                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2766                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2745                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index b41e9656d..8914a4f8a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.827042                       # Number of seconds simulated
-sim_ticks                                2827042159500                       # Number of ticks simulated
-final_tick                               2827042159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827025                       # Number of seconds simulated
+sim_ticks                                2827025397500                       # Number of ticks simulated
+final_tick                               2827025397500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100972                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122474                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2522254422                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 564960                       # Number of bytes of host memory used
-host_seconds                                  1120.84                       # Real time elapsed on the host
-sim_insts                                   113173742                       # Number of instructions simulated
-sim_ops                                     137273263                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  96738                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117339                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2415768223                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 619580                       # Number of bytes of host memory used
+host_seconds                                  1170.24                       # Real time elapsed on the host
+sim_insts                                   113206948                       # Number of instructions simulated
+sim_ops                                     137314363                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1324048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9496932                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1324240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9499748                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10823604                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1324048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8116352                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10826676                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1324240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1324240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8118016                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8133876                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8135540                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           20                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22933                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             148909                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22936                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             148953                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                171883                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126818                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                171931                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126844                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               131199                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            430                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               131225                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            453                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               468351                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3359317                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               468422                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3360333                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3828597                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          468351                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             468351                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2870970                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3829706                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          468422                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             468422                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2871575                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6199                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2877168                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2870970                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2877774                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2871575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           453                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              468351                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3365516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              468422                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3366532                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6705765                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        171884                       # Number of read requests accepted
-system.physmem.writeReqs                       167423                       # Number of write requests accepted
-system.physmem.readBursts                      171884                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     167423                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10992576                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8000                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10315392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10823668                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10452212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      125                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    6228                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4543                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10965                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10116                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11197                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11389                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13120                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10535                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11120                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11540                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10348                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11053                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10478                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9244                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10124                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10758                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10029                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9743                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10407                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9909                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10642                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               10446                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9703                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               10218                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               10399                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10626                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               10202                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10761                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9802                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9030                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9755                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              10443                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9720                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9115                       # Per bank write bursts
+system.physmem.bw_total::total                6707480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        171932                       # Number of read requests accepted
+system.physmem.writeReqs                       167449                       # Number of write requests accepted
+system.physmem.readBursts                      171932                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     167449                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10995584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10340800                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10826740                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10453876                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5856                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4542                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11320                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10283                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11137                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11363                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13028                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10237                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10954                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11381                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10407                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11232                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10729                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9386                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9853                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10909                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9951                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9636                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10810                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10132                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10502                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10558                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9654                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9978                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10358                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10535                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               10309                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10935                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              10009                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9154                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9556                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10555                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9521                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9009                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2827041948500                       # Total gap between requests
+system.physmem.totGap                    2827025186500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2993                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  168336                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  168384                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 163042                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151765                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15965                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3221                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 163068                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151696                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,137 +159,134 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7495                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     8655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    10433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    11221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7391                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7956                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7361                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64399                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      330.873212                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     190.977516                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     347.816153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23539     36.55%     36.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14785     22.96%     59.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6319      9.81%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3687      5.73%     75.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2636      4.09%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1562      2.43%     81.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1140      1.77%     83.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1107      1.72%     85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9624     14.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64399                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6814                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.206340                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      540.339482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6812     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        64517                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      330.708495                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     190.901316                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.828879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23555     36.51%     36.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14820     22.97%     59.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6443      9.99%     69.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3645      5.65%     75.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2568      3.98%     79.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1574      2.44%     81.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1131      1.75%     83.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1187      1.84%     85.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9594     14.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64517                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6820                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.190762                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      540.107379                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6818     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6814                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6814                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.653948                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.805353                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.459775                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5702     83.68%     83.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              39      0.57%     84.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              26      0.38%     84.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             231      3.39%     88.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             131      1.92%     89.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              61      0.90%     90.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              35      0.51%     91.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              27      0.40%     91.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             123      1.81%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              13      0.19%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              19      0.28%     94.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              11      0.16%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              31      0.45%     94.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              13      0.19%     94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              13      0.19%     95.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.38%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              61      0.90%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              10      0.15%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               9      0.13%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              11      0.16%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              89      1.31%     98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             7      0.10%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            18      0.26%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             4      0.06%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             5      0.07%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.06%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            26      0.38%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             4      0.06%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             4      0.06%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.07%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            11      0.16%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151            11      0.16%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.04%     99.60% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6820                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.691349                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.848646                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.179127                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5682     83.31%     83.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              64      0.94%     84.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              25      0.37%     84.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             208      3.05%     87.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             139      2.04%     89.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              55      0.81%     90.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              46      0.67%     91.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              37      0.54%     91.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             121      1.77%     93.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              14      0.21%     93.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              20      0.29%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              15      0.22%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              20      0.29%     94.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              19      0.28%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              10      0.15%     94.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              21      0.31%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              67      0.98%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              14      0.21%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               7      0.10%     96.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              14      0.21%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              85      1.25%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             5      0.07%     98.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            15      0.22%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            16      0.23%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             5      0.07%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.37%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             8      0.12%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            12      0.18%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.07%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.60% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::156-159             2      0.03%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.03%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             3      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             3      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             9      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             4      0.06%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.03%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::232-235             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6814                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2084525750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5305007000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    858795000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12136.34                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            6820                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2011805750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5233168250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    859030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11709.75                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30886.34                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30459.75                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.89                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.65                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.66                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.83                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -297,36 +294,41 @@ system.physmem.busUtil                           0.06                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.50                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     141721                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    126816                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8331811.45                       # Average gap between requests
-system.physmem.pageHitRate                      80.65                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2694668588500                       # Time in different power states
-system.physmem.memoryStateTime::REF       94401060000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       37972497000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 254499840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 232356600                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 138864000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 126781875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                701859600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                637852800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               533628000                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               510805440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184648473360                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184648473360                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           80377758270                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           79142156730                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1625717004000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1626800865000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1892372087070                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1892099291805                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.382923                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.286428                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        27.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     141825                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    127038                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.55                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8329945.36                       # Average gap between requests
+system.physmem.pageHitRate                      80.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  254462040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  138843375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 699683400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                534774960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184647456240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80304363360                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625772042000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892351625375                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.379373                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704495478000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94400540000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28128105750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  233286480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  127289250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 640395600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                512231040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184647456240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79168609575                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626768325500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892097593685                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.289511                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2706163008250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94400540000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26461835250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
@@ -345,16 +347,24 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46933448                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24039449                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1232882                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29542848                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21360620                       # Number of BTB hits
+system.cpu.branchPred.lookups                46965884                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24051171                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1232760                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29570934                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21375571                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.303862                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11754095                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33720                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.285749                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11765533                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33715                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -376,27 +386,89 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                     69937                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                69937                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29497                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22737                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        17703                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52234                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   334.025730                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  1986.195905                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50803     97.26%     97.26% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          591      1.13%     98.39% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          521      1.00%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383           84      0.16%     99.55% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479          102      0.20%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          114      0.22%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52234                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        16206                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9699.278169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7212.227669                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  7791.284796                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        16044     99.00%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          159      0.98%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-131071            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        16206                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 116899920224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.624364                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489854                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  116858057224     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      29153000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       6015500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       4000000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9        926000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       658000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13       874000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       231500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17         5000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 116899920224                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6318     82.14%     82.14% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1374     17.86%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7692                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        69937                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        69937                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7692                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7692                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        77629                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25465003                       # DTB read hits
-system.cpu.dtb.read_misses                      60438                       # DTB read misses
-system.cpu.dtb.write_hits                    19916425                       # DTB write hits
-system.cpu.dtb.write_misses                      9382                       # DTB write misses
+system.cpu.dtb.read_hits                     25472400                       # DTB read hits
+system.cpu.dtb.read_misses                      60528                       # DTB read misses
+system.cpu.dtb.write_hits                    19920178                       # DTB write hits
+system.cpu.dtb.write_misses                      9409                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4324                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       344                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2309                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4326                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       345                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2281                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1303                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25525441                       # DTB read accesses
-system.cpu.dtb.write_accesses                19925807                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1305                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25532928                       # DTB read accesses
+system.cpu.dtb.write_accesses                19929587                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45381428                       # DTB hits
-system.cpu.dtb.misses                           69820                       # DTB misses
-system.cpu.dtb.accesses                      45451248                       # DTB accesses
+system.cpu.dtb.hits                          45392578                       # DTB hits
+system.cpu.dtb.misses                           69937                       # DTB misses
+system.cpu.dtb.accesses                      45462515                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -418,8 +490,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     66294026                       # ITB inst hits
-system.cpu.itb.inst_misses                      11939                       # ITB inst misses
+system.cpu.itb.walker.walks                     11957                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11957                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         4035                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7756                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          166                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11791                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   476.931558                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2426.619854                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        11573     98.15%     98.15% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          164      1.39%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575           47      0.40%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767            2      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11791                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3494                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10252.862049                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7229.260491                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7922.738250                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1610     46.08%     46.08% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          989     28.31%     74.38% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          844     24.16%     98.54% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           31      0.89%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959           18      0.52%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::73728-81919            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3494                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  22130705712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.982067                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.132922                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       397376500      1.80%      1.80% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     21732921212     98.20%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          337000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           44500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           26500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  22130705712                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3007     90.35%     90.35% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           321      9.65%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11957                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15285                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66242388                       # ITB inst hits
+system.cpu.itb.inst_misses                      11957                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -435,91 +554,91 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                      2177                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66305965                       # ITB inst accesses
-system.cpu.itb.hits                          66294026                       # DTB hits
-system.cpu.itb.misses                           11939                       # DTB misses
-system.cpu.itb.accesses                      66305965                       # DTB accesses
-system.cpu.numCycles                        260580731                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66254345                       # ITB inst accesses
+system.cpu.itb.hits                          66242388                       # DTB hits
+system.cpu.itb.misses                           11957                       # DTB misses
+system.cpu.itb.accesses                      66254345                       # DTB accesses
+system.cpu.numCycles                        260505842                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104873538                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184739295                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46933448                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33114715                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     145635789                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6158762                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     168952                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8750                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        338958                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       503648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.icacheStallCycles          104910536                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184564437                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46965884                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33141104                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     145523967                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6162316                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     169075                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        338609                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       504254                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles          106                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66294321                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1128854                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4994                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          254609122                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.884999                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.237560                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  66242687                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1039458                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5021                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          254536314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.884658                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.237297                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                155317216     61.00%     61.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29235163     11.48%     72.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14076452      5.53%     78.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55980291     21.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                155286067     61.01%     61.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29244712     11.49%     72.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14083759      5.53%     78.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55921776     21.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            254609122                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.180111                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.708952                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 78085586                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             105431733                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64660886                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3829260                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2601657                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3422216                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                485978                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157447803                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3691485                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2601657                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83925210                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10033565                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       74541150                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62655394                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              20852146                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146807646                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                950357                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                437123                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  62766                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16447                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               18089237                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150492315                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678770164                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164434086                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            254536314                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.180287                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.708485                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78110854                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             105310937                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64681837                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3829276                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2603410                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3422230                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                485999                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157498066                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3692054                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2603410                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83952319                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10018441                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       74493030                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62674544                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              20794570                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146849554                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                949739                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                436543                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62719                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16684                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               18031839                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150536032                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678970726                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164476932                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10967                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141835122                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8657190                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2845976                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2649716                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13845319                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26411369                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21300781                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1686386                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2189128                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143541895                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2120957                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143337283                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            269192                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6251828                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14653372                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125306                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     254609122                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.562970                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.882443                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             141878160                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8657869                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2847901                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2651576                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13851577                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26418729                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21304216                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1685996                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2099557                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143583180                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2120928                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143378875                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            268933                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6250249                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14652310                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125244                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     254536314                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.563294                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.882192                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           166344309     65.33%     65.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45117660     17.72%     83.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32035421     12.58%     95.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10298180      4.04%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              813519      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           166156595     65.28%     65.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45308451     17.80%     83.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31957183     12.56%     95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10300315      4.05%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              813737      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -527,9 +646,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       254609122                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       254536314                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7370311     32.63%     32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7371563     32.63%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.63% # attempts to use FU when none available
@@ -558,13 +677,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5632420     24.93%     57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9586874     42.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5632608     24.93%     57.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9585974     42.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              96009315     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113982      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              96039761     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113980      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -592,96 +711,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc           8594      0.01%     67.07% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26194290     18.27%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21008765     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26201849     18.27%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21012354     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143337283                       # Type of FU issued
-system.cpu.iq.rate                           0.550069                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22589637                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157598                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          564106761                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         151919680                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140223084                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35756                       # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total              143378875                       # Type of FU issued
+system.cpu.iq.rate                           0.550386                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22590177                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157556                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          564117476                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         151959359                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140262857                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35698                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes              13217                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11431                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165901147                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23436                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           324147                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              165943337                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23378                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323934                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1490308                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1489912                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses          533                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18251                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       701176                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18252                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       700651                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88081                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6304                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87937                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6369                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2601657                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  950737                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                291154                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145863821                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2603410                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  946501                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                282988                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145905073                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26411369                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21300781                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096076                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17895                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                256263                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18251                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317548                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471732                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789280                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142394540                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25793108                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            873030                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26418729                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21304216                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096059                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17893                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                248042                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18252                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317390                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471834                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789224                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142436087                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25800504                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            872964                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200969                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46672402                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26533167                       # Number of branches executed
-system.cpu.iew.exec_stores                   20879294                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.546451                       # Inst execution rate
-system.cpu.iew.wb_sent                      142007306                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140234515                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63283849                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95860591                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200965                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46683536                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26544582                       # Number of branches executed
+system.cpu.iew.exec_stores                   20883032                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.546767                       # Inst execution rate
+system.cpu.iew.wb_sent                      142049013                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140274288                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63301991                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95888204                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.538161                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.538469                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.660165                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7591533                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995651                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755158                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    251674404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.546055                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.146686                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7591203                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995684                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755012                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    251600015                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.546380                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.145616                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    178222235     70.81%     70.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43294364     17.20%     88.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15476639      6.15%     94.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4357303      1.73%     95.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6369018      2.53%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1679088      0.67%     99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       777340      0.31%     99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       414271      0.16%     99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1084146      0.43%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    178032532     70.76%     70.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43398742     17.25%     88.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15483585      6.15%     94.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4358404      1.73%     95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6462138      2.57%     98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1589340      0.63%     99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       777430      0.31%     99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       414440      0.16%     99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1083404      0.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    251674404                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113328647                       # Number of instructions committed
-system.cpu.commit.committedOps              137428168                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    251600015                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113361853                       # Number of instructions committed
+system.cpu.commit.committedOps              137469268                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45520666                       # Number of memory references committed
-system.cpu.commit.loads                      24921061                       # Number of loads committed
-system.cpu.commit.membars                      814701                       # Number of memory barriers committed
-system.cpu.commit.branches                   26049415                       # Number of branches committed
+system.cpu.commit.refs                       45532382                       # Number of memory references committed
+system.cpu.commit.loads                      24928817                       # Number of loads committed
+system.cpu.commit.membars                      814713                       # Number of memory barriers committed
+system.cpu.commit.branches                   26060941                       # Number of branches committed
 system.cpu.commit.fp_insts                      11428                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120247607                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4892692                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120284813                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4896517                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91785919     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91815303     66.79%     66.79% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult          112990      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
@@ -710,210 +829,210 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8593      0.01%     66.88% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24921061     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20599605     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24928817     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20603565     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137428168                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1084146                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         137469268                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1083404                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    373381031                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292971684                       # The number of ROB writes
-system.cpu.timesIdled                          892930                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5971609                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5393503589                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113173742                       # Number of Instructions Simulated
-system.cpu.committedOps                     137273263                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.302484                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.302484                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.434314                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.434314                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155831391                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88636024                       # number of integer regfile writes
+system.cpu.rob.rob_reads                    373323554                       # The number of ROB reads
+system.cpu.rob.rob_writes                   293054802                       # The number of ROB writes
+system.cpu.timesIdled                          892910                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5969528                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5393544954                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113206948                       # Number of Instructions Simulated
+system.cpu.committedOps                     137314363                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.301147                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.301147                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.434566                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.434566                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155872747                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88664446                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      9607                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 503020695                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53185327                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               444130548                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521619                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837995                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.958491                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40159583                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838507                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.894154                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 503168366                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53197006                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               443775049                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521649                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837844                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.958421                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40169385                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838356                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.914472                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         244924250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.958491                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.958421                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179379502                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179379502                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23322864                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23322864                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15584894                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15584894                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346636                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346636                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       442009                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       442009                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460310                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460310                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38907758                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38907758                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39254394                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39254394                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       700618                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        700618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3574058                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3574058                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177109                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177109                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        26740                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        26740                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4274676                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4274676                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4451785                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4451785                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9939142148                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9939142148                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 135148977049                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    356483749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    356483749                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       189500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       189500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145088119197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145088119197                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145088119197                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145088119197                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24023482                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24023482                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19158952                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19158952                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523745                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523745                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468749                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468749                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460315                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460315                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43182434                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43182434                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43706179                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43706179                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029164                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029164                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186548                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.186548                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338159                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.338159                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.098991                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.098991                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.101857                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.101857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        37900                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        37900                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33941.313727                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32590.998711                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       505021                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179425849                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179425849                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23330547                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23330547                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15587007                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15587007                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       346674                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        346674                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441974                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441974                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460321                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460321                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38917554                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38917554                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39264228                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39264228                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       700623                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        700623                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3575875                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3575875                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177079                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177079                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26763                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26763                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      4276498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4276498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4453577                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4453577                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9909110648                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9909110648                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 134775393563                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    355748499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    355748499                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       176500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       176500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144684504211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144684504211                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144684504211                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144684504211                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24031170                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24031170                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19162882                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19162882                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523753                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523753                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468737                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468737                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460325                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460325                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43194052                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43194052                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43717805                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43717805                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029155                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029155                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.186604                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.186604                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.338096                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.338096                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057096                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057096                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099007                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099007                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.101871                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.101871                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        44125                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        44125                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33832.473255                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32487.257818                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       491325                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6926                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6982                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    72.916691                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    70.370238                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695574                       # number of writebacks
-system.cpu.dcache.writebacks::total            695574                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286297                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       286297                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3274736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3274736                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18417                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18417                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3561033                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3561033                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3561033                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3561033                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414321                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       414321                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299322                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299322                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119334                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119334                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8323                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8323                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713643                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713643                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832977                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832977                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5358688665                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   5358688665                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11888843709                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11888843709                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1476460251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1476460251                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    110246000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    110246000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       179500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       179500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17247532374                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17247532374                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18723992625                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18723992625                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792718250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792718250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440457453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440457453                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233175703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233175703                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017247                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017247                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015623                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015623                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227848                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227848                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017756                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017756                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016526                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019059                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019059                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        35900                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        35900                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       695426                       # number of writebacks
+system.cpu.dcache.writebacks::total            695426                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       286545                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       286545                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3276416                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3276416                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18452                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18452                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total      3562961                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3562961                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3562961                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414078                       # number of ReadReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total       119308                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8311                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8311                       # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5351526415                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5351526415                       # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11825722463                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1475435001                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1475435001                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    109426500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    109426500                       # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       168500                       # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total  17177248878                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18652683879                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18652683879                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5792686500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5792686500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4440468453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4440468453                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10233154953                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  10233154953                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017231                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017231                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015627                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015627                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227794                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227794                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017731                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017731                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016519                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016519                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019050                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019050                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        42125                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        42125                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -921,265 +1040,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1894210                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.373832                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64309690                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1894722                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.941491                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1894041                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.373863                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64258114                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1894553                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.917296                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       13186180250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.373832                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.373863                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          208                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68186062                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68186062                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64309690                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64309690                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64309690                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64309690                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64309690                       # number of overall hits
-system.cpu.icache.overall_hits::total        64309690                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981630                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981630                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981630                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981630                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981630                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981630                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  26770075875                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  26770075875                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  26770075875                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  26770075875                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  26770075875                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  26770075875                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66291320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66291320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66291320                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66291320                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66291320                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66291320                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029893                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029893                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029893                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029893                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029893                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029893                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13509.119197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13509.119197                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1592                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68134254                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68134254                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64258114                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64258114                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        64258114                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1981572                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1981572                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total        1981572                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1981572                       # number of overall misses
+system.cpu.icache.overall_misses::total       1981572                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26765848354                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26765848354                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26765848354                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst  26765848354                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26765848354                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66239686                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66239686                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66239686                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66239686                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66239686                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66239686                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029915                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029915                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029915                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029915                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029915                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029915                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13507.381187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13507.381187                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2017                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               104                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               103                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    15.307692                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    19.582524                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        86886                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        86886                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        86886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        86886                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        86886                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        86886                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894744                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1894744                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1894744                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1894744                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1894744                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1894744                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22166113097                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  22166113097                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22166113097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  22166113097                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22166113097                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  22166113097                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        87002                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        87002                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        87002                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst        87002                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        87002                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1894570                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst      1894570                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22163460869                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    202549500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    202549500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    202549500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028582                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028582                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028582                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028582                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.737717                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.737717                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028602                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028602                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            98615                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65077.693225                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3021592                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           163828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            18.443685                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            98730                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65075.133005                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3019277                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           163872                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            18.424606                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.218373                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798544                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5192.626837                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756260                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000156                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.158546                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.798547                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5229.614939                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.757349                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000170                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000043                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157315                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65200                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65129                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2969                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7003                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55048                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2965                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6995                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54988                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994873                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         28442992                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        28442992                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53902                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        2468583                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       695574                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       695574                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           36                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           36                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.overall_hits::total        2628333                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           19                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.993790                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         28438035                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        28438035                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53702                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        2467972                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       695426                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       695426                       # number of Writeback hits
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+system.cpu.l2cache.UpgradeReq_hits::total           32                       # number of UpgradeReq hits
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+system.cpu.l2cache.overall_hits::cpu.inst      1874573                       # number of overall hits
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+system.cpu.l2cache.overall_hits::total        2627799                       # number of overall hits
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-system.cpu.l2cache.UpgradeReq_misses::total         2734                       # number of UpgradeReq misses
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+system.cpu.l2cache.ReadReq_misses::total        33598                       # number of ReadReq misses
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::total       136934                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       536250                       # number of ReadReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72250                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1188,8 +1307,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        90628                       # number of writebacks
-system.cpu.l2cache.writebacks::total            90628                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        90654                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          112                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
@@ -1199,98 +1318,98 @@ system.cpu.l2cache.demand_mshr_hits::total          137                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          137                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           19                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       451250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1251787750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    914145000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2167621250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27559234                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27559234                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1250973750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    908888250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2162010000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27698243                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27698243                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8214311559                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8214311559                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8149358299                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8149358299                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1696750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       451250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1251787750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9128456559                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10381932809                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1237250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1250973750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9058246549                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10311368299                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1696750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       451250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1251787750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9128456559                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10381932809                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387474750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545351750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107339500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107339500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157877000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494814250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652691250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024922                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013377                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987004                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987004                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461548                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461548                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060884                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000352                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000598                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010526                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179407                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060884                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1250973750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9058246549                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10311368299                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    157876500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5387443500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545320000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107345000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107345000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    157876500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9494788500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652665000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000372                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000597                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010528                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.024905                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013376                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988468                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988468                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461519                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461519                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000372                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000597                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010528                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.179479                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060908                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000372                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000597                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010528                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.179479                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060908                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1300,54 +1419,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2565344                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2565278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2565017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2564966                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27608                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27608                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       695574                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       695426                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296684                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296684                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795456                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495832                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31236                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128794                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6451318                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121309456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98375777                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       215684                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219947773                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       65392                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3562462                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.010230                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.100625                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2779                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296811                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296811                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3795114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2495409                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31281                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128693                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6450497                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    121298704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98357729                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        46936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          219918257                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       65703                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3562118                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.010231                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.100630                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5            3526018     98.98%     98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5            3525674     98.98%     98.98% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::6              36444      1.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3562462                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2503396529                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3562118                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2503082512                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       256500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2849706150                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2849465378                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1334755109                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1334578357                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19527240                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19552240                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74897454                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74992959                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
@@ -1444,23 +1563,23 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347066130                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347066125                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36776516                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36776514                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                1.000725                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.000670                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         251942535000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.000725                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062545                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062545                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         251936772000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000670                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062542                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062542                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1474,14 +1593,14 @@ system.iocache.demand_misses::realview.ide          220                       #
 system.iocache.demand_misses::total               220                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          220                       # number of overall misses
 system.iocache.overall_misses::total              220                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     26411377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     26411377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9622478237                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9622478237                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     26411377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     26411377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     26411377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     26411377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     26427377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     26427377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9617153234                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9617153234                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     26427377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     26427377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     26427377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     26427377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1498,19 +1617,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120051.713636                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 120051.713636                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 120051.713636                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 120051.713636                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         56749                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 120124.440909                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 120124.440909                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 120124.440909                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 120124.440909                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 120124.440909                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56312                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7275                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7225                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.800550                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.794048                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1524,14 +1643,14 @@ system.iocache.demand_mshr_misses::realview.ide          220
 system.iocache.demand_mshr_misses::total          220                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          220                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          220                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     14970377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     14970377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738798269                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     14970377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     14970377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     14970377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     14970377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     14986377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     14986377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7733477262                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7733477262                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     14986377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     14986377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     14986377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     14986377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1540,66 +1659,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68047.168182                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68119.895455                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68119.895455                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               67832                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67831                       # Transaction distribution
+system.membus.trans_dist::ReadReq               67820                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67819                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27608                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27608                       # Transaction distribution
-system.membus.trans_dist::Writeback            126818                       # Transaction distribution
+system.membus.trans_dist::Writeback            126844                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4543                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4542                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4545                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135125                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135125                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4544                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135185                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135185                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452492                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       452612                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       560248                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108873                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108873                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 669001                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 669121                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16640360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16803825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16645096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16808561                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21439281                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21444017                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              484                       # Total snoops (count)
-system.membus.snoop_fanout::samples            336405                       # Request fanout histogram
+system.membus.snoop_fanout::samples            336478                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  336405    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  336478    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              336405                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            94190000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              336478                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            94194499                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1701500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1683660499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1683962999                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1677935457                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1678430208                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38220484                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38218486                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 053f94faa..0523405d3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,153 +1,153 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.818075                       # Number of seconds simulated
-sim_ticks                                2818074786500                       # Number of ticks simulated
-final_tick                               2818074786500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.818071                       # Number of seconds simulated
+sim_ticks                                2818071194500                       # Number of ticks simulated
+final_tick                               2818071194500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 252135                       # Simulator instruction rate (inst/s)
-host_op_rate                                   306151                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5631568448                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 564964                       # Number of bytes of host memory used
-host_seconds                                   500.41                       # Real time elapsed on the host
-sim_insts                                   126169808                       # Number of instructions simulated
-sim_ops                                     153199842                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 294940                       # Simulator instruction rate (inst/s)
+host_op_rate                                   358127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6587540433                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 622484                       # Number of bytes of host memory used
+host_seconds                                   427.79                       # Real time elapsed on the host
+sim_insts                                   126171688                       # Number of instructions simulated
+sim_ops                                     153202470                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           666212                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4384416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           666276                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4385696                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           128384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1037892                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           127360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1038980                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.dtb.walker         6016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           504320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          4231744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           505600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          4227776                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10960328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       666212                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       128384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       504320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1298916                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8261760                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10959048                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       666276                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       127360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       505600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1299236                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8262336                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8279284                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8279860                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             18863                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             69025                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             18864                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             69045                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2006                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16218                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1990                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16235                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.dtb.walker           94                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              7880                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             66121                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              7900                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             66059                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180228                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          129090                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                180208                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          129099                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133471                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               133480                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            91                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              236407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1555820                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              236430                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1556276                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               45557                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              368298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               45194                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              368685                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu2.dtb.walker          2135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              178959                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1501644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              179413                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1500237                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3889296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         236407                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          45557                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         178959                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             460923                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2931704                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3888847                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         236430                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          45194                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         179413                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             461037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2931912                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6216                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2937922                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2931704                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2938130                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2931912                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           91                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             236407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1562035                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             236430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1562491                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              45557                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             368301                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              45194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             368688                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu2.dtb.walker         2135                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             178959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1501644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             179413                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1500237                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6827218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         92321                       # Number of read requests accepted
-system.physmem.writeReqs                        90302                       # Number of write requests accepted
-system.physmem.readBursts                       92321                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      90302                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5904000                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      4544                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5704128                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5908484                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5779208                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       71                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    1152                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2483                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6041                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5798                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5558                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6021                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5562                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5457                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6123                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6801                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6403                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6349                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5693                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5092                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5281                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5450                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5307                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5314                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5390                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4962                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5472                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5886                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5376                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5734                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5792                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6324                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6132                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6057                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5626                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4872                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5573                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5712                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5197                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5022                       # Per bank write bursts
+system.physmem.bw_total::total                6826977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         92280                       # Number of read requests accepted
+system.physmem.writeReqs                        90311                       # Number of write requests accepted
+system.physmem.readBursts                       92280                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      90311                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5901184                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      4736                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5694528                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5905860                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5779784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       74                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1313                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           2491                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6033                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5793                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5545                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6032                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5564                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5452                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6124                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6804                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6414                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6339                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5684                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5101                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5267                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               5451                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               5288                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5315                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5413                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4989                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5365                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5927                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5380                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5714                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5766                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6373                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6011                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5951                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5678                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4910                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5493                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5839                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5189                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4979                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2816508644000                       # Total gap between requests
+system.physmem.totGap                    2816505052000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       1                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   92320                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   92279                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  90300                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     60706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28069                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       505                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  90309                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     60465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     28317                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2940                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       476                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -178,149 +178,149 @@ system.physmem.rdQLenPdf::31                        0                       # Wh
 system.physmem.wrQLenPdf::0                        57                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        54                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        52                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       49                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       48                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5702                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2426                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     3952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        33954                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      341.872416                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     193.139988                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     360.706061                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12607     37.13%     37.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         7646     22.52%     59.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         2942      8.66%     68.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1742      5.13%     73.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1359      4.00%     77.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          780      2.30%     79.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          533      1.57%     81.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          565      1.66%     82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5780     17.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          33954                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3432                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.875583                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      525.946384                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           3431     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        33947                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.579050                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     192.896082                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     361.051588                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12589     37.08%     37.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7648     22.53%     59.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3047      8.98%     68.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1722      5.07%     73.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1227      3.61%     77.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          803      2.37%     79.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          549      1.62%     81.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          558      1.64%     82.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5804     17.10%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          33947                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3440                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.800581                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      525.347088                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3439     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3432                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3432                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.969406                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.900383                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       25.459060                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 4      0.12%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.17% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            3440                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3440                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.865407                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.895854                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       25.306431                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 5      0.15%      0.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 1      0.03%      0.17% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::8-11                3      0.09%      0.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               2      0.06%      0.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            2696     78.55%     78.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              29      0.84%     79.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.87%     80.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             138      4.02%     84.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              83      2.42%     87.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              30      0.87%     87.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              20      0.58%     88.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              23      0.67%     89.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              73      2.13%     91.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.20%     91.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.15%     91.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.23%     91.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              20      0.58%     92.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               8      0.23%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.23%     92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              21      0.61%     93.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              41      1.19%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               8      0.23%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.09%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               9      0.26%     95.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              65      1.89%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.12%     97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             7      0.20%     97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             5      0.15%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             7      0.20%     97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.09%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             8      0.23%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.09%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               4      0.12%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            2693     78.28%     78.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              34      0.99%     79.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              21      0.61%     80.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             172      5.00%     85.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              62      1.80%     87.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              30      0.87%     87.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              17      0.49%     88.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              16      0.47%     88.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              84      2.44%     91.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.32%     91.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              14      0.41%     92.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.29%     92.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              20      0.58%     92.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.17%     93.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.17%     93.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.73%     94.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              46      1.34%     95.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.12%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               4      0.12%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               9      0.26%     95.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              47      1.37%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.09%     97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             6      0.17%     97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.06%     97.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            16      0.47%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.03%     98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             7      0.20%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.06%     98.28% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131            22      0.64%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             7      0.20%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.06%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.06%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.06%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             3      0.09%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.03%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.09%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             5      0.15%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.09%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.06%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.17%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             3      0.09%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.09%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.03%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.09%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.12%     99.65% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::168-171             1      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.09%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.06%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.03%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             3      0.09%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.03%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::224-227             1      0.03%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::228-231             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3432                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1184332750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2914020250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    461250000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12838.30                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::248-251             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3440                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1163516500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2892379000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    461030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12618.66                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31588.30                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.10                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31368.66                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.09                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.02                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.10                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.05                       # Average system write bandwidth in MiByte/s
@@ -329,36 +329,41 @@ system.physmem.busUtil                           0.03                       # Da
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.03                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      76434                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     70988                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.86                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15422529.71                       # Average gap between requests
-system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2704815148250                       # Time in different power states
-system.physmem.memoryStateTime::REF       94101540000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       19154581250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 134477280                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 122214960                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  73375500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  66684750                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                369415800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                350110800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               291185280                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               286357680                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          184062612240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          184062612240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           70840900170                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           70013903985                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1628700821250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1629426256500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1884472787520                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1884328140915                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.710440                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.659112                       # Core power per rank (mW)
+system.physmem.avgWrQLen                         6.25                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      76428                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     70807                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15425212.92                       # Average gap between requests
+system.physmem.pageHitRate                      81.25                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  134288280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   73012500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 369306600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                291126960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           178872248880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            68915344410                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1612195386000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1860850713630                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.510917                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2632883157750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91447980000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     14405588500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  122351040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   66577500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 349884600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                285444000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           178872248880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68134185630                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1610493455250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1858324146900                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.557325                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2634053636000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91447980000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     13230281250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -378,6 +383,14 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -399,27 +412,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                     5757                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                5757                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         5757                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           5757    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         5757                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 166121609118                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.475514                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.499400                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    87128456868     52.45%     52.45% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    78993152250     47.55%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 166121609118                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3229     67.67%     67.67% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1543     32.33%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4772                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5757                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5757                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4772                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4772                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        10529                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14476474                       # DTB read hits
-system.cpu0.dtb.read_misses                      4869                       # DTB read misses
-system.cpu0.dtb.write_hits                   11056177                       # DTB write hits
-system.cpu0.dtb.write_misses                      893                       # DTB write misses
+system.cpu0.dtb.read_hits                    14474153                       # DTB read hits
+system.cpu0.dtb.read_misses                      4865                       # DTB read misses
+system.cpu0.dtb.write_hits                   11054581                       # DTB write hits
+system.cpu0.dtb.write_misses                      892                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         188                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     401                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3212                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3207                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   944                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   943                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      196                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14481343                       # DTB read accesses
-system.cpu0.dtb.write_accesses               11057070                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      195                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14479018                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11055473                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         25532651                       # DTB hits
-system.cpu0.dtb.misses                           5762                       # DTB misses
-system.cpu0.dtb.accesses                     25538413                       # DTB accesses
+system.cpu0.dtb.hits                         25528734                       # DTB hits
+system.cpu0.dtb.misses                           5757                       # DTB misses
+system.cpu0.dtb.accesses                     25534491                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -441,8 +483,29 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    67995752                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2758                       # ITB inst misses
+system.cpu0.itb.walker.walks                     2755                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2755                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2755                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2755    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2755                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 166121609118                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.475515                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.499400                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    87128348368     52.45%     52.45% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    78993260750     47.55%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 166121609118                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1528     75.53%     75.53% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          495     24.47%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2023                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2755                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2755                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2023                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2023                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4778                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    67991390                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2755                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -451,45 +514,45 @@ system.cpu0.itb.flush_tlb                         188                       # Nu
 system.cpu0.itb.flush_tlb_mva                     401                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1969                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1966                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                67998510                       # ITB inst accesses
-system.cpu0.itb.hits                         67995752                       # DTB hits
-system.cpu0.itb.misses                           2758                       # DTB misses
-system.cpu0.itb.accesses                     67998510                       # DTB accesses
-system.cpu0.numCycles                        82558276                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                67994145                       # ITB inst accesses
+system.cpu0.itb.hits                         67991390                       # DTB hits
+system.cpu0.itb.misses                           2755                       # DTB misses
+system.cpu0.itb.accesses                     67994145                       # DTB accesses
+system.cpu0.numCycles                        82552372                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   66186941                       # Number of instructions committed
-system.cpu0.committedOps                     80639436                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             70858992                       # Number of integer alu accesses
+system.cpu0.committedInsts                   66182532                       # Number of instructions committed
+system.cpu0.committedOps                     80633643                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             70853114                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  5470                       # Number of float alu accesses
-system.cpu0.num_func_calls                    7266542                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      8791397                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    70858992                       # number of integer instructions
+system.cpu0.num_func_calls                    7266071                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      8791663                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    70853114                       # number of integer instructions
 system.cpu0.num_fp_insts                         5470                       # number of float instructions
-system.cpu0.num_int_register_reads          131380013                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          49295072                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          131368884                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          49289864                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                4246                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1228                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           245776790                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           29457750                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     26204570                       # number of memory refs
-system.cpu0.num_load_insts                   14653679                       # Number of load instructions
-system.cpu0.num_store_insts                  11550891                       # Number of store instructions
-system.cpu0.num_idle_cycles              77949108.406676                       # Number of idle cycles
-system.cpu0.num_busy_cycles              4609167.593324                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055829                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944171                       # Percentage of idle cycles
-system.cpu0.Branches                         16455876                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           245759484                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           29458192                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     26200850                       # number of memory refs
+system.cpu0.num_load_insts                   14651277                       # Number of load instructions
+system.cpu0.num_store_insts                  11549573                       # Number of store instructions
+system.cpu0.num_idle_cycles              77943726.541103                       # Number of idle cycles
+system.cpu0.num_busy_cycles              4608645.458897                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055827                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944173                       # Percentage of idle cycles
+system.cpu0.Branches                         16455843                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2193      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 55779692     67.98%     67.99% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58849      0.07%     68.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 55777669     67.99%     67.99% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58831      0.07%     68.06% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     68.06% # Class of executed instruction
@@ -513,294 +576,294 @@ system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.06% # Cl
 system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4532      0.01%     68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4520      0.01%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.06% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.06% # Class of executed instruction
-system.cpu0.op_class::MemRead                14653679     17.86%     85.92% # Class of executed instruction
-system.cpu0.op_class::MemWrite               11550891     14.08%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                14651277     17.86%     85.92% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11549573     14.08%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  82049836                       # Class of executed instruction
+system.cpu0.op_class::total                  82044063                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3055                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           833965                       # number of replacements
+system.cpu0.dcache.tags.replacements           833838                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.996800                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           46972085                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           834477                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            56.289251                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           46974042                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           834350                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            56.300164                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.818118                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.670897                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.507786                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.948864                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032560                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018570                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.894462                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.632625                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.469713                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949013                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032486                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018496                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          195                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        198452344                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       198452344                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     13787811                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      4397354                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      8501200                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       26686365                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     10663716                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3166111                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      5160414                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18990241                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190628                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        60624                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       130481                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       381733                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       235896                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        80331                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       134984                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       451211                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       237277                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        82832                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       139583                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459692                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     24451527                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      7563465                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     13661614                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        45676606                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     24642155                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      7624089                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     13792095                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       46058339                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       191712                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        58922                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       315531                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       566165                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       143864                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        35394                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data      1531641                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1710899                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54000                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        21214                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data        65487                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       140701                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4460                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3296                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         9679                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17435                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        198459549                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       198459549                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     13785736                       # number of ReadReq hits
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
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-system.cpu0.dcache.StoreCondReq_misses::total           17                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       335576                       # number of demand (read+write) misses
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-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    899565500                       # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1328486412                       # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data     10807580                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        81838                       # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       240356                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        83627                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       144663                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       468646                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       237279                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        82832                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1325719411                       # number of WriteReq miss cycles
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 system.cpu0.dcache.StoreCondReq_accesses::total       459709                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     24787103                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      7657781                       # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::cpu0.data     25031731                       # number of overall (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total     48476104                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013714                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013222                       # miss rate for ReadReq accesses
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-system.cpu0.dcache.ReadReq_miss_rate::total     0.020775                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013311                       # miss rate for WriteReq accesses
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-system.cpu0.dcache.WriteReq_miss_rate::total     0.082648                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.220743                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.259219                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.334172                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.269318                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018556                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.039413                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066907                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.037203                       # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018545                       # miss rate for LoadLockedReq accesses
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 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000107                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000037                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013538                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012316                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.119105                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.047485                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015563                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014927                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.121789                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.049875                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056448                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16821.983748                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10963.981973                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37534.226479                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46119.783369                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 42064.106374                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14131.143811                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13679.124496                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10265.356811                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13800.066667                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12176.529412                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23623.265533                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41115.179568                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34331.428710                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19285.483528                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39707.448360                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32333.523062                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       374153                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        25938                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            24753                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            535                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.115461                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    48.482243                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000115                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000039                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013533                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012325                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.119048                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.047479                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015558                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014931                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.121735                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.049871                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.767550                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16642.926742                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10860.397820                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37446.527441                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46032.518019                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 41985.058666                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14080.606061                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13612.771261                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10226.470413                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        16219                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14416.888889                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23574.486138                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41021.105356                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34255.702183                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19253.547815                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39615.225320                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 32261.521207                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       372760                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        22765                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            24978                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            525                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.923533                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    43.361905                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       692650                       # number of writebacks
-system.cpu0.dcache.writebacks::total           692650                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          119                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       155404                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       155523                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1411618                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1411618                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1952                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6678                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8630                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          119                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      1567022                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1567141                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          119                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      1567022                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1567141                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        58803                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       160127                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       218930                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35394                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       120023                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       155417                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20830                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43721                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        64551                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1344                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3001                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4345                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           15                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           15                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        94197                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       280150                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       374347                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       115027                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       323871                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       438898                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    779470500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2130747955                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2910218455                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1251702570                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5436442471                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6688145041                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    266097500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    651596008                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    917693508                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     21534500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     37307002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     58841502                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       176999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       176999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2031173070                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7567190426                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9598363496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2297270570                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8218786434                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10516057004                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1018847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1696409500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2715257000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    779636500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1318509000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2098145500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1798484000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3014918500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4813402500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013196                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018162                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008033                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011055                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017935                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007508                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.254527                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.223103                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.123558                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.016071                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.020745                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.009271                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000107                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012301                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.018064                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.007806                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014862                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020622                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.009054                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13255.624713                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13306.612595                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13292.917622                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35364.823699                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45295.005716                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43033.548717                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12774.723956                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14903.501933                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14216.565320                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16022.693452                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12431.523492                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13542.347986                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11799.933333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11799.933333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21563.033536                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27011.209802                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25640.284271                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19971.576847                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25376.728494                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23960.138811                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       692729                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692729                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          123                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       154842                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       154965                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1412163                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1412163                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1954                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6831                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8785                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          123                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      1567005                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1567128                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          123                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      1567005                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1567128                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        58836                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       160126                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       218962                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35403                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       120009                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       155412                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20795                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43908                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        64703                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1346                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         2870                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4216                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           16                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        94239                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       280135                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       374374                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       115034                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       324043                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       439077                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    777918000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2124515706                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2902433706                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1248908571                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5424851729                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6673760300                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    265951000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    654196260                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    920147260                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     21422750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     35664251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57087001                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       227496                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       227496                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2026826571                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7549367435                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9576194006                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2292777571                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8203563695                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10496341266                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1019447000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1696986500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2716433500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    779587000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1319132500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2098719500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1799034000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3016119000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4815153000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013205                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018152                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008034                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011060                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017927                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007507                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.254373                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.224004                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.123850                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.016095                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019843                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.008998                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000115                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012309                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.018055                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.007807                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014866                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020624                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.009057                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13221.802978                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14899.249795                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14221.091140                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15915.861813                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12426.568293                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.560009                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14218.500000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14218.500000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21507.301340                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26949.033270                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25579.217590                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19931.303536                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25316.281157                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23905.468212                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -811,143 +874,151 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1798241                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.545331                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          100915026                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1798752                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            56.102801                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10926866250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   477.669310                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    21.516745                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    12.359276                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.932948                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.042025                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.024139                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999112                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1797406                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.544833                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          100910374                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1797917                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            56.126269                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10928216250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   477.581873                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    21.468426                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    12.494533                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.932777                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.041931                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.024403                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999111                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          230                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        104562639                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       104562639                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     67129206                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     21624080                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     12161740                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      100915026                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     67129206                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     21624080                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     12161740                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       100915026                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     67129206                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     21624080                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     12161740                       # number of overall hits
-system.cpu0.icache.overall_hits::total      100915026                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       868572                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       248802                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       731453                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1848827                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       868572                       # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total       1848827                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       868572                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       248802                       # number of overall misses
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-system.cpu0.icache.overall_misses::total      1848827                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   3368077000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  10037357964                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13405434964                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   3368077000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  10037357964                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13405434964                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   3368077000                       # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total  13405434964                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     67997778                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     21872882                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.demand_accesses::total    102763853                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     67997778                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     21872882                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     12893193                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    102763853                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012774                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011375                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.056732                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.017991                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012774                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011375                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.056732                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.017991                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012774                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011375                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.056732                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.017991                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.178158                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13722.492032                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7250.778447                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13537.178158                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13722.492032                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7250.778447                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13537.178158                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13722.492032                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7250.778447                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         5131                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        104556280                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       104556280                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     67125667                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     21618827                       # number of ReadReq hits
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+system.cpu0.icache.demand_hits::total       100910374                       # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu1.inst     21618827                       # number of overall hits
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+system.cpu0.icache.overall_hits::total      100910374                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       867746                       # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total      1847960                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   3371834500                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_latency::total  13398807276                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   3371834500                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.demand_miss_latency::total  13398807276                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::total  13398807276                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     67993413                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012762                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011387                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.056695                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.017984                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012762                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011387                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.056695                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.017984                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012762                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011387                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.056695                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.017984                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13540.851445                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.999658                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7250.593777                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13540.851445                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.999658                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7250.593777                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13540.851445                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.999658                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7250.593777                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6029                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              344                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              382                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.915698                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.782723                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        50040                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        50040                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        50040                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        50040                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        50040                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        50040                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       248802                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       681413                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       930215                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       248802                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       681413                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       930215                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       248802                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       681413                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       930215                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2869743000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8188546795                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11058289795                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2869743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8188546795                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11058289795                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2869743000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8188546795                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11058289795                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        50013                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        50013                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        50013                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        50013                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        50013                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        50013                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       249012                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       681189                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       930201                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       249012                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       681189                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       930201                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       249012                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       681189                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       930201                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2873083500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8182514470                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11055597970                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2873083500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8182514470                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11055597970                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2873083500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8182514470                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11055597970                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011387                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.052817                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009052                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011387                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.052817                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.009052                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011375                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.052851                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011387                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.052817                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.009052                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.931907                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12012.105994                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11885.171022                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.931907                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12012.105994                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11885.171022                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.931907                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12012.105994                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11885.171022                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -969,27 +1040,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                     1854                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                1854                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          620                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1234                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         1854                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           1854    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         1854                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1496                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean  9777.746658                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  7722.280706                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6250.292235                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191          511     34.16%     34.16% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383          754     50.40%     84.56% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          230     15.37%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::73728-81919            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1496                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1000015000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1000015000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1000015000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K          885     59.16%     59.16% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          611     40.84%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1496                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1854                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1854                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1496                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1496                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3350                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4627532                       # DTB read hits
-system.cpu1.dtb.read_misses                      1596                       # DTB read misses
-system.cpu1.dtb.write_hits                    3288935                       # DTB write hits
-system.cpu1.dtb.write_misses                      256                       # DTB write misses
+system.cpu1.dtb.read_hits                     4626652                       # DTB read hits
+system.cpu1.dtb.read_misses                      1593                       # DTB read misses
+system.cpu1.dtb.write_hits                    3288334                       # DTB write hits
+system.cpu1.dtb.write_misses                      261                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         166                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     148                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     147                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1270                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1268                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   238                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   232                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                       69                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4629128                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3289191                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 4628245                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3288595                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7916467                       # DTB hits
-system.cpu1.dtb.misses                           1852                       # DTB misses
-system.cpu1.dtb.accesses                      7918319                       # DTB accesses
+system.cpu1.dtb.hits                          7914986                       # DTB hits
+system.cpu1.dtb.misses                           1854                       # DTB misses
+system.cpu1.dtb.accesses                      7916840                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1011,55 +1119,86 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    21872882                       # ITB inst hits
-system.cpu1.itb.inst_misses                       825                       # ITB inst misses
+system.cpu1.itb.walker.walks                      832                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                 832                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          221                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          611                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples          832                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0            832    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total          832                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          612                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  8281.924765                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6395.528631                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::2048-4095          192     31.37%     31.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143            1      0.16%     31.54% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          290     47.39%     78.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335           12      1.96%     80.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-22527          105     17.16%     98.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575           12      1.96%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          612                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          391     63.89%     63.89% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          221     36.11%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          612                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          832                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total          832                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          612                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          612                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1444                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    21867839                       # ITB inst hits
+system.cpu1.itb.inst_misses                       832                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         166                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     148                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     147                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     668                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     672                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                21873707                       # ITB inst accesses
-system.cpu1.itb.hits                         21872882                       # DTB hits
-system.cpu1.itb.misses                            825                       # DTB misses
-system.cpu1.itb.accesses                     21873707                       # DTB accesses
-system.cpu1.numCycles                       158012156                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                21868671                       # ITB inst accesses
+system.cpu1.itb.hits                         21867839                       # DTB hits
+system.cpu1.itb.misses                            832                       # DTB misses
+system.cpu1.itb.accesses                     21868671                       # DTB accesses
+system.cpu1.numCycles                       158011786                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   21172070                       # Number of instructions committed
-system.cpu1.committedOps                     25390672                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22586857                       # Number of integer alu accesses
+system.cpu1.committedInsts                   21167008                       # Number of instructions committed
+system.cpu1.committedOps                     25384727                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             22581810                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1738                       # Number of float alu accesses
-system.cpu1.num_func_calls                    2402647                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2689176                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22586857                       # number of integer instructions
+system.cpu1.num_func_calls                    2402385                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2688390                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    22581810                       # number of integer instructions
 system.cpu1.num_fp_insts                         1738                       # number of float instructions
-system.cpu1.num_int_register_reads           41666783                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15854927                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           41656503                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          15851657                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1290                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                448                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            92283936                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            9328431                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      8130215                       # number of memory refs
-system.cpu1.num_load_insts                    4674464                       # Number of load instructions
-system.cpu1.num_store_insts                   3455751                       # Number of store instructions
-system.cpu1.num_idle_cycles              151523865.450182                       # Number of idle cycles
-system.cpu1.num_busy_cycles              6488290.549818                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.041062                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.958938                       # Percentage of idle cycles
-system.cpu1.Branches                          5242761                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            92262793                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            9324878                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      8128633                       # number of memory refs
+system.cpu1.num_load_insts                    4673659                       # Number of load instructions
+system.cpu1.num_store_insts                   3454974                       # Number of store instructions
+system.cpu1.num_idle_cycles              151523982.353984                       # Number of idle cycles
+system.cpu1.num_busy_cycles              6487803.646016                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.041059                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.958941                       # Percentage of idle cycles
+system.cpu1.Branches                          5241513                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   34      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 17956106     68.78%     68.78% # Class of executed instruction
-system.cpu1.op_class::IntMult                   18827      0.07%     68.85% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 17951469     68.78%     68.78% # Class of executed instruction
+system.cpu1.op_class::IntMult                   18860      0.07%     68.85% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     68.85% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     68.85% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     68.85% # Class of executed instruction
@@ -1083,26 +1222,34 @@ system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.85% # Cl
 system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.85% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.85% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.85% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              1169      0.00%     68.86% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              1172      0.00%     68.86% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.86% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.86% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.86% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4674464     17.91%     86.76% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3455751     13.24%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                 4673659     17.91%     86.76% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3454974     13.24%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  26106351                       # Class of executed instruction
+system.cpu1.op_class::total                  26100168                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               17443399                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9460519                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           398611                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            10920300                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                8161771                       # Number of BTB hits
+system.cpu2.branchPred.lookups               17449157                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          9464735                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           398390                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            10718645                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                8165775                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            74.739439                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4093630                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21092                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            76.182904                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4093661                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             20704                       # Number of incorrect RAS predictions.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1124,27 +1271,100 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu2.dtb.walker.walks                    43517                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               43517                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1        13970                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2        11118                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksSquashedBefore        18429                       # Table walks squashed before starting
+system.cpu2.dtb.walker.walkWaitTime::samples        25088                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::mean   493.961256                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::stdev  3141.545513                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0-8191        24512     97.70%     97.70% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::8192-16383          373      1.49%     99.19% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::16384-24575          135      0.54%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::24576-32767           33      0.13%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::32768-40959           15      0.06%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::40960-49151            7      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::49152-57343            6      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::65536-73727            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::122880-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        25088                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         9234                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean  9422.312939                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  7440.393288                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191         2697     29.21%     29.21% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383         4034     43.69%     72.89% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575         2262     24.50%     97.39% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::24576-32767          120      1.30%     98.69% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-40959           50      0.54%     99.23% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::40960-49151           64      0.69%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::49152-57343            4      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::73728-81919            2      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total         9234                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples  52111304876                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::mean     0.433489                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::stdev     0.514696                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0-1  52056176876     99.89%     99.89% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::2-3     40469500      0.08%     99.97% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::4-5      8303000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::6-7      2155500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::8-9      1410500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::10-11       753500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::12-13       454000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::14-15      1056000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::16-17        83500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::18-19       122000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::20-21        61500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::22-23        86000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::24-25       164500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::26-27         4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::28-29         4500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total  52111304876                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K         2902     72.88%     72.88% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M         1080     27.12%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         3982                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        43517                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        43517                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         3982                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         3982                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        47499                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     9671030                       # DTB read hits
-system.cpu2.dtb.read_misses                     37752                       # DTB read misses
-system.cpu2.dtb.write_hits                    7157940                       # DTB write hits
-system.cpu2.dtb.write_misses                     5738                       # DTB write misses
+system.cpu2.dtb.read_hits                     9677625                       # DTB read hits
+system.cpu2.dtb.read_misses                     37716                       # DTB read misses
+system.cpu2.dtb.write_hits                    7160348                       # DTB write hits
+system.cpu2.dtb.write_misses                     5801                       # DTB write misses
 system.cpu2.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     368                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva                     369                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2464                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      439                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   949                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    2469                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      429                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   945                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      419                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 9708782                       # DTB read accesses
-system.cpu2.dtb.write_accesses                7163678                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      418                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 9715341                       # DTB read accesses
+system.cpu2.dtb.write_accesses                7166149                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         16828970                       # DTB hits
-system.cpu2.dtb.misses                          43490                       # DTB misses
-system.cpu2.dtb.accesses                     16872460                       # DTB accesses
+system.cpu2.dtb.hits                         16837973                       # DTB hits
+system.cpu2.dtb.misses                          43517                       # DTB misses
+system.cpu2.dtb.accesses                     16881490                       # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1166,158 +1386,210 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                    12894617                       # ITB inst hits
-system.cpu2.itb.inst_misses                      6298                       # ITB inst misses
+system.cpu2.itb.walker.walks                     6476                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                6476                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1         2218                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         4151                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksSquashedBefore          107                       # Table walks squashed before starting
+system.cpu2.itb.walker.walkWaitTime::samples         6369                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::mean  1246.035484                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::stdev  5374.992147                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0-8191         6033     94.72%     94.72% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::8192-16383          153      2.40%     97.13% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::16384-24575          113      1.77%     98.90% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::24576-32767           28      0.44%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::32768-40959           19      0.30%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::40960-49151            8      0.13%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::49152-57343            9      0.14%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::57344-65535            3      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::65536-73727            2      0.03%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::73728-81919            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         6369                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples         1962                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean  9197.080965                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  8421.034460                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-8191          606     30.89%     30.89% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::8192-16383          818     41.69%     72.58% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::16384-24575          463     23.60%     96.18% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-32767           28      1.43%     97.60% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-40959           29      1.48%     99.08% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::40960-49151           11      0.56%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::49152-57343            5      0.25%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::57344-65535            1      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::73728-81919            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total         1962                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples   4866645120                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::mean     0.377306                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::stdev     0.486503                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0     3033838520     62.34%     62.34% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::1     1830102100     37.61%     99.94% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::2        2122000      0.04%     99.99% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::3         461500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::4         121000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total   4866645120                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K         1443     77.79%     77.79% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          412     22.21%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total         1855                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         6476                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         6476                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst         1855                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total         1855                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         8331                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    12898498                       # ITB inst hits
+system.cpu2.itb.inst_misses                      6476                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     368                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva                     369                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1799                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                    1789                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1027                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1015                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                12900915                       # ITB inst accesses
-system.cpu2.itb.hits                         12894617                       # DTB hits
-system.cpu2.itb.misses                           6298                       # DTB misses
-system.cpu2.itb.accesses                     12900915                       # DTB accesses
-system.cpu2.numCycles                        69897742                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                12904974                       # ITB inst accesses
+system.cpu2.itb.hits                         12898498                       # DTB hits
+system.cpu2.itb.misses                           6476                       # DTB misses
+system.cpu2.itb.accesses                     12904974                       # DTB accesses
+system.cpu2.numCycles                        69896550                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          26768356                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      69154350                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   17443399                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          12255401                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     39728052                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                2075674                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     91833                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                 964                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              303                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       279943                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       102540                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          510                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 12893196                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               269600                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2749                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          68010313                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.222372                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.345734                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          26772867                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      69167442                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   17449157                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          12259436                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     39647350                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                2075847                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     94572                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                 925                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              261                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       361977                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        99094                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          575                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 12897087                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               269205                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2824                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          68015518                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.222532                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.345771                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                49396667     72.63%     72.63% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                 2406815      3.54%     76.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                 1558633      2.29%     78.46% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4908408      7.22%     85.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                 1099721      1.62%     87.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  702073      1.03%     88.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 3889062      5.72%     94.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  750470      1.10%     95.15% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 3298464      4.85%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                49396866     72.63%     72.63% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                 2407853      3.54%     76.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                 1558370      2.29%     78.46% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4909650      7.22%     85.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                 1103212      1.62%     87.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  700919      1.03%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 3889597      5.72%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  749830      1.10%     95.15% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 3299221      4.85%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            68010313                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.249556                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.989365                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                18657683                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             36955851                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 10391299                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1075131                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                930120                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved             1306172                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred               109269                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              59268734                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               353681                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                930120                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                19279637                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4349454                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      27177493                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 10831041                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              5442328                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              56795330                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 2300                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                936981                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                152434                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               3851730                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           58689966                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            260889069                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        63678439                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             4318                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             48634410                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10055540                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            957404                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        893614                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  6253924                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            10259989                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            7928891                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          1377694                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores         1916931                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  54575287                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             669934                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 51950842                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            68646                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7267604                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     18361034                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         68925                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     68010313                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.763867                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.465859                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            68015518                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.249643                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.989569                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                18660323                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             36954486                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 10395816                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1074729                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                929937                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved             1306815                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred               109505                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              59278443                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               354551                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                929937                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                19281301                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4387069                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      27167714                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 10836297                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5412952                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              56807794                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2395                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                934627                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                156415                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               3819110                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           58701003                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            260943920                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        63689416                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             4317                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             48649356                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10051631                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            957722                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        893887                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  6244990                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            10262812                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            7930622                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          1370921                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores         1928187                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  54587761                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             670112                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 51973443                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            68390                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7260181                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     18315253                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         68730                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     68015518                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.764141                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.466174                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           47556715     69.93%     69.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6835010     10.05%     79.98% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            5099948      7.50%     87.47% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4195226      6.17%     93.64% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1610331      2.37%     96.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1069065      1.57%     97.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            1123688      1.65%     99.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             361159      0.53%     99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             159171      0.23%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           47556774     69.92%     69.92% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            6833375     10.05%     79.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            5102327      7.50%     87.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4195165      6.17%     93.64% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1616653      2.38%     96.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1064575      1.57%     97.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            1125788      1.66%     99.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             361184      0.53%     99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             159677      0.23%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       68010313                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       68015518                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  78624      9.78%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                373360     46.42%     56.20% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               352326     43.80%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  78584      9.71%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                374915     46.33%     56.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               355764     43.96%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass              110      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             34419657     66.25%     66.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               39271      0.08%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             34433275     66.25%     66.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               39265      0.08%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.33% # Type of FU issued
@@ -1330,10 +1602,10 @@ system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.33% # Ty
 system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  2      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  3      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 1      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.33% # Type of FU issued
@@ -1341,101 +1613,101 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.33% # Ty
 system.cpu2.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.33% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc          2864      0.01%     66.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             9952470     19.16%     85.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            7536463     14.51%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc          2873      0.01%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             9958899     19.16%     85.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            7539012     14.51%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              51950842                       # Type of FU issued
-system.cpu2.iq.rate                          0.743241                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     804311                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.015482                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         172775366                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         62545429                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     50354259                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               9588                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              5092                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         4209                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              52749857                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   5186                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          265342                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              51973443                       # Type of FU issued
+system.cpu2.iq.rate                          0.743577                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     809264                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.015571                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         172830468                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         62550700                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     50376095                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               9590                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              5049                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         4207                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              52777410                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   5187                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          265138                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1601303                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1888                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation        38444                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       793651                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1600472                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1933                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation        38461                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       793125                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       130825                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       118759                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       131320                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       120276                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                930120                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                3238109                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               943841                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           55348166                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            92957                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             10259989                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             7928891                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            358502                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 33985                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               900757                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents         38444                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        183146                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       162363                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              345509                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             51516440                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              9776464                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           391010                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                929937                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                3246832                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               971285                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           55360766                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            91934                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             10262812                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             7930622                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            358706                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 34253                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               928134                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents         38461                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        182765                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       162631                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              345396                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             51539725                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              9783295                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           390308                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                       102945                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    17239257                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 9485344                       # Number of branches executed
-system.cpu2.iew.exec_stores                   7462793                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.737026                       # Inst execution rate
-system.cpu2.iew.wb_sent                      51063802                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     50358468                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 26440569                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 45930116                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                       102893                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    17248466                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 9490874                       # Number of branches executed
+system.cpu2.iew.exec_stores                   7465171                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.737372                       # Inst execution rate
+system.cpu2.iew.wb_sent                      51085657                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     50380302                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 26454346                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 45953910                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.720459                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.575670                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.720784                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.575671                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        8108589                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         601009                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           290869                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     66287251                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.712520                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.616760                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8107084                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         601382                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           290377                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     66292417                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.712682                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.616986                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     48204047     72.72%     72.72% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      8094433     12.21%     84.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      3998554      6.03%     90.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      1723968      2.60%     93.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       875669      1.32%     94.89% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       615346      0.93%     95.81% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      1257319      1.90%     97.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       299111      0.45%     98.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1218804      1.84%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     48208105     72.72%     72.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      8091600     12.21%     84.93% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      3999207      6.03%     90.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      1724132      2.60%     93.56% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       877027      1.32%     94.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       615427      0.93%     95.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      1259890      1.90%     97.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       297840      0.45%     98.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1219189      1.84%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     66287251                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            38872037                       # Number of instructions committed
-system.cpu2.commit.committedOps              47230974                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     66292417                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            38883433                       # Number of instructions committed
+system.cpu2.commit.committedOps              47245385                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                      15793926                       # Number of memory references committed
-system.cpu2.commit.loads                      8658686                       # Number of loads committed
-system.cpu2.commit.membars                     225734                       # Number of memory barriers committed
-system.cpu2.commit.branches                   8913791                       # Number of branches committed
+system.cpu2.commit.refs                      15799837                       # Number of memory references committed
+system.cpu2.commit.loads                      8662340                       # Number of loads committed
+system.cpu2.commit.membars                     225899                       # Number of memory barriers committed
+system.cpu2.commit.branches                   8915887                       # Number of branches committed
 system.cpu2.commit.fp_insts                      4128                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 41344274                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             1642310                       # Number of function calls committed.
+system.cpu2.commit.int_insts                 41357490                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             1642928                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        31396236     66.47%     66.47% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          37948      0.08%     66.55% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        31404754     66.47%     66.47% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          37921      0.08%     66.55% # Class of committed instruction
 system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.55% # Class of committed instruction
 system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.55% # Class of committed instruction
 system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.55% # Class of committed instruction
@@ -1459,36 +1731,36 @@ system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.55% #
 system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.55% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.55% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.55% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc         2864      0.01%     66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc         2873      0.01%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.56% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        8658686     18.33%     84.89% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       7135240     15.11%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        8662340     18.33%     84.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       7137497     15.11%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         47230974                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1218804                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total         47245385                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1219189                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   112988408                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  112405622                       # The number of ROB writes
-system.cpu2.timesIdled                         280375                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1887429                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  5250225403                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   38810797                       # Number of Instructions Simulated
-system.cpu2.committedOps                     47169734                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.800987                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.800987                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.555251                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.555251                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                56393520                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               31926452                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    15872                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   13692                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                182232541                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                19215539                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads              124355307                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                481535                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   113003070                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  112431430                       # The number of ROB writes
+system.cpu2.timesIdled                         280451                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1881032                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  5250223632                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   38822148                       # Number of Instructions Simulated
+system.cpu2.committedOps                     47184100                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.800430                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.800430                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.555423                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.555423                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                56420474                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               31939226                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    15888                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   13694                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                182315650                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                19227541                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads              124375401                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                481787                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30188                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30188                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59019                       # Transaction distribution
@@ -1544,7 +1816,7 @@ system.iobus.pkt_size_system.bridge.master::total       159119
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480367                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             18213000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             18225000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1570,25 +1842,25 @@ system.iobus.reqLayer23.occupancy             2807000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy                1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            15730000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            15727000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               25000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           217719639                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           217868633                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            39873000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            39885000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            22974011                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            22990014                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse                0.993341                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.993331                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         245004243009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.993341                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062084                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062084                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         245002453509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.993331                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062083                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062083                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1604,8 +1876,8 @@ system.iocache.overall_misses::realview.ide          252                       #
 system.iocache.overall_misses::total              252                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     14419928                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     14419928                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6029712700                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6029712700                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   6024842691                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   6024842691                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     14419928                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     14419928                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     14419928                       # number of overall miss cycles
@@ -1628,17 +1900,17 @@ system.iocache.overall_miss_rate::realview.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 57221.936508                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 57221.936508                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 57221.936508                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 57221.936508                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 57221.936508                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34890                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs         34568                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 4513                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 4486                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.730999                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.705751                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1646,323 +1918,327 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          127                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        22720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        22720                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        22736                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        22736                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ide          127                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          127                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          127                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          127                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide      7815928                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      7815928                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4848250722                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4848250722                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   4842542719                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   4842542719                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ide      7815928                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total      7815928                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ide      7815928                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total      7815928                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.503968                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.627208                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.627208                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.627650                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.627650                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total     0.503968                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide     0.503968                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     0.503968                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212990.091441                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212990.091441                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 61542.740157                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 61542.740157                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   100831                       # number of replacements
-system.l2c.tags.tagsinuse                65118.744874                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2894730                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166072                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    17.430572                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   100812                       # number of replacements
+system.l2c.tags.tagsinuse                65118.584894                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2893892                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   166052                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    17.427625                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49795.493403                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939326                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   49801.969845                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939327                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5292.397633                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2853.974292                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969197                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1121.420686                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      949.232304                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    58.100226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     3505.367496                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1539.850216                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.759819                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     5299.216432                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2852.911552                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969199                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1106.770268                       # Average occupied blocks per requestor
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 system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    144626500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total     6971987004                       # number of overall miss cycles
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 system.l2c.ReadReq_accesses::cpu1.data          80977                       # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::writebacks       692650                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           692650                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1234                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          436                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         1101                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000797                       # miss rate for ReadReq accesses
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 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000389                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.011336                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.027797                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000725                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.008063                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.031602                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003417                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.011577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.022037                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.014247                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992707                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988532                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.962761                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.980152                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.data      0.031552                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.inst      0.011609                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992713                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988506                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.971612                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.983707                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.066667                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.176471                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.438021                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.400223                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.524832                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.468386                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000797                       # miss rate for demand accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.438164                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.400709                       # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.468332                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000798                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000389                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.011336                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.176753                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000725                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.008063                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.142752                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003417                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.011577                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.205608                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.064555                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000797                       # miss rate for overall accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000724                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003430                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000798                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000389                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.011336                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.176753                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000725                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008063                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.142752                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003417                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.011577                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.205608                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.064555                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu2.data      0.205407                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.064571                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72096.959123                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75383.841344                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77106.382979                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77006.909229                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 81590.718517                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 39048.605025                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data    53.361949                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   284.893396                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   119.656112                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70557.251805                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74662.275908                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 40664.197733                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73101.507538                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 74778.082192                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 83404.255319                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76417.889212                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 80145.919281                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 38757.292317                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data    53.486047                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   263.890669                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   111.515274                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 11749.500000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total         7833                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70261.205395                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74522.716244                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 40554.854940                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72096.959123                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 71303.550453                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77106.382979                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 77006.909229                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 75133.750526                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 40347.147014                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73101.507538                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 70957.808294                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu2.inst 76417.889212                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 74905.768909                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72096.959123                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 71303.550453                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77106.382979                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 77006.909229                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 75133.750526                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 40347.147014                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73101.507538                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 70957.808294                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 83404.255319                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 76417.889212                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 74905.768909                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 40202.125474                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1971,142 +2247,142 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               92900                       # number of writebacks
-system.l2c.writebacks::total                    92900                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data            43                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               92909                       # number of writebacks
+system.l2c.writebacks::total                    92909                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
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 system.l2c.ReadReq_mshr_hits::total                48                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             43                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
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 system.l2c.demand_mshr_hits::total                 48                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            43                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::total                48                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2006                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           94                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         7883                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         7903                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu2.data         4515                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total           17058                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          431                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         1060                       # number of UpgradeReq MSHR misses
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 system.l2c.UpgradeReq_mshr_misses::total         1491                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
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+system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            4                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2006                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu2.dtb.walker           94                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2006                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
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 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
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 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000725                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.008063                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031602                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.962761                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.538073                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.066667                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.058824                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::total     0.257697                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000725                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008063                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.142752                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.data     0.142752                       # mshr miss rate for overall accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.400709                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.524396                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.257566                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000724                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007992                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.142887                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003430                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011603                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.205272                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034918                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000724                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007992                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.142887                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003430                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011603                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.205272                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034918                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62886.186010                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69219.046512                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64881.697444                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60462.060302                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62280.039139                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63863.659370                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67812.900554                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64314.383046                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10002.886792                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.341382                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.356268                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.676727                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57766.563505                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62320.767201                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57472.558521                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62169.148043                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61307.541942                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58558.171601                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62786.059428                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62106.440817                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60462.060302                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58213.978994                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63863.659370                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62550.140576                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61856.475401                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59455.882353                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58558.171601                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 64427.787644                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62786.059428                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62106.440817                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60462.060302                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58213.978994                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63863.659370                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62550.140576                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61856.475401                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2117,55 +2393,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               74228                       # Transaction distribution
-system.membus.trans_dist::ReadResp              74227                       # Transaction distribution
+system.membus.trans_dist::ReadReq               74222                       # Transaction distribution
+system.membus.trans_dist::ReadResp              74221                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27571                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27571                       # Transaction distribution
-system.membus.trans_dist::Writeback            129090                       # Transaction distribution
+system.membus.trans_dist::Writeback            129099                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4545                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4548                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137060                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137060                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4550                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4556                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137047                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137047                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105462                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1990                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       471586                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       579048                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       471572                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       579034                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109015                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       109015                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 688063                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 688049                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159119                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16930172                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17093291                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16929468                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17092587                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4642496                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4642496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21735787                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              288                       # Total snoops (count)
-system.membus.snoop_fanout::samples            341037                       # Request fanout histogram
+system.membus.pkt_size::total                21735083                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              289                       # Total snoops (count)
+system.membus.snoop_fanout::samples            341035                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  341037    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  341035    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              341037                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40803000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              341035                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40827000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              460500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              469500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           937458500                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           937138500                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          904148767                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          904275509                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           23873989                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           23892986                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2198,54 +2474,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2443122                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2443118                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2442249                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2442245                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27571                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27571                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           692650                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        22720                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2771                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            17                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2788                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296527                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296527                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3615529                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2484690                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28930                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        88144                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6217293                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115152760                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97928947                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        48448                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       155392                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              213285547                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           51952                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3431323                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.010630                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.102554                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback           692729                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        22736                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2762                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            18                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2780                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296542                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296542                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3613854                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2484499                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        29280                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87986                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6215619                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115099320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97925875                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        49208                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       154964                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              213229367                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           51973                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3430536                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.010633                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.102566                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3394847     98.94%     98.94% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3394060     98.94%     98.94% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                  36476      1.06%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3431323                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2376326693                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3430536                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         2377189197                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           558000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4188826435                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4188720502                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2020844355                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2021336108                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11830425                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          12001413                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          39636892                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          39606873                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 3bffe858b..355e87caf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.814521                       # Number of seconds simulated
-sim_ticks                                2814521286500                       # Number of ticks simulated
-final_tick                               2814521286500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.814515                       # Number of seconds simulated
+sim_ticks                                2814515403000                       # Number of ticks simulated
+final_tick                               2814515403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106354                       # Simulator instruction rate (inst/s)
-host_op_rate                                   129085                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2558515098                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 570360                       # Number of bytes of host memory used
-host_seconds                                  1100.06                       # Real time elapsed on the host
-sim_insts                                   116996192                       # Number of instructions simulated
-sim_ops                                     142001364                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 109456                       # Simulator instruction rate (inst/s)
+host_op_rate                                   132849                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2632808896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 624704                       # Number of bytes of host memory used
+host_seconds                                  1069.02                       # Real time elapsed on the host
+sim_insts                                   117010217                       # Number of instructions simulated
+sim_ops                                     142017883                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         4288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         4416                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           746368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5095008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           629952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4708740                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           748224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5094496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           629568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4721220                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11189732                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       746368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       629952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1376320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8426816                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11203044                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       748224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       629568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1377792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8429952                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8444340                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           67                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8447476                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           69                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             11662                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             80128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           68                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9843                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             73575                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             11691                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             80120                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           64                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9837                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             73770                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175359                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131669                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175567                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131718                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136050                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136099                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1569                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              265185                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1810257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              223822                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1673016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              265845                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1810079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1455                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              223686                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1677454                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3975714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         265185                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         223822                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             489007                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2994049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3980452                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         265845                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         223686                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             489531                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2995170                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6223                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3000276                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2994049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3001396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2995170                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1569                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             265185                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1816481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             223822                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1673019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             265845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1816303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1455                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             223686                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1677457                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6975990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175360                       # Number of read requests accepted
-system.physmem.writeReqs                       172246                       # Number of write requests accepted
-system.physmem.readBursts                      175360                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     172246                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11215872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  10651968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11189796                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               10760884                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    5779                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4663                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11102                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11119                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11680                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11222                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11370                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11380                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11917                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11794                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10207                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10426                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10580                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9765                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10349                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11405                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10639                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10293                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10392                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               10480                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10999                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               10520                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               10645                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               10713                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               11169                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               10762                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9958                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10000                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9968                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9745                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              10100                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              10962                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              10229                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9795                       # Per bank write bursts
+system.physmem.bw_total::total                6981848                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175568                       # Number of read requests accepted
+system.physmem.writeReqs                       172295                       # Number of write requests accepted
+system.physmem.readBursts                      175568                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     172295                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11229120                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7232                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  10657088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11203108                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               10764020                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      113                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5755                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4657                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11278                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11187                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11389                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10916                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11527                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11542                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11806                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11898                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10235                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10554                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10596                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9816                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10461                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11360                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10541                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10349                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               10520                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               10540                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10805                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               10377                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               10808                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               10825                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               10943                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               10998                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9971                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10108                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9937                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9693                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              10233                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              10896                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              10053                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9810                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2814521100500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2814515217000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     541                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174805                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  175013                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 167865                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    104183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61033                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8516                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1495                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 167914                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    104295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8447                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -161,192 +161,199 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        91                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     8662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     9336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    10292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    10753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    11486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    11345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    11140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    10200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3809                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     9292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    10236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    11546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    11398                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    12006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    11257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10784                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    10246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8299                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        67109                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      325.854595                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.388710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     345.406571                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24509     36.52%     36.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15902     23.70%     60.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6498      9.68%     69.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3742      5.58%     75.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2828      4.21%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1529      2.28%     81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1119      1.67%     83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1119      1.67%     85.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9863     14.70%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          67109                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7131                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.571869                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      462.936248                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7128     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::31                     8036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      292                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        66987                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      326.722260                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.177109                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     345.277059                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24335     36.33%     36.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15823     23.62%     59.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6599      9.85%     69.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3701      5.52%     75.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2840      4.24%     79.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1617      2.41%     81.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1134      1.69%     83.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1090      1.63%     85.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9848     14.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          66987                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7135                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.589488                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      462.801411                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7132     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7131                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7131                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.339924                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.576956                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.763951                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                15      0.21%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.10%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                3      0.04%      0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               7      0.10%      0.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5889     82.58%     83.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             114      1.60%     84.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              53      0.74%     85.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             224      3.14%     88.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             142      1.99%     90.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              54      0.76%     91.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              26      0.36%     91.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              40      0.56%     92.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             124      1.74%     93.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              11      0.15%     94.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              11      0.15%     94.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              11      0.15%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              24      0.34%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              13      0.18%     94.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              13      0.18%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              32      0.45%     95.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              59      0.83%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               9      0.13%     96.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               6      0.08%     96.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               9      0.13%     96.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              92      1.29%     97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.07%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             8      0.11%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             4      0.06%     98.23% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7135                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7135                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.338052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.587494                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.995044                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                12      0.17%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.08%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                5      0.07%      0.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               6      0.08%      0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5911     82.85%     83.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             110      1.54%     84.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              53      0.74%     85.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             225      3.15%     88.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             144      2.02%     90.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              50      0.70%     91.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              36      0.50%     91.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              29      0.41%     92.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             105      1.47%     93.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.24%     94.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              10      0.14%     94.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.20%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              31      0.43%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              18      0.25%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.13%     95.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              33      0.46%     95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              56      0.78%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              14      0.20%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.08%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              11      0.15%     96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              75      1.05%     97.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             8      0.11%     98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            14      0.20%     98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     98.23% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115            17      0.24%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.04%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            14      0.20%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.04%     98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            38      0.53%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             9      0.13%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.06%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             9      0.13%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             3      0.04%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.04%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             7      0.10%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.04%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             3      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7131                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2737638250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6023538250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    876240000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15621.51                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::116-119             5      0.07%     98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             6      0.08%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             5      0.07%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            32      0.45%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             7      0.10%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             6      0.08%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.07%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             7      0.10%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             9      0.13%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.04%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             3      0.04%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.07%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.04%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7135                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2670855500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5960636750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    877275000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15222.45                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34371.51                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  33972.45                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.79                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144870                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    129705                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8096871.46                       # Average gap between requests
-system.physmem.pageHitRate                      80.35                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2688100208500                       # Time in different power states
-system.physmem.memoryStateTime::REF       93982980000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       32438087000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 267820560                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 239523480                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 146132250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 130692375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                714347400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                652579200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               555206400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               523305360                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          183830708880                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          183830708880                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           78196283910                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           77193580095                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1620118404000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1620997968750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1883828903400                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1883568358140                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.325253                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.232681                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.82                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        11.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145151                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    129833                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.73                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.96                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8090872.61                       # Average gap between requests
+system.physmem.pageHitRate                      80.41                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  265386240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  144804000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 714027600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                556087680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           183830200320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            77881590900                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1620389778750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1883781875490                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.310395                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2695567326750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     93982720000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     24965345250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  241035480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  131517375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654513600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                522942480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           183830200320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            77208822180                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1620979926750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1883568958185                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.234745                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2696551299250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     93982720000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23977600750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          640                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           640                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst          640                       # Number of instructions bytes read from this memory
@@ -365,16 +372,24 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               27454524                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14302225                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           560028                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            17144432                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12924274                       # Number of BTB hits
+system.cpu0.branchPred.lookups               27466718                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14314218                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           559197                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            17107445                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12928393                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            75.384673                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6779174                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             30579                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            75.571735                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6777363                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             30194                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -396,27 +411,104 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                    58720                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               58720                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        19962                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14154                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        24604                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        34116                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   475.187595                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3075.067201                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        33369     97.81%     97.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          426      1.25%     99.06% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          228      0.67%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767           49      0.14%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           15      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            6      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::122880-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        34116                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12972                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12168.830173                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9642.893366                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7992.253434                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-8191         3564     27.47%     27.47% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::8192-16383         6077     46.85%     74.32% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2864     22.08%     96.40% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::24576-32767          230      1.77%     98.17% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-40959           90      0.69%     98.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::40960-49151          115      0.89%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-57343           10      0.08%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::57344-65535            3      0.02%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::73728-81919           10      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-90111            4      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::90112-98303            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-106495            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        12972                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  78620736948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.741175                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.458010                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  78549397948     99.91%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     52259000      0.07%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      9664500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      3325500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2093000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1088000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       676500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      1423500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       291000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       117500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        73500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        71500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       138500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        55500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29         6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31        55500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  78620736948                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3790     68.96%     68.96% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1706     31.04%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5496                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58720                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58720                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5496                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5496                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        64216                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    14369333                       # DTB read hits
-system.cpu0.dtb.read_misses                     50679                       # DTB read misses
-system.cpu0.dtb.write_hits                   10383293                       # DTB write hits
-system.cpu0.dtb.write_misses                     7631                       # DTB write misses
+system.cpu0.dtb.read_hits                    14377700                       # DTB read hits
+system.cpu0.dtb.read_misses                     50689                       # DTB read misses
+system.cpu0.dtb.write_hits                   10391095                       # DTB write hits
+system.cpu0.dtb.write_misses                     8031                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3537                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1074                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1312                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3541                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1016                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1359                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      596                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14420012                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10390924                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      592                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14428389                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10399126                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24752626                       # DTB hits
-system.cpu0.dtb.misses                          58310                       # DTB misses
-system.cpu0.dtb.accesses                     24810936                       # DTB accesses
+system.cpu0.dtb.hits                         24768795                       # DTB hits
+system.cpu0.dtb.misses                          58720                       # DTB misses
+system.cpu0.dtb.accesses                     24827515                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -438,158 +530,209 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    20633477                       # ITB inst hits
-system.cpu0.itb.inst_misses                      8891                       # ITB inst misses
+system.cpu0.itb.walker.walks                     8876                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                8876                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3394                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5333                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          149                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         8727                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1034.949009                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  4440.773831                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         8334     95.50%     95.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          202      2.31%     97.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          114      1.31%     99.12% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           44      0.50%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           18      0.21%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151            9      0.10%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343            3      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         8727                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2584                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12070.828560                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9384.773588                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7691.454372                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          754     29.18%     29.18% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1107     42.84%     72.02% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          648     25.08%     97.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           49      1.90%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           17      0.66%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            4      0.15%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.12%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2584                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  31375770192                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.875900                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.330034                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     3896845928     12.42%     12.42% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    27476174764     87.57%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2435000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         275000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          39500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  31375770192                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1855     76.18%     76.18% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          580     23.82%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2435                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8876                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8876                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2435                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2435                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        11311                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20634228                       # ITB inst hits
+system.cpu0.itb.inst_misses                      8876                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         181                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2375                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2373                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1486                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1477                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20642368                       # ITB inst accesses
-system.cpu0.itb.hits                         20633477                       # DTB hits
-system.cpu0.itb.misses                           8891                       # DTB misses
-system.cpu0.itb.accesses                     20642368                       # DTB accesses
-system.cpu0.numCycles                       108176623                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20643104                       # ITB inst accesses
+system.cpu0.itb.hits                         20634228                       # DTB hits
+system.cpu0.itb.misses                           8876                       # DTB misses
+system.cpu0.itb.accesses                     20643104                       # DTB accesses
+system.cpu0.numCycles                       108167671                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          40839610                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     106163283                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   27454524                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19703448                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     62043143                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3268003                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    133218                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                6760                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              444                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       566983                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       143911                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          303                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20632158                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               383201                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3475                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         105368337                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.210422                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.308267                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          40851007                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     106236775                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   27466718                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19705756                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     62062972                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3267693                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    153669                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                7048                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              432                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       489783                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       144519                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          202                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20632894                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               382391                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3679                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         105343442                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.211364                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.309053                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                76140836     72.26%     72.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3909718      3.71%     75.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2409828      2.29%     78.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 8201309      7.78%     86.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1666024      1.58%     87.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1066995      1.01%     88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6252269      5.93%     94.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1076692      1.02%     95.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4644666      4.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                76103279     72.24%     72.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3910098      3.71%     75.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2412212      2.29%     78.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 8199484      7.78%     86.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1671331      1.59%     87.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1069053      1.01%     88.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6251821      5.93%     94.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1074556      1.02%     95.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4651608      4.42%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           105368337                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.253794                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.981388                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                28207041                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58279935                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15901267                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1497528                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1482288                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1929977                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               153844                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              87989191                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               497994                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1482288                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                29073693                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                7845343                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      44593101                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16518954                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              5854664                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              84134111                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 3122                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1216605                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                229511                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               3673419                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           86811691                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            387318144                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        93734921                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6132                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             72788537                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                14023138                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1551068                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1456111                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8913232                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            15130036                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11520954                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1958410                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2751427                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  80936298                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1061855                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 77564111                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            93737                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10215309                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     25112322                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        116543                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    105368337                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.736124                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.430465                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           105343442                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.253927                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.982149                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                28225112                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             58231710                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15904811                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1498973                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1482577                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1930879                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               153387                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              88028064                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               497001                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1482577                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                29091969                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                7814173                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      44573853                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16523893                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              5856699                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              84168015                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 2790                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1211369                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                234681                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               3674238                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           86834114                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            387462225                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        93765985                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6215                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72808994                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                14025104                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1551576                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1456348                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8924255                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            15135142                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11528605                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1955130                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2746979                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  80972727                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1061733                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 77600115                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            93477                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10225467                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     25113988                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        116264                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    105343442                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.736639                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.430545                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           74478008     70.68%     70.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10230371      9.71%     80.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7904463      7.50%     87.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6602787      6.27%     94.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2340926      2.22%     96.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1499410      1.42%     97.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1574332      1.49%     99.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             494613      0.47%     99.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             243427      0.23%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           74430085     70.65%     70.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10248464      9.73%     80.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7900647      7.50%     87.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6607763      6.27%     94.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2341378      2.22%     96.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1506364      1.43%     97.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1572871      1.49%     99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             494450      0.47%     99.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             241420      0.23%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      105368337                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      105343442                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 114999     10.01%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     3      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                537121     46.77%     56.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               496300     43.22%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 114775     10.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     3      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                538516     46.90%     56.89% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               494955     43.11%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2212      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             51748002     66.72%     66.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57664      0.07%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2213      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             51768146     66.71%     66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57542      0.07%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.79% # Type of FU issued
@@ -612,411 +755,411 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.79% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4488      0.01%     66.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     66.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14779498     19.05%     85.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10972237     14.15%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4481      0.01%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14787493     19.06%     85.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           10980227     14.15%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              77564111                       # Type of FU issued
-system.cpu0.iq.rate                          0.717014                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1148423                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.014806                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         261725178                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         92258450                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     75089604                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              13541                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              7156                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5898                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              78703023                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   7299                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          349741                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              77600115                       # Type of FU issued
+system.cpu0.iq.rate                          0.717406                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1148249                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014797                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         261771758                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         92305365                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     75123288                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              13640                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              7254                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5910                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              78738792                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7359                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          349889                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2246191                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2538                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        53151                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1141086                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2246274                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2500                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53675                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1142950                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       210404                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       206292                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       210780                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       206750                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1482288                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5387849                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              2181647                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           82121235                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           133747                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             15130036                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11520954                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            554131                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44613                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              2124772                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         53151                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        259624                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       223920                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              483544                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             76945762                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14537604                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           560147                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1482577                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5380945                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              2158862                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           82157406                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           132522                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             15135142                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11528605                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            554173                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 44324                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              2102450                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53675                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        259338                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       224546                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              483884                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             76981591                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14546003                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           559940                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       123082                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25403316                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14507602                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10865712                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.711298                       # Inst execution rate
-system.cpu0.iew.wb_sent                      76276982                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     75095502                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 39231378                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 67987446                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       122946                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25419191                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14512373                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10873188                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.711688                       # Inst execution rate
+system.cpu0.iew.wb_sent                      76311316                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     75129198                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 39246313                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 68010606                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.694193                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.577039                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.694562                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.577062                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       11493235                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         945312                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           408278                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    102784889                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.686324                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.576953                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       11503261                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         945469                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           407891                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    102758261                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.686747                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.577053                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     75343720     73.30%     73.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12296354     11.96%     85.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6287520      6.12%     91.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2655547      2.58%     93.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1297923      1.26%     95.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       837088      0.81%     96.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1893538      1.84%     97.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       418210      0.41%     98.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1754989      1.71%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     75291319     73.27%     73.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12321005     11.99%     85.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6288153      6.12%     91.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2655881      2.58%     93.96% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1298740      1.26%     95.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       839233      0.82%     96.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1891164      1.84%     97.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       416236      0.41%     98.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1756530      1.71%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    102784889                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            58163617                       # Number of instructions committed
-system.cpu0.commit.committedOps              70543777                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    102758261                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            58183568                       # Number of instructions committed
+system.cpu0.commit.committedOps              70568955                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23263713                       # Number of memory references committed
-system.cpu0.commit.loads                     12883845                       # Number of loads committed
-system.cpu0.commit.membars                     375648                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13703294                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5822                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 61764808                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2662565                       # Number of function calls committed.
+system.cpu0.commit.refs                      23274523                       # Number of memory references committed
+system.cpu0.commit.loads                     12888868                       # Number of loads committed
+system.cpu0.commit.membars                     375842                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13706650                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5838                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 61788721                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2663542                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        47219648     66.94%     66.94% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55928      0.08%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4488      0.01%     67.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        47234123     66.93%     66.93% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55828      0.08%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4481      0.01%     67.02% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.02% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.02% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.02% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12883845     18.26%     85.29% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10379868     14.71%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12888868     18.26%     85.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10385655     14.72%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         70543777                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1754989                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total         70568955                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1756530                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   170407355                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  166661887                       # The number of ROB writes
-system.cpu0.timesIdled                         403384                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        2808286                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2462180041                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   58092959                       # Number of Instructions Simulated
-system.cpu0.committedOps                     70473119                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.862130                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.862130                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.537020                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.537020                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                83669019                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               47858513                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16561                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13070                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                272007090                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                28371958                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              192053211                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                725022                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           853093                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.984491                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42526051                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           853605                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.819356                       # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads                   170410924                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  166734025                       # The number of ROB writes
+system.cpu0.timesIdled                         403289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2824229                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2462180705                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   58113002                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70498389                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.861333                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.861333                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.537249                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.537249                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                83710036                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47877732                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16593                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13071                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                272135235                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                28380305                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              192072102                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                725098                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           853107                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.984634                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42535549                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           853619                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.829665                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         91705250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   331.074612                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   180.909879                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.646630                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.353340                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   327.353563                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   184.631071                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.639362                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.360608                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189920314                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189920314                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12675400                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12670649                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25346049                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7759190                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8148697                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15907887                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181607                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180873                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       362480                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209218                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       237638                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446856                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       215214                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       244406                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459620                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20434590                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20819346                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41253936                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20616197                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21000219                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41616416                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       429328                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       400663                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       829991                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1922864                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1781286                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3704150                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        97758                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        84121                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       181879                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13488                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14194                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27682                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           28                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           50                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses        189955198                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189955198                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12681674                       # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::cpu0.data      7766233                       # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181732                       # number of SoftPFReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209455                       # number of LoadLockedReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total       447130                       # number of LoadLockedReq hits
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+system.cpu0.dcache.demand_hits::cpu0.data     20447907                       # number of demand (read+write) hits
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+system.cpu0.dcache.demand_hits::total        41263508                       # number of demand (read+write) hits
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+system.cpu0.dcache.ReadReq_misses::total       832250                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1921923                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::total      3700347                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        98138                       # number of SoftPFReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total       182587                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13508                       # number of LoadLockedReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total        27709                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           30                       # number of StoreCondReq misses
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 system.cpu0.dcache.StoreCondReq_misses::total           78                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2352192                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2181949                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4534141                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2449950                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2266070                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4716020                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7076789424                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6619917975                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  13696707399                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83693793081                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  75813102630                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 159506895711                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183195494                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    209562743                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    392758237                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       592508                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       853516                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data      2351648                       # number of demand (read+write) misses
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+system.cpu0.dcache.demand_misses::total       4532597                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2449786                       # number of overall misses
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+system.cpu0.dcache.overall_misses::total      4715184                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7060794359                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6694788448                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  13755582807                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83430874942                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  75332466558                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 158763341500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    183117244                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    210458494                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    393575738                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       643510                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       802514                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total      1446024                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  90770582505                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  82433020605                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 173203603110                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  90770582505                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  82433020605                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 173203603110                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     13104728                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13071312                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26176040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9682054                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9929983                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19612037                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       279365                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       264994                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       544359                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222706                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251832                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474538                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       215242                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       244456                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459698                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22786782                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23001295                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45788077                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     23066147                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23266289                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46332436                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032761                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030652                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031708                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198601                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179385                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188871                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.349929                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.317445                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.334116                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060564                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056363                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058335                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000130                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000205                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data  90491669301                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  82027255006                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 172518924307                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  90491669301                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  82027255006                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 172518924307                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     13111399                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13070058                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26181457                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9688156                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9926492                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19614648                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       279870                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       264780                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       544650                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222963                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       251876                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       215343                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       244453                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459796                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22799555                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     22996550                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45796105                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     23079425                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23261330                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46340755                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032775                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030797                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031788                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.198379                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.179159                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188652                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.350656                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.318940                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335237                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060584                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.056381                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058355                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000139                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000196                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000170                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103226                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094862                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099024                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106214                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097397                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.101787                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16483.409943                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16522.409045                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16502.236047                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43525.591556                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42560.881650                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43061.672910                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13582.109579                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14764.178033                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14188.217506                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        21161                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17070.320000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103144                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.094838                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.098973                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106146                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.097389                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.101750                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16430.960170                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16631.981735                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16528.186010                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43410.102768                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42359.114901                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 42904.987424                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13556.206988                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14819.977044                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14203.895413                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21450.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16719.041667                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38589.784552                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37779.535913                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 38199.871400                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37049.973471                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36377.084823                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36726.647281                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1109617                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       154794                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            70377                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2390                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.766756                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    64.767364                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38480.108120                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37610.808417                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 38061.827316                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36938.601699                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36208.761112                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36587.951670                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1102752                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       157342                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            69674                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2409                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.827310                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    65.314238                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       704003                       # number of writebacks
-system.cpu0.dcache.writebacks::total           704003                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215622                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       188357                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       403979                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1768499                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1636007                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3404506                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9539                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8963                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18502                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1984121                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1824364                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3808485                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1984121                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1824364                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3808485                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       213706                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       212306                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       426012                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       154365                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       145279                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299644                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        64075                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57558                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       121633                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3949                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5231                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9180                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           28                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           50                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       703765                       # number of writebacks
+system.cpu0.dcache.writebacks::total           703765                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       215820                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       190387                       # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1767730                       # number of WriteReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total      3401042                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9415                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8962                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18377                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1983550                       # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::total      3807249                       # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total      3807249                       # number of overall MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       154193                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total       299305                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        64082                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57716                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       121798                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4093                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5239                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9332                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           30                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           48                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total           78                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       368071                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       357585                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       725656                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       432146                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       415143                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       847289                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2880376399                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2931260112                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5811636511                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6719128315                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6232840178                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12951968493                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    978421259                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    894015008                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1872436267                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     46952751                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     79934003                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    126886754                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       536492                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       753484                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       368098                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       357250                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       725348                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       432180                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       414966                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       847146                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2879120711                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2930558911                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5809679622                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6700541283                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6184063438                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12884604721                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    975154510                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    900261506                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1875416016                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     47931501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     80133502                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    128065003                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       583490                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       706486                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1289976                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9599504714                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9164100290                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  18763605004                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10577925973                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10058115298                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  20636041271                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3170222000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2614349000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784571000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2418015877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2018079000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436094877                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5588237877                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4632428000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220665877                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016308                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016242                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016275                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015943                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014630                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015279                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.229359                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.217205                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223443                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017732                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020772                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019345                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000130                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000205                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9579661994                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9114622349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  18694284343                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10554816504                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10014883855                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  20569700359                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3162299001                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2622267000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5784566001                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2409236377                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2026898500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4436134877                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5571535378                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   4649165500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10220700878                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016314                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016231                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016273                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015916                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014619                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015259                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228971                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.217977                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223626                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018357                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020800                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019653                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000139                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000196                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000170                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016153                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015546                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018735                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017843                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018287                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016145                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015535                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015839                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018726                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017839                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018281                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13459.810248                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13814.398698                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13636.369151                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43455.547807                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42615.796337                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43048.411223                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15217.292063                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15598.127140                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15397.757073                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11710.603714                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15295.572056                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13723.210780                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19449.666667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14718.458333                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26024.759694                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25513.288591                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25772.848816                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24422.269665                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24134.227515                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24281.175097                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1027,150 +1170,158 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1945413                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.581807                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39117111                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1945925                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.102065                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9481344250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.889096                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   233.692710                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.542752                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.456431                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999183                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1946899                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.580862                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           39112552                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1947411                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.084385                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9482142250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   275.928996                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   235.651865                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.538924                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.460258                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999181                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          158                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43149539                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43149539                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19581058                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19536053                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39117111                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19581058                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19536053                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39117111                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19581058                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19536053                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39117111                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1050436                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1035972                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2086408                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1050436                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1035972                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2086408                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1050436                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1035972                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2086408                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14355946637                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14071596928                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  28427543565                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14355946637                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  14071596928                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  28427543565                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14355946637                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  14071596928                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  28427543565                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20631494                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20572025                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41203519                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20631494                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20572025                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41203519                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20631494                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20572025                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41203519                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050914                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050358                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050637                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050914                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050358                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050637                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050914                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050358                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050637                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13666.655215                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13582.989625                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13625.112425                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13625.112425                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13666.655215                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13582.989625                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13625.112425                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         9173                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         43147534                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        43147534                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19581661                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19530891                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       39112552                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19581661                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19530891                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        39112552                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19581661                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19530891                       # number of overall hits
+system.cpu0.icache.overall_hits::total       39112552                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1050570                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1036904                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2087474                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1050570                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1036904                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2087474                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1050570                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1036904                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2087474                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14373129884                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14097990125                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  28471120009                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14373129884                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  14097990125                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  28471120009                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14373129884                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  14097990125                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  28471120009                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20632231                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20567795                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     41200026                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20632231                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20567795                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     41200026                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20632231                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20567795                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     41200026                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050919                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050414                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050667                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050919                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050414                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050667                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050919                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050414                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050667                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13681.268153                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.234680                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13639.029760                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13681.268153                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13596.234680                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13639.029760                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13681.268153                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13596.234680                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13639.029760                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         8502                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              525                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              563                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.472381                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.101243                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70447                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        69940                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       140387                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        70447                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        69940                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       140387                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        70447                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        69940                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       140387                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       979989                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       966032                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1946021                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       979989                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       966032                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1946021                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       979989                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       966032                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1946021                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11725666308                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11493227261                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  23218893569                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11725666308                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11493227261                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  23218893569                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11725666308                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11493227261                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  23218893569                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     49455500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     49455500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total     49455500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047229                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047229                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047500                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046959                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047229                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11931.471227                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11965.099923                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11897.356672                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11931.471227                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70345                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        69620                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       139965                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        70345                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        69620                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       139965                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        70345                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        69620                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       139965                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       980225                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       967284                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1947509                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       980225                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       967284                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1947509                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       980225                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       967284                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1947509                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11736390069                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11515392307                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  23251782376                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11736390069                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11515392307                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  23251782376                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11736390069                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11515392307                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  23251782376                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     49454750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     49454750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     49454750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total     49454750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047270                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047270                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.047509                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.047029                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047270                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11939.242579                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11939.242579                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.159294                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.872103                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11939.242579                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27255758                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14164958                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           545624                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17245755                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               12796801                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27252662                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14161158                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           545075                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17238794                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               12795126                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            74.202614                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6756979                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29539                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            74.222860                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6755804                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29339                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1192,27 +1343,102 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                    58706                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               58706                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19477                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14176                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25053                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        33653                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   557.840311                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3475.112155                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-8191        32827     97.55%     97.55% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-16383          501      1.49%     99.03% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-24575          206      0.61%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-32767           52      0.15%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-40959           23      0.07%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-49151           18      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-57343           14      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-73727            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::81920-90111            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::90112-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-106495            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::122880-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        33653                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        11554                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10457.034101                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  8151.140813                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7042.402736                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         4078     35.30%     35.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5524     47.81%     83.11% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1648     14.26%     97.37% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          166      1.44%     98.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959           76      0.66%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           59      0.51%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::73728-81919            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        11554                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  82024244244                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.681515                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.487291                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  81955384244     99.92%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     50513000      0.06%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5      9145000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      3183000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      1958500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1084000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       660000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15       995500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       376500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       124000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21        98500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        69500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25        91500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        76000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29       274000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31       211000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  82024244244                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3372     68.52%     68.52% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1549     31.48%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         4921                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58706                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58706                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         4921                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         4921                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        63627                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14301761                       # DTB read hits
-system.cpu1.dtb.read_misses                     48555                       # DTB read misses
-system.cpu1.dtb.write_hits                   10652785                       # DTB write hits
-system.cpu1.dtb.write_misses                    10002                       # DTB write misses
+system.cpu1.dtb.read_hits                    14299827                       # DTB read hits
+system.cpu1.dtb.read_misses                     48713                       # DTB read misses
+system.cpu1.dtb.write_hits                   10649623                       # DTB write hits
+system.cpu1.dtb.write_misses                     9993                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         175                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3340                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    3345                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                      749                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1278                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  1307                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      539                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14350316                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10662787                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      516                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14348540                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10659616                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         24954546                       # DTB hits
-system.cpu1.dtb.misses                          58557                       # DTB misses
-system.cpu1.dtb.accesses                     25013103                       # DTB accesses
+system.cpu1.dtb.hits                         24949450                       # DTB hits
+system.cpu1.dtb.misses                          58706                       # DTB misses
+system.cpu1.dtb.accesses                     25008156                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1234,329 +1460,386 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    20573712                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7567                       # ITB inst misses
+system.cpu1.itb.walker.walks                     7607                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7607                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2551                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4918                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          138                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7469                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1253.983130                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  5505.331618                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         7086     94.87%     94.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          200      2.68%     97.55% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575          109      1.46%     99.01% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           32      0.43%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           14      0.19%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           11      0.15%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343            1      0.01%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            6      0.08%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::106496-114687            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7469                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2377                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11683.850652                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  8982.900240                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7620.243918                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095          698     29.36%     29.36% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191           50      2.10%     31.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          916     38.54%     70.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383           82      3.45%     73.45% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           34      1.43%     74.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575          536     22.55%     97.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           26      1.09%     98.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            4      0.17%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            7      0.29%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959           17      0.72%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            6      0.25%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2377                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  26182117896                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.680154                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.466824                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     8377919500     32.00%     32.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    17801455396     67.99%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2155000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         325500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         194500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          68000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  26182117896                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1688     75.39%     75.39% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          551     24.61%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2239                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7607                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7607                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2239                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2239                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         9846                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20569517                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7607                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         175                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2209                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2207                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1224                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1289                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20581279                       # ITB inst accesses
-system.cpu1.itb.hits                         20573712                       # DTB hits
-system.cpu1.itb.misses                           7567                       # DTB misses
-system.cpu1.itb.accesses                     20581279                       # DTB accesses
-system.cpu1.numCycles                       106992745                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20577124                       # ITB inst accesses
+system.cpu1.itb.hits                         20569517                       # DTB hits
+system.cpu1.itb.misses                           7607                       # DTB misses
+system.cpu1.itb.accesses                     20577124                       # DTB accesses
+system.cpu1.numCycles                       107002102                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          40476291                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     106336791                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27255758                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19553780                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     61749013                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3214085                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    109935                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                4125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              398                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       310457                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       137038                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20572028                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               377209                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3305                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         104394378                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.225923                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.323476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          40500350                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     106310459                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27252662                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19550930                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     61683449                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3213099                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    111780                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                3981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              436                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       347701                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       135656                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          234                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20567798                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               376508                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3292                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         104390100                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.225611                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.323253                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                75141351     71.98%     71.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3905835      3.74%     75.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2486724      2.38%     78.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8099869      7.76%     85.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1581267      1.51%     87.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1170303      1.12%     88.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6153110      5.89%     94.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1141979      1.09%     95.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4713940      4.52%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                75144035     71.98%     71.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3907124      3.74%     75.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2485008      2.38%     78.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8099840      7.76%     85.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1578542      1.51%     87.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1169165      1.12%     88.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6151960      5.89%     94.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1142182      1.09%     95.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4712244      4.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           104394378                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.254744                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.993869                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                27669699                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             57891094                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15657559                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1717451                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1458318                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1956668                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               150768                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              88739686                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               487490                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1458318                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                28613011                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                6694397                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      45325373                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16423590                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              5879419                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              84880856                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 2064                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1581177                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                275105                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               3240122                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           87684483                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            391488803                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        94864107                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5764                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             73992323                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13692160                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1588753                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1487965                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10049323                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15109971                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11816534                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2163704                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2733219                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  81632312                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1156422                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 78295274                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            93656                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        9981310                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25207475                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        106198                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    104394378                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.749995                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.429509                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           104390100                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.254693                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.993536                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                27682693                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             57882458                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15650277                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1716894                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1457466                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1955529                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               151159                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              88694873                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               489106                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1457466                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                28625802                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                6604433                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      45361321                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16416425                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              5924344                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              84834346                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 2307                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1574765                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                278233                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               3285499                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           87641847                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            391276070                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94803920                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5749                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             73988395                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13653452                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1589936                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1488982                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 10049361                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15102779                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11808907                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2150791                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2768917                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  81595404                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1156818                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78284353                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            93210                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        9952134                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     25073057                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        106330                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    104390100                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.749921                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.429238                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           72878860     69.81%     69.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10639333     10.19%     80.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8017923      7.68%     87.68% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6659758      6.38%     94.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2479715      2.38%     96.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1538380      1.47%     97.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1459445      1.40%     99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             494321      0.47%     99.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             226643      0.22%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           72870740     69.81%     69.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10640655     10.19%     80.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8029126      7.69%     87.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6654786      6.37%     94.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2478739      2.37%     96.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1537519      1.47%     97.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1459463      1.40%     99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             490817      0.47%     99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             228255      0.22%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      104394378                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      104390100                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 101103      8.77%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.77% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                535174     46.44%     55.22% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               516045     44.78%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 100798      8.75%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     4      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.75% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                535574     46.51%     55.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               515204     44.74%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass              125      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             52268288     66.76%     66.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59024      0.08%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              1      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              1      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4106      0.01%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass              124      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52262651     66.76%     66.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59116      0.08%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4115      0.01%     66.84% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14700600     18.78%     85.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11263124     14.39%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             1      0.00%     66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14698419     18.78%     85.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11259924     14.38%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              78295274                       # Type of FU issued
-system.cpu1.iq.rate                          0.731781                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1152326                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014718                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         262217922                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         92814464                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     75924804                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              12986                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6859                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5648                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              79440457                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7018                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          366358                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78284353                       # Type of FU issued
+system.cpu1.iq.rate                          0.731615                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1151580                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014710                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         262190696                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         92748647                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     75915598                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              12900                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6883                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5649                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79428849                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6960                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          366149                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2171723                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2780                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        52487                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1144439                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2166601                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2614                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        52391                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1139774                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       191401                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       154292                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       191651                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       153600                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1458318                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4304329                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2156600                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           82933418                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           134740                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15109971                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11816534                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            582996                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 47778                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2096463                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         52487                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        251579                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       218702                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              470281                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             77694436                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14463933                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           542445                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1457466                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                4280991                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2091777                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           82896193                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           132170                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15102779                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11808907                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            583505                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 47325                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2032029                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         52391                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        250395                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       218336                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              468731                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77684491                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14461832                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           541313                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       144684                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25618626                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14454326                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11154693                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.726165                       # Inst execution rate
-system.cpu1.iew.wb_sent                      77075073                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     75930452                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 39739983                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 69711076                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       143971                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25613639                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14454387                       # Number of branches executed
+system.cpu1.iew.exec_stores                  11151807                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.726009                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77065601                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     75921247                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39733715                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69689049                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.709679                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.570067                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.709530                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.570157                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       11308333                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls        1050224                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           396863                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    101852612                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.703099                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.586744                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       11280608                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls        1050488                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           395955                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    101852201                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.703017                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.586598                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     73894552     72.55%     72.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12525380     12.30%     84.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6426003      6.31%     91.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2662589      2.61%     93.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1410437      1.38%     95.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       930996      0.91%     96.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1822810      1.79%     97.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       425009      0.42%     98.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1754836      1.72%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     73888394     72.54%     72.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12531229     12.30%     84.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6432271      6.32%     91.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2665520      2.62%     93.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1405579      1.38%     95.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       922819      0.91%     96.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1826114      1.79%     97.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       423793      0.42%     98.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1756482      1.72%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    101852612                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            58987480                       # Number of instructions committed
-system.cpu1.commit.committedOps              71612492                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    101852201                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            58981554                       # Number of instructions committed
+system.cpu1.commit.committedOps              71603833                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23610343                       # Number of memory references committed
-system.cpu1.commit.loads                     12938248                       # Number of loads committed
-system.cpu1.commit.membars                     439261                       # Number of memory barriers committed
-system.cpu1.commit.branches                  13694369                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5606                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 62760739                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2679383                       # Number of function calls committed.
+system.cpu1.commit.refs                      23605311                       # Number of memory references committed
+system.cpu1.commit.loads                     12936178                       # Number of loads committed
+system.cpu1.commit.membars                     439363                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13694258                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5590                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 62751370                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2679190                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        47940825     66.94%     66.94% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57221      0.08%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4103      0.01%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        47937101     66.95%     66.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57311      0.08%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4110      0.01%     67.03% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.03% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.03% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       12938248     18.07%     85.10% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10672095     14.90%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       12936178     18.07%     85.10% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10669133     14.90%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         71612492                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1754836                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total         71603833                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1756482                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   170535238                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  168387616                       # The number of ROB writes
-system.cpu1.timesIdled                         388789                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2598367                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2951659136                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   58903233                       # Number of Instructions Simulated
-system.cpu1.committedOps                     71528245                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.816415                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.816415                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.550535                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.550535                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                84575323                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48329446                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    16299                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13042                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                274393748                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                28845956                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              191595742                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                795775                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   170496195                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168311101                       # The number of ROB writes
+system.cpu1.timesIdled                         389572                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2612002                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2951648369                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   58897215                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71519494                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.816760                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.816760                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.550430                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.550430                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84567520                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48323955                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    16256                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13038                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                274360839                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                28850413                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              191580382                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                795927                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30210                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30210                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
@@ -1652,21 +1935,21 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347069959                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347059161                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36834574                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36834571                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36411                       # number of replacements
-system.iocache.tags.tagsinuse                1.036467                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.036460                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     28                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36427                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000769                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         234012835000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.036467                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         234008190000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.036460                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ide     0.064779                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.064779                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1684,14 +1967,14 @@ system.iocache.demand_misses::realview.ide          249                       #
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29650777                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29650777                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9620896608                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9620896608                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29650777                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29650777                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29650777                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29650777                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29657377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29657377                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9617288213                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9617288213                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29657377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29657377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29657377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29657377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
@@ -1708,19 +1991,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119079.425703                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119079.425703                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119079.425703                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119079.425703                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         56505                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119105.931727                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119105.931727                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265692.963864                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 265692.963864                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119105.931727                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119105.931727                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119105.931727                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119105.931727                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         56457                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7228                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7214                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.817515                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.826033                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1734,14 +2017,14 @@ system.iocache.demand_mshr_misses::realview.ide          249
 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16701777                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16701777                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7738504756                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16701777                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16701777                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16701777                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16701777                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16708377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16708377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7734902355                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7734902355                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16708377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16708377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16708377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16708377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.999255                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1750,258 +2033,258 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67075.409639                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67075.409639                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213788.566898                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213788.566898                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67075.409639                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67075.409639                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67101.915663                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67101.915663                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213689.044810                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213689.044810                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67101.915663                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67101.915663                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67101.915663                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67101.915663                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104261                       # number of replacements
-system.l2c.tags.tagsinuse                65126.190512                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3112631                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169500                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    18.363605                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104467                       # number of replacements
+system.l2c.tags.tagsinuse                65129.957708                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3116952                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169707                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    18.366667                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48604.861621                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    48.289581                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   48713.108693                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    48.622899                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000234                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5571.225601                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2881.829872                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    43.411642                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4982.002827                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2994.569133                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.741651                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000737                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     5546.203044                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2803.513756                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    43.406508                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4962.784204                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3012.318369                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.743303                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000742                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.085010                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.043973                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.084628                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.042778                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000662                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.076019                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.045693                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993747                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65174                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           65                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3251                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         9024                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52558                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000992                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994476                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 29243192                       # Number of tag accesses
-system.l2c.tags.data_accesses                29243192                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        37242                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         8932                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             968875                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             274747                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        36318                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         7553                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             956014                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             266907                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2556588                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          704003                       # number of Writeback hits
-system.l2c.Writeback_hits::total               704003                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              44                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              49                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  93                       # number of UpgradeReq hits
+system.l2c.tags.occ_percent::cpu1.inst       0.075726                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.045964                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.993804                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           90                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65150                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_percent::1024     0.994110                       # Percentage of cache occupancy per task id
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-system.l2c.overall_accesses::cpu1.inst         965864                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         418904                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2889564                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000112                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.011244                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.024727                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001869                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010198                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.029673                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.013936                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967953                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.966667                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.967288                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.357143                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.320000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data       152830                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       143677                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu0.dtb.walker        37641                       # number of overall (read+write) accesses
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001833                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000110                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.964621                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.960825                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.962676                       # miss rate for UpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.482325                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.462572                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.472753                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000112                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001796                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.061070                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79212.686567                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   227.981189                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   360.646024                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   296.532727                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 26149.500000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7280.937500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 14538.076923                       # average SCUpgradeReq miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74500                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 76974.002402                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2010,166 +2293,166 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95507                       # number of writebacks
-system.l2c.writebacks::total                    95507                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             6                       # number of ReadReq MSHR hits
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+system.l2c.writebacks::writebacks               95556                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu1.data            68                       # number of ReadReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.data             68                       # number of demand (read+write) MSHR hits
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1421                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::total           26                       # number of SCUpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13885.538462                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.019186                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64881.384750                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 64334.531244                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63329.770854                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64165.472427                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63649.761155                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65562.364403                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 64678.034623                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 65072.025171                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63329.770854                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64165.472427                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63649.761155                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65562.364403                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 64678.034623                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -2182,57 +2465,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               68031                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68030                       # Transaction distribution
+system.membus.trans_dist::ReadReq               68075                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68074                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27609                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27609                       # Transaction distribution
-system.membus.trans_dist::Writeback            131669                       # Transaction distribution
+system.membus.trans_dist::Writeback            131718                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36196                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4639                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4633                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq             26                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4665                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138446                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138446                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4659                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138608                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138608                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           20                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       464572                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       572218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       465023                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       572669                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108820                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108820                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 681038                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 681489                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17318744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17482733                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17335192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17499181                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4631872                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4631872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22114605                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              524                       # Total snoops (count)
-system.membus.snoop_fanout::samples            347207                       # Request fanout histogram
+system.membus.pkt_size::total                22131053                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              522                       # Total snoops (count)
+system.membus.snoop_fanout::samples            347455                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  347207    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  347455    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              347207                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81506999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              347455                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81552000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               15812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1714000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1698000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1759264748                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1759525499                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1730266590                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1732085345                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38512426                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38509429                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2265,54 +2548,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2657108                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2657013                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2659236                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2659139                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27609                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27609                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           704003                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           703765                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteInvalidateReq        36196                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2844                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2841                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq            78                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2921                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296844                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296844                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3893099                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2534750                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42773                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       169663                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6640285                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124570688                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99881325                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        65944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       294780                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224812737                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           68939                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3665274                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.009944                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.099221                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp           2918                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296507                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296507                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3896051                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2534528                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        43103                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       170141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6643823                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124664384                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99866733                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        66624                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       296168                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              224893909                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           68735                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3666824                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.009939                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.099200                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3628828     99.01%     99.01% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3630378     99.01%     99.01% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                  36446      0.99%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3665274                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4674358232                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3666824                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4674174231                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           697500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           688500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        8766890883                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        8773601584                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3912089949                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3912223359                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          26359345                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          26520841                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          96778607                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          96916821                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3042                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 120ee67e1..15d0bc0bd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.904915                       # Number of seconds simulated
-sim_ticks                                2904914753500                       # Number of ticks simulated
-final_tick                               2904914753500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.904914                       # Number of seconds simulated
+sim_ticks                                2904913754500                       # Number of ticks simulated
+final_tick                               2904913754500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 754235                       # Simulator instruction rate (inst/s)
-host_op_rate                                   909375                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            19474929667                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 559844                       # Number of bytes of host memory used
-host_seconds                                   149.16                       # Real time elapsed on the host
-sim_insts                                   112502966                       # Number of instructions simulated
-sim_ops                                     135643907                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 719084                       # Simulator instruction rate (inst/s)
+host_op_rate                                   866994                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18567568294                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 616260                       # Number of bytes of host memory used
+host_seconds                                   156.45                       # Real time elapsed on the host
+sim_insts                                   112501381                       # Number of instructions simulated
+sim_ops                                     135642071                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           552740                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4263328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           553252                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4270880                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           636352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4758276                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           635584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4758596                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10212232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       552740                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       636352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1189092                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7616448                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10219848                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       553252                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       635584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1188836                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7620224                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7633972                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7637748                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             17090                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             67133                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             17098                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             67251                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              9943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             74349                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              9931                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74354                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168539                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          119007                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                168658                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          119066                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123388                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123447                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              190278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1467626                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              190454                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1470226                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           154                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              219060                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1638009                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              218796                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1638120                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3515501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         190278                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         219060                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             409338                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2621918                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3518124                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         190454                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         218796                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             409250                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2623219                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6030                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2627950                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2621918                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2629251                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2623219                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             190278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1473656                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             190454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1476256                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          154                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             219060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1638012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             218796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1638122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6143452                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        168539                       # Number of read requests accepted
-system.physmem.writeReqs                       159612                       # Number of write requests accepted
-system.physmem.readBursts                      168539                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     159612                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10780160                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6336                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9866880                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10212232                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9952308                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       99                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    5435                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                6147376                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        168658                       # Number of read requests accepted
+system.physmem.writeReqs                       159671                       # Number of write requests accepted
+system.physmem.readBursts                      168658                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     159671                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10788160                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9869632                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10219848                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9956084                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       93                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    5450                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs           4495                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9752                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9630                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10293                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9989                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18671                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9771                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9508                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10210                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9949                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18798                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               10140                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10341                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10423                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10351                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10416                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                9932                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10445                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9791                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9555                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9939                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9802                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10416                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9794                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9556                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10053                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9934                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               9961                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               9776                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9466                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9312                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               10445                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9717                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9000                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9463                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9580                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9878                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9939                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               10290                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9717                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9744                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9808                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9372                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9292                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9147                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9468                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9241                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               10223                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9791                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9126                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9458                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9597                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9810                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9882                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               10274                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9701                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9802                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9921                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9488                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9342                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9089                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2904914374000                       # Total gap between requests
+system.physmem.totGap                    2904913375000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  158967                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159086                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 155231                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    167646                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       538                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       244                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 155290                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    167768                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       542                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       243                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -164,152 +164,150 @@ system.physmem.rdQLenPdf::31                        0                       # Wh
 system.physmem.wrQLenPdf::0                       200                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       193                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                       190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       183                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     8545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8818                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     9589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     9964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    10608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    10419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6635                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6530                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7797                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     8604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     9747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    10172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    10874                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    10612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11134                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28                     8063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      380                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36                      298                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::38                      268                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      188                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       62                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54                       26                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        60664                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      340.349730                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     196.021429                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     354.920810                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21349     35.19%     35.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14624     24.11%     59.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5778      9.52%     68.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3154      5.20%     74.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2318      3.82%     77.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1542      2.54%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1044      1.72%     82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1115      1.84%     83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         9740     16.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          60664                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6204                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.148614                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      546.636063                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6203     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60740                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      340.100889                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     196.092266                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     354.277091                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21340     35.13%     35.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14718     24.23%     59.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5632      9.27%     68.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3268      5.38%     74.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2341      3.85%     77.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1599      2.63%     80.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1029      1.69%     82.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1125      1.85%     84.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9688     15.95%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60740                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6228                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.064066                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      545.583235                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6227     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6204                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6204                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.850097                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.346548                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.047003                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                14      0.23%      0.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                12      0.19%      0.42% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6228                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6228                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.761240                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.356568                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.463142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                15      0.24%      0.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                11      0.18%      0.42% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::8-11                8      0.13%      0.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              18      0.29%      0.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4939     79.61%     80.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              68      1.10%     81.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              50      0.81%     82.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             255      4.11%     86.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             123      1.98%     88.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              43      0.69%     89.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              46      0.74%     89.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              38      0.61%     90.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             127      2.05%     92.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              11      0.18%     92.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              16      0.26%     92.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.13%     93.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              34      0.55%     93.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              17      0.27%     93.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              13      0.21%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              28      0.45%     94.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              70      1.13%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              11      0.18%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               7      0.11%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              13      0.21%     96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              92      1.48%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     97.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            13      0.21%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             5      0.08%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            13      0.21%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             4      0.06%     98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             6      0.10%     98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.05%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            29      0.47%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            12      0.19%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             7      0.11%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             6      0.10%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             6      0.10%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             4      0.06%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.06%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             6      0.10%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             2      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6204                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1487388750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4645638750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    842200000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8830.38                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::12-15              13      0.21%      0.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4938     79.29%     80.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              76      1.22%     81.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              62      1.00%     82.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             242      3.89%     86.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             139      2.23%     88.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              50      0.80%     89.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              31      0.50%     89.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              38      0.61%     90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             131      2.10%     92.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              23      0.37%     92.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              11      0.18%     92.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              18      0.29%     93.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              33      0.53%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              12      0.19%     93.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.14%     94.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              29      0.47%     94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              74      1.19%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              10      0.16%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               6      0.10%     96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              12      0.19%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             105      1.69%     97.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.06%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             8      0.13%     98.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             5      0.08%     98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            14      0.22%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             5      0.08%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            10      0.16%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            36      0.58%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             6      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.08%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             5      0.08%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.05%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.08%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             3      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             2      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6228                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1469432250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4630026000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    842825000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8717.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27580.38                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27467.30                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.71                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.40                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
@@ -319,36 +317,41 @@ system.physmem.busUtil                           0.06                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.55                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     138839                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    123106                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        11.21                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     138952                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    123085                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8852370.93                       # Average gap between requests
-system.physmem.pageHitRate                      81.19                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     2756204372250                       # Time in different power states
-system.physmem.memoryStateTime::REF       97001320000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       51708967750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 232462440                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 226157400                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 126839625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 123399375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                696064200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                617760000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               498059280                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               500962320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          189734581920                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          189734581920                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0           86971409685                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1           86091461640                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          1666655279250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          1667427163500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            1944914696400                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            1944721486155                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.526666                       # Core power per rank (mW)
-system.physmem.averagePower::1             669.460155                       # Core power per rank (mW)
+system.physmem.writeRowHitRate                  79.81                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8847568.67                       # Average gap between requests
+system.physmem.pageHitRate                      81.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  232530480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126876750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 695315400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                497106720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           189734581920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            86967425385                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1666658766000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1944912602655                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.525949                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2772474399000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     97001320000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     35434263500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  226663920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123675750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 619483800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                502193520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           189734581920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            86205812760                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1667326855500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1944739267170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.466276                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2773597933750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     97001320000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34314407250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -368,6 +371,14 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -389,27 +400,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                     7245                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7245                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2256                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4989                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         7245                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7245    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7245                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6163                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11073.588350                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  8976.658748                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6262.578720                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-2047            6      0.10%      0.10% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::2048-4095         1618     26.25%     26.35% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::4096-6143            2      0.03%     26.38% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::10240-12287         3154     51.18%     77.56% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::12288-14335           39      0.63%     78.19% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::14336-16383           18      0.29%     78.48% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::20480-22527         1281     20.79%     99.27% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::22528-24575           45      0.73%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6163                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    809116500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      809116500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    809116500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3931     63.78%     63.78% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         2232     36.22%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6163                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7245                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7245                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6163                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6163                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        13408                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12308215                       # DTB read hits
-system.cpu0.dtb.read_misses                      6223                       # DTB read misses
-system.cpu0.dtb.write_hits                    9796614                       # DTB write hits
-system.cpu0.dtb.write_misses                     1025                       # DTB write misses
+system.cpu0.dtb.read_hits                    12308192                       # DTB read hits
+system.cpu0.dtb.read_misses                      6208                       # DTB read misses
+system.cpu0.dtb.write_hits                    9797532                       # DTB write hits
+system.cpu0.dtb.write_misses                     1037                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        2937                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     436                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    4667                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    4666                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   862                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   859                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      219                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12314438                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9797639                       # DTB write accesses
+system.cpu0.dtb.read_accesses                12314400                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9798569                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         22104829                       # DTB hits
-system.cpu0.dtb.misses                           7248                       # DTB misses
-system.cpu0.dtb.accesses                     22112077                       # DTB accesses
+system.cpu0.dtb.hits                         22105724                       # DTB hits
+system.cpu0.dtb.misses                           7245                       # DTB misses
+system.cpu0.dtb.accesses                     22112969                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -431,7 +483,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    58194599                       # ITB inst hits
+system.cpu0.itb.walker.walks                     3600                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3600                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          840                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2760                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3600                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3600    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3600                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2772                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 11755.230880                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9457.284814                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6774.641568                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          701     25.29%     25.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1365     49.24%     74.53% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          705     25.43%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2772                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    808810000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      808810000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    808810000                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1932     69.70%     69.70% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          840     30.30%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2772                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3600                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3600                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2772                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2772                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6372                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    58198432                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3600                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -448,38 +529,38 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                58198199                       # ITB inst accesses
-system.cpu0.itb.hits                         58194599                       # DTB hits
+system.cpu0.itb.inst_accesses                58202032                       # ITB inst accesses
+system.cpu0.itb.hits                         58198432                       # DTB hits
 system.cpu0.itb.misses                           3600                       # DTB misses
-system.cpu0.itb.accesses                     58198199                       # DTB accesses
-system.cpu0.numCycles                      2905784484                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     58202032                       # DTB accesses
+system.cpu0.numCycles                      2905779233                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   56652370                       # Number of instructions committed
-system.cpu0.committedOps                     68154355                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             60226518                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5995                       # Number of float alu accesses
-system.cpu0.num_func_calls                    4919534                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7679282                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    60226518                       # number of integer instructions
-system.cpu0.num_fp_insts                         5995                       # number of float instructions
-system.cpu0.num_int_register_reads          109459523                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41576844                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4468                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1530                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           246082665                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           26221599                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     22745945                       # number of memory refs
-system.cpu0.num_load_insts                   12471278                       # Number of load instructions
-system.cpu0.num_store_insts                  10274667                       # Number of store instructions
-system.cpu0.num_idle_cycles              2686990403.807933                       # Number of idle cycles
-system.cpu0.num_busy_cycles              218794080.192067                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.075296                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.924704                       # Percentage of idle cycles
-system.cpu0.Branches                         13013332                       # Number of branches fetched
+system.cpu0.committedInsts                   56657023                       # Number of instructions committed
+system.cpu0.committedOps                     68159505                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             60230099                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  6043                       # Number of float alu accesses
+system.cpu0.num_func_calls                    4917301                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7681441                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    60230099                       # number of integer instructions
+system.cpu0.num_fp_insts                         6043                       # number of float instructions
+system.cpu0.num_int_register_reads          109460291                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41577079                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4484                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1562                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           246097869                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           26230649                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     22747427                       # number of memory refs
+system.cpu0.num_load_insts                   12471045                       # Number of load instructions
+system.cpu0.num_store_insts                  10276382                       # Number of store instructions
+system.cpu0.num_idle_cycles              2686979283.194706                       # Number of idle cycles
+system.cpu0.num_busy_cycles              218799949.805294                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.075298                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.924702                       # Percentage of idle cycles
+system.cpu0.Branches                         13013493                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2203      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46892920     67.27%     67.28% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58660      0.08%     67.36% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46896636     67.27%     67.28% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58754      0.08%     67.36% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     67.36% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     67.36% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     67.36% # Class of executed instruction
@@ -507,23 +588,23 @@ system.cpu0.op_class::SimdFloatMisc              4258      0.01%     67.37% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.37% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.37% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.37% # Class of executed instruction
-system.cpu0.op_class::MemRead                12471278     17.89%     85.26% # Class of executed instruction
-system.cpu0.op_class::MemWrite               10274667     14.74%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                12471045     17.89%     85.26% # Class of executed instruction
+system.cpu0.op_class::MemWrite               10276382     14.74%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  69703986                       # Class of executed instruction
+system.cpu0.op_class::total                  69709278                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           822947                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.850765                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43250055                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           823459                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            52.522415                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements           822797                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.850764                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43249693                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           823309                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.531544                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        876905250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   320.083666                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   191.767099                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.625163                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.374545                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   320.252560                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   191.598204                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.625493                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.374215                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999709                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
@@ -531,128 +612,128 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1          368
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        177185510                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       177185510                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11600521                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     11519661                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23120182                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9401520                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      9429674                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18831194                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       198556                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       193555                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       392111                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       227604                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       215818                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       443422                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       235826                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       224574                       # number of StoreCondReq hits
+system.cpu0.dcache.tags.tag_accesses        177183348                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       177183348                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11600363                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     11519690                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23120053                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      9402507                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      9428435                       # number of WriteReq hits
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 system.cpu0.dcache.StoreCondReq_hits::total       460400                       # number of StoreCondReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11639                       # number of LoadLockedReq misses
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
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-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2923278500                       # number of ReadReq miss cycles
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-system.cpu0.dcache.ReadReq_miss_latency::total   5937489000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5689271509                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6091520937                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11780792446                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    135155000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    145306000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    280461000                       # number of LoadLockedReq miss cycles
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 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        75500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        75500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       151000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8612550009                       # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total  17718281446                       # number of overall miss cycles
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       238732                       # number of LoadLockedReq accesses(hits+misses)
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 system.cpu0.dcache.LoadLockedReq_accesses::total       466189                       # number of LoadLockedReq accesses(hits+misses)
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 system.cpu0.dcache.StoreCondReq_accesses::total       460402                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     21349452                       # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::cpu0.data     21604665                       # number of overall (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total     43163914                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016908                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017333                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.017120                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015487                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015745                       # miss rate for WriteReq accesses
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016912                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017319                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015749                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.221999                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.243542                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.232784                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046613                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.051170                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048836                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.222165                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.243321                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.232751                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046775                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.051003                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048839                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016273                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016619                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.016446                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018703                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019312                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.019007                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14651.776540                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14834.078102                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14743.759808                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.575527                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40381.579838                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 39434.538871                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12145.488857                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12484.405877                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12318.750824                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016613                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.016443                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018707                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019302                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.019004                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14645.339136                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14803.006832                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14724.849536                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38482.948511                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40265.954026                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39383.379963                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12196.417376                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12466.107903                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12333.856729                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        75500                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        75500                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        75500                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.665837                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25719.208451                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25259.327321                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21314.605485                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21869.904186                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 21596.414362                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.907697                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25658.188286                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25228.534250                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21311.221639                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21821.243544                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21569.945442                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs           38                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
@@ -661,113 +742,113 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs            2
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       686899                       # number of writebacks
-system.cpu0.dcache.writebacks::total           686899                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          272                       # number of ReadReq MSHR hits
+system.cpu0.dcache.writebacks::writebacks       686778                       # number of writebacks
+system.cpu0.dcache.writebacks::total           686778                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          276                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          344                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          616                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7030                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7175                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          620                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7049                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7156                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14205                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          272                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          276                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_hits::cpu1.data          344                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          616                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          272                       # number of overall MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          620                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          276                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_hits::cpu1.data          344                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          616                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       199245                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       202851                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       402096                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       147894                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       150849                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       298743                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55774                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        61059                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       116833                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4098                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4464                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8562                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.overall_mshr_hits::total          620                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       199290                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       202677                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       401967                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       147875                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       150867                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       298742                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55842                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        60970                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       116812                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4116                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4447                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8563                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       347139                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       353700                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       700839                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       402913                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       414759                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       817672                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2517898250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2600172750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5118071000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5366137441                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5759365015                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11125502456                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    677278250                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    762448500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1439726750                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     48257750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52710750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100968500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       347165                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       353544                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       700709                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       403007                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       414514                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       817521                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2517038250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2591733500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5108771750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5367510939                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5742623268                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11110134207                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    678934750                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    762190250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1441125000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     48430250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52495750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    100926000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        73500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        73500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       147000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7884035691                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8359537765                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16243573456                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8561313941                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9121986265                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  17683300206                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2688812000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3102617000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5791429000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2186315500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2243484000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4429799500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4875127500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5346101000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10221228500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016885                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017304                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017094                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015487                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015745                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7884549189                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   8334356768                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16218905957                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8563483939                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   9096547018                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  17660030957                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2685824500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3105604250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5791428750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2183466000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2246337500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4429803500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4869290500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5351941750                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10221232250                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016889                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017289                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017089                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015484                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015749                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.218539                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.238633                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228599                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017166                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019626                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018366                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.218687                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.238410                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228556                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017244                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019548                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018368                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016260                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016603                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016431                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018649                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019238                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018943                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36283.672367                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38179.669835                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37241.048179                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12143.261197                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12487.078072                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12322.946000                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11775.927282                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11807.963710                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11792.630227                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016597                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016428                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018653                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019228                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018940                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12630.027849                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12787.506723                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12709.430749                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36297.622580                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38064.144366                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37189.729623                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12158.138140                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12501.070198                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12337.131459                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11766.338678                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11804.756015                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11786.289852                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        73500                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        73500                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        73500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.244477                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23573.746883                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23146.421634                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.970710                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21945.089956                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21601.929439                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -778,16 +859,16 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1699785                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.774941                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          113901535                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1700297                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            66.989200                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1699876                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.774945                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          113899876                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1700388                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            66.984639                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      25359588250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   418.326028                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    92.448913                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.817043                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.180564                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   419.439814                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    91.335131                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.819218                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.178389                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.997607                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
@@ -795,62 +876,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          196
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        117302141                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       117302141                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     57346605                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     56554930                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      113901535                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     57346605                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     56554930                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       113901535                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     57346605                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     56554930                       # number of overall hits
-system.cpu0.icache.overall_hits::total      113901535                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       847994                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       852309                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1700303                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       847994                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       852309                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1700303                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       847994                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       852309                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1700303                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11562218249                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11735358750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  23297576999                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11562218249                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  11735358750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  23297576999                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11562218249                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  11735358750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  23297576999                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     58194599                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     57407239                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115601838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     58194599                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     57407239                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115601838                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     58194599                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     57407239                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115601838                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014572                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014847                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014708                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014572                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014847                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014708                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014572                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014847                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014708                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13634.787804                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13768.901596                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.014876                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13634.787804                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13768.901596                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13702.014876                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13634.787804                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13768.901596                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13702.014876                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        117300664                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       117300664                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     57350245                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     56549631                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      113899876                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     57350245                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     56549631                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       113899876                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     57350245                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     56549631                       # number of overall hits
+system.cpu0.icache.overall_hits::total      113899876                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       848187                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       852207                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1700394                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       848187                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       852207                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1700394                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       848187                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       852207                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1700394                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11567227499                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11741384499                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  23308611998                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11567227499                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  11741384499                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  23308611998                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11567227499                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  11741384499                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  23308611998                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     58198432                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     57401838                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115600270                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     58198432                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     57401838                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115600270                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     58198432                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     57401838                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115600270                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014574                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014846                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014709                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014574                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014846                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014709                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014574                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014846                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014709                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13637.591120                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13777.620342                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13707.771257                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13637.591120                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13777.620342                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13707.771257                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13637.591120                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13777.620342                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13707.771257                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -859,51 +940,59 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       847994                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       852309                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1700303                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       847994                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       852309                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1700303                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       847994                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       852309                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1700303                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9863343751                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10027058250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  19890402001                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9863343751                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10027058250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  19890402001                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9863343751                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10027058250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  19890402001                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       848187                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       852207                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1700394                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       848187                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       852207                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1700394                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       848187                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       852207                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1700394                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9867956501                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10033302501                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  19901259002                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9867956501                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10033302501                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  19901259002                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9867956501                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10033302501                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  19901259002                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    597905000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    597905000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    597905000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    597905000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014708                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014708                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014572                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014847                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014708                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11698.151448                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11698.151448                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11631.383891                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11764.580979                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014574                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014846                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014709                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014574                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014846                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014709                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014574                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014846                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014709                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11634.175602                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11773.316226                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11703.910389                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11634.175602                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11773.316226                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11703.910389                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11634.175602                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11773.316226                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11703.910389                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -925,27 +1014,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                     6287                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6287                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1877                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4409                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples         6286                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6286    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6286                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5205                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10664.029395                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  8432.528945                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7016.441417                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         4168     80.08%     80.08% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767         1031     19.81%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-81919            3      0.06%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-98303            2      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-180223            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         5205                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   2238481496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.553158                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.497166                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1000247500     44.68%     44.68% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1238233996     55.32%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   2238481496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3350     64.37%     64.37% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1854     35.63%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5204                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6287                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6287                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5204                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5204                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        11491                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12222550                       # DTB read hits
-system.cpu1.dtb.read_misses                      5478                       # DTB read misses
-system.cpu1.dtb.write_hits                    9817405                       # DTB write hits
-system.cpu1.dtb.write_misses                      801                       # DTB write misses
+system.cpu1.dtb.read_hits                    12222323                       # DTB read hits
+system.cpu1.dtb.read_misses                      5479                       # DTB read misses
+system.cpu1.dtb.write_hits                    9816234                       # DTB write hits
+system.cpu1.dtb.write_misses                      808                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2935                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    4101                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    4100                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   936                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   935                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      226                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12228028                       # DTB read accesses
-system.cpu1.dtb.write_accesses                9818206                       # DTB write accesses
+system.cpu1.dtb.read_accesses                12227802                       # DTB read accesses
+system.cpu1.dtb.write_accesses                9817042                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         22039955                       # DTB hits
-system.cpu1.dtb.misses                           6279                       # DTB misses
-system.cpu1.dtb.accesses                     22046234                       # DTB accesses
+system.cpu1.dtb.hits                         22038557                       # DTB hits
+system.cpu1.dtb.misses                           6287                       # DTB misses
+system.cpu1.dtb.accesses                     22044844                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -967,8 +1098,40 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    57407239                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3155                       # ITB inst misses
+system.cpu1.itb.walker.walks                     3158                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3158                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          699                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2459                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         3158                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3158    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3158                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2331                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10972.758473                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  8658.635701                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6654.132285                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::2048-4095          701     30.07%     30.07% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143            5      0.21%     30.29% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287         1063     45.60%     75.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335           47      2.02%     77.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383            1      0.04%     77.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-22527          442     18.96%     96.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575           72      3.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2331                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1000205500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000205500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000205500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1632     70.01%     70.01% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          699     29.99%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2331                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3158                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3158                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2331                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2331                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         5489                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    57401838                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3158                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -977,45 +1140,45 @@ system.cpu1.itb.flush_tlb                        2935                       # Nu
 system.cpu1.itb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2356                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2358                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                57410394                       # ITB inst accesses
-system.cpu1.itb.hits                         57407239                       # DTB hits
-system.cpu1.itb.misses                           3155                       # DTB misses
-system.cpu1.itb.accesses                     57410394                       # DTB accesses
-system.cpu1.numCycles                      2904045023                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                57404996                       # ITB inst accesses
+system.cpu1.itb.hits                         57401838                       # DTB hits
+system.cpu1.itb.misses                           3158                       # DTB misses
+system.cpu1.itb.accesses                     57404996                       # DTB accesses
+system.cpu1.numCycles                      2904048276                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   55850596                       # Number of instructions committed
-system.cpu1.committedOps                     67489552                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             59717976                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5231                       # Number of float alu accesses
-system.cpu1.num_func_calls                    4978644                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      7556287                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    59717976                       # number of integer instructions
-system.cpu1.num_fp_insts                         5231                       # number of float instructions
-system.cpu1.num_int_register_reads          108697708                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          41105654                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4046                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1186                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           243864682                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           25692319                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     22680019                       # number of memory refs
-system.cpu1.num_load_insts                   12382292                       # Number of load instructions
-system.cpu1.num_store_insts                  10297727                       # Number of store instructions
-system.cpu1.num_idle_cycles              2693854199.172201                       # Number of idle cycles
-system.cpu1.num_busy_cycles              210190823.827799                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.072379                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.927621                       # Percentage of idle cycles
-system.cpu1.Branches                         12914403                       # Number of branches fetched
+system.cpu1.committedInsts                   55844358                       # Number of instructions committed
+system.cpu1.committedOps                     67482566                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             59712832                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5183                       # Number of float alu accesses
+system.cpu1.num_func_calls                    4980648                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      7553958                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    59712832                       # number of integer instructions
+system.cpu1.num_fp_insts                         5183                       # number of float instructions
+system.cpu1.num_int_register_reads          108693830                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          41104260                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4030                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1154                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           243842957                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           25682716                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     22677996                       # number of memory refs
+system.cpu1.num_load_insts                   12382220                       # Number of load instructions
+system.cpu1.num_store_insts                  10295776                       # Number of store instructions
+system.cpu1.num_idle_cycles              2693878470.584054                       # Number of idle cycles
+system.cpu1.num_busy_cycles              210169805.415946                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.072371                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.927629                       # Percentage of idle cycles
+system.cpu1.Branches                         12913817                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                  134      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 46321486     67.07%     67.07% # Class of executed instruction
-system.cpu1.op_class::IntMult                   56040      0.08%     67.15% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 46316521     67.07%     67.07% # Class of executed instruction
+system.cpu1.op_class::IntMult                   55928      0.08%     67.15% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     67.15% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     67.15% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     67.15% # Class of executed instruction
@@ -1043,11 +1206,11 @@ system.cpu1.op_class::SimdFloatMisc              4215      0.01%     67.16% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.16% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.16% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.16% # Class of executed instruction
-system.cpu1.op_class::MemRead                12382292     17.93%     85.09% # Class of executed instruction
-system.cpu1.op_class::MemWrite               10297727     14.91%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                12382220     17.93%     85.09% # Class of executed instruction
+system.cpu1.op_class::MemWrite               10295776     14.91%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69061894                       # Class of executed instruction
+system.cpu1.op_class::total                  69054794                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
@@ -1145,21 +1308,21 @@ system.iobus.reqLayer25.occupancy            30680000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           347067538                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           347068533                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36804503                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36804505                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.084296                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084285                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         309429812000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.084296                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         309430209000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.084285                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ide     0.067768                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.067768                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1177,8 +1340,8 @@ system.iocache.overall_misses::realview.ide          234                       #
 system.iocache.overall_misses::total              234                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ide     28034377                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     28034377                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9591408658                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9591408658                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9589202651                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9589202651                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ide     28034377                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     28034377                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ide     28034377                       # number of overall miss cycles
@@ -1201,17 +1364,17 @@ system.iocache.overall_miss_rate::realview.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119805.029915                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264719.596152                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264719.596152                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 119805.029915                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 119805.029915                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         55572                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs         55434                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7176                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7152                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.744147                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.750839                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1227,8 +1390,8 @@ system.iocache.overall_mshr_misses::realview.ide          234
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ide     15865377                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     15865377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7707754664                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7707754664                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7705544661                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7705544661                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ide     15865377                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     15865377                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ide     15865377                       # number of overall MSHR miss cycles
@@ -1243,253 +1406,253 @@ system.iocache.overall_mshr_miss_rate::realview.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212780.329726                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212780.329726                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212719.320368                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212719.320368                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    89435                       # number of replacements
-system.l2c.tags.tagsinuse                64927.975067                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2767630                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   154676                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    17.893080                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    89554                       # number of replacements
+system.l2c.tags.tagsinuse                64927.556568                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2767374                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   154795                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    17.877670                       # Average number of references to valid blocks.
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-system.l2c.tags.occ_blocks::writebacks   50554.064375                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu0.data     2070.927660                       # Average occupied blocks per requestor
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-system.l2c.Writeback_accesses::total           686899                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1362                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1382                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.UpgradeReq_accesses::total            2744                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       146532                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.dtb.walker         6460                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.dtb.walker         6460                       # number of overall (read+write) accesses
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 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000155                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000289                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.009520                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::total          0.013434                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991189                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992041                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992035                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.991618                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu0.data     0.423860                       # miss rate for ReadExReq accesses
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 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000155                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000289                       # miss rate for demand accesses
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 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000155                       # miss rate for overall accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        74500                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72746.655518                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 76545.323221                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   186.352298                       # average UpgradeReq miss latency
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 system.l2c.UpgradeReq_avg_miss_latency::total   170.701948                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        72500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        72500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        72500                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        74500                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        74500                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 72746.655518                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70080.518220                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 69593.422321                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70133.163519                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 70016.246850                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1498,151 +1661,151 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82817                       # number of writebacks
-system.l2c.writebacks::total                    82817                       # number of writebacks
+system.l2c.writebacks::writebacks               82876                       # number of writebacks
+system.l2c.writebacks::total                    82876                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         8073                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         5538                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         8081                       # number of ReadReq MSHR misses
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 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         9945                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6604                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1350                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1371                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         9933                       # number of ReadReq MSHR misses
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 system.l2c.UpgradeReq_mshr_misses::total         2721                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        62109                       # number of ReadExReq MSHR misses
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 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57370.855040                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60355.215939                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57217.681950                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60635.205879                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56507.069783                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57254.032801                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -1655,57 +1818,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               70575                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70575                       # Transaction distribution
+system.membus.trans_dist::ReadReq               70570                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70570                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27613                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27613                       # Transaction distribution
-system.membus.trans_dist::Writeback            119007                       # Transaction distribution
+system.membus.trans_dist::Writeback            119066                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4495                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4497                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129060                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129060                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129184                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129184                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       437896                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       545560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438193                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       545857                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 654447                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 654744                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15529084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     15692509                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15540476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     15703901                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20327965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20339357                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              498                       # Total snoops (count)
-system.membus.snoop_fanout::samples            319191                       # Request fanout histogram
+system.membus.snoop_fanout::samples            319369                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  319191    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  319369    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              319191                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87172500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              319369                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87174000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1735000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1737000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1662315000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1663053000                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1640286255                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1641418005                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38333497                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38335495                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -1738,54 +1901,54 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            2303097                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2303082                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            2303048                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2303033                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27613                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27613                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           686899                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           686778                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2744                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2746                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295999                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295999                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3418625                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2457116                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18180                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34622                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5928543                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108853880                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96862117                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24836                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        46784                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              205787617                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           53694                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3284793                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.011099                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.104766                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadExReq           295998                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295998                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3418807                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2456695                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18188                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34627                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5928317                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108859704                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96844773                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24844                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        46792                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              205776113                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           53699                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3284622                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.011100                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.104768                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                3248335     98.89%     98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                3248164     98.89%     98.89% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                  36458      1.11%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3284793                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4419462750                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3284622                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4418893499                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           985500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        7665779999                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        7666187498                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3782690745                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3782041495                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11971000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11977000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          22951201                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          22953702                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index ecc4cd446..3b8bb2577 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,162 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.349389                       # Number of seconds simulated
-sim_ticks                                47349388766500                       # Number of ticks simulated
-final_tick                               47349388766500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.355615                       # Number of seconds simulated
+sim_ticks                                47355615197500                       # Number of ticks simulated
+final_tick                               47355615197500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 148460                       # Simulator instruction rate (inst/s)
-host_op_rate                                   174619                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7799944718                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 883812                       # Number of bytes of host memory used
-host_seconds                                  6070.48                       # Real time elapsed on the host
-sim_insts                                   901223526                       # Number of instructions simulated
-sim_ops                                    1060022042                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 178863                       # Simulator instruction rate (inst/s)
+host_op_rate                                   210359                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9462962325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 759628                       # Number of bytes of host memory used
+host_seconds                                  5004.31                       # Real time elapsed on the host
+sim_insts                                   895084962                       # Number of instructions simulated
+sim_ops                                    1052703090                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       126592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       108352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst         12219800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     55224576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       171840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       160768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst         11630176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     36221056                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        451968                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116315128                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4075008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       659840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4734848                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     84862912                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       106496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        83264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst         18925144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     17557952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       158592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       147776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst         13767904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     16399360                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        427968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             67574456                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      8104128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3589696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11693824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78266240                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.inst         20812                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.inst             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          84883728                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1693                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            190956                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       862884                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2685                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2512                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst            181736                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       565954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7062                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1817460                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1325983                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78287056                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1664                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1301                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            295727                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       274343                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2478                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2309                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst            215138                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       256240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6687                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1055887                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1222910                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.inst             2602                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.inst                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1328586                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2674                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2288                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              258077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      1166321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              245625                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       764974                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2456529                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          86063                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          13936                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              99998                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1792270                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst                440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1225513                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              399639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       370768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              290734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       346302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1426958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         171133                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          75803                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             246936                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1652734                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst                439                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.inst                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1792710                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1792270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2288                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             258517                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      1166321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             245625                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       764974                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4249239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1817460                       # Number of read requests accepted
-system.physmem.writeReqs                      1459105                       # Number of write requests accepted
-system.physmem.readBursts                     1817460                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1459105                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                116259968                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     57472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  92884608                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 116315128                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               93236944                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      898                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7766                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          92270                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              109521                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              125500                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              109858                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118807                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              114750                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              133958                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              108183                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              109296                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              104951                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              157608                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              96466                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             111139                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             103753                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             116262                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              95073                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             101437                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               88391                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               94888                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               89089                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               94540                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               92096                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              104028                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               87215                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               89925                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               85891                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               90043                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              85085                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              94536                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              86659                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              94890                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              85144                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              88902                       # Per bank write bursts
+system.physmem.bw_write::total                1653174                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1652734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             400078                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       370768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             290734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       346302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3080131                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1055887                       # Number of read requests accepted
+system.physmem.writeReqs                      1888199                       # Number of write requests accepted
+system.physmem.readBursts                     1055887                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1888199                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 67557888                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18880                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 120408192                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  67574456                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              120698960                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      295                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6789                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         114993                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               58784                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               68771                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               59130                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               67531                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               66855                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               75133                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               65903                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               67407                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               54196                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              110706                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              54461                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              64104                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              57097                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              66166                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              60751                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              58597                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              116651                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              125865                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              118664                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              124773                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              121001                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              125597                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              113710                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              116980                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              110183                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              114411                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             109841                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             116847                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             116927                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             118874                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             112844                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             118210                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47349386828500                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47355613259000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1817418                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1055845                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1456502                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    724796                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    275224                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    218778                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    130576                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    121480                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     92297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     78276                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     67824                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     54542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     29215                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     6539                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     4680                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     3658                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     2988                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     2241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1701                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      695                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      500                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      212                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1885596                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    695873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    103690                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     49130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     41556                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::10                     3052                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::14                      532                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::17                      225                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::19                       80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -180,156 +180,180 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    20715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    26374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    37146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    48711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    55470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    67793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    75025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    82665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    93812                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26                   101866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   103500                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   107192                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30                   103030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   105997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   102597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                    17377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                    13177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     9215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     5577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      557                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49                      457                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::51                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      234                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::43                     1337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      455                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      191                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       894898                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      233.707153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     136.846498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     284.283402                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         463489     51.79%     51.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       185877     20.77%     72.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        67737      7.57%     80.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36988      4.13%     84.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        29329      3.28%     87.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        22133      2.47%     90.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        15835      1.77%     91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        13649      1.53%     93.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        59861      6.69%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         894898                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         77790                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.351999                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      144.403085                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          77788    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::56                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       12                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1046123                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      179.678328                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     108.587927                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     250.922876                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         666099     63.67%     63.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       200536     19.17%     82.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        50293      4.81%     87.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        24222      2.32%     89.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        17786      1.70%     91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12328      1.18%     92.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8853      0.85%     93.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7558      0.72%     94.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        58448      5.59%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1046123                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         79224                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        13.323930                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      140.057237                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          79222    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           77790                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         77790                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.656922                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.550932                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.537959                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           73893     94.99%     94.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            1079      1.39%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             616      0.79%     97.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             255      0.33%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             611      0.79%     98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             159      0.20%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             204      0.26%     98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             127      0.16%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             198      0.25%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              57      0.07%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            225      0.29%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            47      0.06%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            57      0.07%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            49      0.06%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135           102      0.13%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            22      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            26      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            10      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            13      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             6      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             9      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           77790                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   101322311265                       # Total ticks spent queuing
-system.physmem.totMemAccLat              135382848765                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9082810000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       55776.96                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           79224                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         79224                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.747576                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.323530                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.901705                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           65925     83.21%     83.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            5556      7.01%     90.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            2071      2.61%     92.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47            1166      1.47%     94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55            1087      1.37%     95.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             456      0.58%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             393      0.50%     96.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             290      0.37%     97.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             329      0.42%     97.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             179      0.23%     97.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            294      0.37%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111           101      0.13%     98.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119           139      0.18%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127           103      0.13%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           155      0.20%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            83      0.10%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            89      0.11%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            58      0.07%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            57      0.07%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            65      0.08%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            66      0.08%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191            81      0.10%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199            58      0.07%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207            58      0.07%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215            69      0.09%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223            72      0.09%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231            57      0.07%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239            44      0.06%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247            31      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255            21      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263            22      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271            15      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             7      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::280-287             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-295             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::296-303             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-311             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::312-319             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-327             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::328-335             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-343             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::344-351             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-359             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::360-367             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-375             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::376-383             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-391             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::456-463             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-503             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           79224                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    39480003252                       # Total ticks spent queuing
+system.physmem.totMemAccLat               59272353252                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5277960000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       37400.82                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  74526.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.46                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.96                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.46                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.97                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  56150.82                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.54                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.40                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1479200                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    893785                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  61.58                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14450922.48                       # Average gap between requests
-system.physmem.pageHitRate                      72.61                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     45452153624500                       # Time in different power states
-system.physmem.memoryStateTime::REF      1581100040000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      316134376000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3577346640                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3188082240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1951925250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1739529000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               7253009400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               6916111800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              4796314560                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              4608252000                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3092631678240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3092631678240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1196963299980                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1185023558430                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          27359663548500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          27370137006000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            31666837122570                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            31664244217710                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.790877                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.736116                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     797783                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1093063                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.10                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16084996.59                       # Average gap between requests
+system.physmem.pageHitRate                      64.38                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4126437000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2251528125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4130209200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               6241801680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3093038526240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1193820708150                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27366157608000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31669766818395                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.764772                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45525574397500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1581308040000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    248732168750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 3782252880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2063729250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4103353800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5949527760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3093038526240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1183965961905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27374802122250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31667705474085                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.721243                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45539970549502                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1581308040000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    234336016748                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          584                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1324                       # Number of bytes read from this memory
@@ -354,16 +378,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              127854962                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         91169153                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5795491                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            97464931                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               70565780                       # Number of BTB hits
+system.cpu0.branchPred.lookups              131272413                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         92904470                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6038757                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98925935                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               71271707                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.401200                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               14662444                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            979053                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.045523                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15434878                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1076370                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -385,27 +417,75 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   271399                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               271399                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8182                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        72706                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       271399                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         271399    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       271399                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        80888                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        77350     95.63%     95.63% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         2802      3.46%     99.09% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          370      0.46%     99.55% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          250      0.31%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           18      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           21      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           23      0.03%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           10      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           23      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        80888                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    644436704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      644436704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    644436704                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        72706     89.88%     89.88% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         8182     10.12%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        80888                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       271399                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       271399                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        80888                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        80888                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       352287                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    80634882                       # DTB read hits
-system.cpu0.dtb.read_misses                    217470                       # DTB read misses
-system.cpu0.dtb.write_hits                   71942682                       # DTB write hits
-system.cpu0.dtb.write_misses                    47848                       # DTB write misses
+system.cpu0.dtb.read_hits                    83830376                       # DTB read hits
+system.cpu0.dtb.read_misses                    224800                       # DTB read misses
+system.cpu0.dtb.write_hits                   74836136                       # DTB write hits
+system.cpu0.dtb.write_misses                    46599                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   34852                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1874                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  8493                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              42371                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   31986                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     2076                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8713                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11561                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                80852352                       # DTB read accesses
-system.cpu0.dtb.write_accesses               71990530                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10302                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                84055176                       # DTB read accesses
+system.cpu0.dtb.write_accesses               74882735                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        152577564                       # DTB hits
-system.cpu0.dtb.misses                         265318                       # DTB misses
-system.cpu0.dtb.accesses                    152842882                       # DTB accesses
+system.cpu0.dtb.hits                        158666512                       # DTB hits
+system.cpu0.dtb.misses                         271399                       # DTB misses
+system.cpu0.dtb.accesses                    158937911                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -427,145 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   228743332                       # ITB inst hits
-system.cpu0.itb.inst_misses                     63317                       # ITB inst misses
+system.cpu0.itb.walker.walks                    59516                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                59516                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          630                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51758                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        59516                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          59516    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        59516                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52388                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        48500     92.58%     92.58% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         3085      5.89%     98.47% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          277      0.53%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          436      0.83%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           18      0.03%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           31      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52388                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    643764704                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      643764704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    643764704                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        51758     98.80%     98.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          630      1.20%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52388                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        59516                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        59516                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52388                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52388                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       111904                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   234493726                       # ITB inst hits
+system.cpu0.itb.inst_misses                     59516                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24510                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              42371                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   22765                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   202277                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   197741                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               228806649                       # ITB inst accesses
-system.cpu0.itb.hits                        228743332                       # DTB hits
-system.cpu0.itb.misses                          63317                       # DTB misses
-system.cpu0.itb.accesses                    228806649                       # DTB accesses
-system.cpu0.numCycles                       867293351                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               234553242                       # ITB inst accesses
+system.cpu0.itb.hits                        234493726                       # DTB hits
+system.cpu0.itb.misses                          59516                       # DTB misses
+system.cpu0.itb.accesses                    234553242                       # DTB accesses
+system.cpu0.numCycles                       936626399                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  417325536                       # Number of instructions committed
-system.cpu0.committedOps                    490736323                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     44793539                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4342                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93832115526                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.078218                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.481182                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  433367687                       # Number of instructions committed
+system.cpu0.committedOps                    509515701                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     43981618                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     3754                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93775213530                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.161274                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.462690                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4790                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      682045150                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      185248201                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5375859                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          504.387778                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          144555742                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5376371                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            26.887233                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       4951320000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   504.387778                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.985132                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.985132                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   12643                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      703108983                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      233517416                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5387052                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          501.034252                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          150576282                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5387564                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.948862                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       4951668000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   501.034252                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.978583                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.978583                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        308078040                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       308078040                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst     74032777                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       74032777                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst     66638302                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      66638302                       # number of WriteReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst       115191                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       115191                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst      1688442                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1688442                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst      1614699                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1614699                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst    140671079                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       140671079                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst    140671079                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      140671079                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst      3863790                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3863790                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst      2319255                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2319255                       # number of WriteReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst       742685                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       742685                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst       105957                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       105957                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst       178436                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       178436                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst      6183045                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6183045                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst      6183045                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6183045                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst  54382834533                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  54382834533                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  36195221997                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36195221997                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst  21037893950                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  21037893950                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst   1466052740                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   1466052740                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst   3737583856                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3737583856                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst      3062000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3062000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  90578056530                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  90578056530                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  90578056530                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  90578056530                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst     77896567                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     77896567                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst     68957557                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     68957557                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst       857876                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total       857876                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst      1794399                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1794399                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst      1793135                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1793135                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst    146854124                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    146854124                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst    146854124                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    146854124                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.049602                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.049602                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.033633                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.033633                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst     0.865725                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.865725                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.059049                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059049                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.099511                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099511                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.042103                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.042103                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.042103                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.042103                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        320066517                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       320066517                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst     77114778                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       77114778                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst     69351990                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69351990                       # number of WriteReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst       251432                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       251432                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst      1745310                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1745310                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.inst      1668274                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1668274                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst    146466768                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       146466768                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst    146466768                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      146466768                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst      3852692                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3852692                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst      2255601                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2255601                       # number of WriteReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst       766100                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       766100                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst       104059                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       104059                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst       180014                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       180014                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst      6108293                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6108293                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst      6108293                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6108293                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst  54452724607                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54452724607                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  41906959422                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  41906959422                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst  27296991314                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27296991314                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst   1502404735                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   1502404735                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst   3769027814                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   3769027814                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst      2840500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2840500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  96359684029                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  96359684029                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  96359684029                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  96359684029                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst     80967470                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     80967470                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst     71607591                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     71607591                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst      1017532                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1017532                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst      1849369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1849369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst      1848288                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1848288                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst    152575061                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    152575061                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst    152575061                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    152575061                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.047583                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.047583                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.031499                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.031499                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst     0.752900                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.752900                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.056267                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056267                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.097395                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097395                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.040035                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.040035                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.040035                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.040035                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14649.425409                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14649.425409                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -574,88 +694,88 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3741617                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3741617                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst       374932                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       374932                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       967778                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       967778                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst           26                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total           26                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           53                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total           53                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst           76                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           76                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst      1342710                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1342710                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst      1342710                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1342710                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst      3488858                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3488858                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst      1351477                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1351477                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst       742659                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       742659                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst       105904                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       105904                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst       178360                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       178360                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst      4840335                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4840335                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst      4840335                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4840335                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst  42020078260                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42020078260                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst  19120911908                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  19120911908                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  19537847050                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  19537847050                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst   1252614238                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1252614238                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst   3369767592                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3369767592                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst      2341000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2341000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst  61140990168                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61140990168                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst  61140990168                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  61140990168                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2949307890                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2949307890                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   3070097397                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3070097397                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst   6019405287                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6019405287                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.044788                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.044788                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.019599                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019599                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.865695                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.865695                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.059019                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059019                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.099468                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099468                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.032960                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032960                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.032960                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032960                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      3733142                       # number of writebacks
+system.cpu0.dcache.writebacks::total          3733142                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst       361487                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       361487                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       935411                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       935411                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst          100                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total          100                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           34                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total           34                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst           67                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           67                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst      1296898                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1296898                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst      1296898                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1296898                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst      3491205                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3491205                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst      1320190                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1320190                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst       766000                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       766000                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst       104025                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       104025                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst       179947                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       179947                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst      4811395                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4811395                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst      4811395                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4811395                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst  42113152704                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42113152704                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst  22270249828                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22270249828                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  25755951436                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  25755951436                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst   1293404753                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1293404753                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst   3399276642                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3399276642                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst      2291500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2291500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst  64383402532                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  64383402532                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst  64383402532                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  64383402532                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5824362996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5824362996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   5586865743                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5586865743                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst  11411228739                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11411228739                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.043119                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.043119                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.018436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.752802                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.752802                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.056249                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056249                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.097359                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097359                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.031535                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.031535                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.031535                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031535                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -663,58 +783,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          8781546                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.937582                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          219752565                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          8782058                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            25.022901                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      16633914000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.937582                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999878                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999878                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          9463678                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.932976                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          224826074                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9464190                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            23.755448                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      21621868750                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932976                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999869                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        465851331                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       465851331                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    219752565                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      219752565                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    219752565                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       219752565                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    219752565                       # number of overall hits
-system.cpu0.icache.overall_hits::total      219752565                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8782067                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      8782067                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8782067                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       8782067                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8782067                       # number of overall misses
-system.cpu0.icache.overall_misses::total      8782067                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  75181971221                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  75181971221                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  75181971221                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  75181971221                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  75181971221                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  75181971221                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    228534632                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    228534632                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    228534632                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    228534632                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    228534632                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    228534632                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038428                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.038428                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038428                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.038428                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038428                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.038428                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8560.851474                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8560.851474                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8560.851474                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8560.851474                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8560.851474                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8560.851474                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        478044747                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       478044747                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    224826074                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      224826074                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    224826074                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       224826074                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    224826074                       # number of overall hits
+system.cpu0.icache.overall_hits::total      224826074                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9464200                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9464200                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9464200                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9464200                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9464200                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9464200                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93878607487                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  93878607487                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  93878607487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  93878607487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  93878607487                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  93878607487                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    234290274                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    234290274                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    234290274                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    234290274                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    234290274                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    234290274                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040395                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.040395                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040395                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.040395                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040395                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.040395                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9919.338928                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9919.338928                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9919.338928                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9919.338928                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9919.338928                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9919.338928                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -723,353 +843,346 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8782067                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      8782067                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8782067                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      8782067                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8782067                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      8782067                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  61997855741                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  61997855741                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  61997855741                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  61997855741                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  61997855741                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  61997855741                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9464200                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9464200                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9464200                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9464200                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9464200                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9464200                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  79648587963                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  79648587963                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  79648587963                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  79648587963                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  79648587963                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  79648587963                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4713229500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4713229500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4713229500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   4713229500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038428                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.038428                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038428                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.038428                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7059.597216                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7059.597216                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7059.597216                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7059.597216                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040395                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040395                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040395                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.040395                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040395                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.040395                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8415.776079                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8415.776079                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8415.776079                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  8415.776079                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8415.776079                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  8415.776079                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     84003023                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      4398912                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     74572645                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      1090360                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       154166                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      3786940                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      6742713                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         4037603                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16229.874548                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          15269588                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         4053811                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.766724                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     14918796500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  3465.639505                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    40.958286                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    27.625357                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  2577.016988                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.211526                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002500                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001686                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.157289                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.617592                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.990593                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022        10250                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024         5866                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0          116                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1         1048                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         4016                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         3415                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1655                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           22                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           23                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          525                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2441                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1975                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          887                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.625610                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.358032                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       311163440                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      311163440                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       470272                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       147367                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst     11429450                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total      12047089                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3741617                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3741617                       # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst       295044                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total       295044                       # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst        86443                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        86443                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst        36465                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36465                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.inst       911350                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       911350                       # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       470272                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       147367                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst     12340800                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       12958439                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       470272                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       147367                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst     12340800                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      12958439                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13865                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10088                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst       947171                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total       971124                       # number of ReadReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst       446451                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::total       446451                       # number of WriteInvalidateReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst       123568                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       123568                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst       141888                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       141888                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.inst       231493                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       231493                       # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13865                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10088                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst      1178664                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1202617                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13865                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10088                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst      1178664                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1202617                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    459903131                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    354751936                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  28411115925                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total  29225770992                       # number of ReadReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst  15916059245                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total  15916059245                       # number of WriteInvalidateReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst   2454108805                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2454108805                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst   2872469472                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2872469472                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst      2284000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2284000                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst   8822124839                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   8822124839                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    459903131                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    354751936                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  37233240764                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  38047895831                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    459903131                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    354751936                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  37233240764                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  38047895831                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       484137                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       157455                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst     12376621                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total     13018213                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3741617                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3741617                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst       741495                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::total       741495                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst       210011                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       210011                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst       178353                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       178353                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst      1142843                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1142843                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       484137                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       157455                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst     13519464                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     14161056                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       484137                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       157455                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst     13519464                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     14161056                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.076529                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.074597                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst     0.602096                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.602096                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.588388                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.588388                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.795546                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.795546                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.num_hwpf_issued     11128158                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified     11136239                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         7035                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage      1270201                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2736028                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16197.540138                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          15248127                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2752162                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.540418                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      5578143500                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks  4129.920995                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    42.114006                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    24.266127                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  9438.642805                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  2562.596205                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.252070                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002570                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001481                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.576089                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.156408                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.988619                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         2519                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           71                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13544                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          133                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          367                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         1060                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          959                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           25                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           35                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1002                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2423                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4868                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5129                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.153748                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004333                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.826660                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       319708402                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      319708402                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       463342                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       138212                       # number of ReadReq hits
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+system.cpu0.l2cache.ReadReq_hits::total      12212111                       # number of ReadReq hits
+system.cpu0.l2cache.Writeback_hits::writebacks      3733141                       # number of Writeback hits
+system.cpu0.l2cache.Writeback_hits::total      3733141                       # number of Writeback hits
+system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst       193768                       # number of WriteInvalidateReq hits
+system.cpu0.l2cache.WriteInvalidateReq_hits::total       193768                       # number of WriteInvalidateReq hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst        68627                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total        68627                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst        33597                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total        33597                       # number of SCUpgradeReq hits
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+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       138212                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst     12466328                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       138212                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst     12466328                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      13067882                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11843                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8238                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst      1448613                       # number of ReadReq misses
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+system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst       126856                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       126856                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst       146340                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.inst      1719289                       # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8238                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst      1719289                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1739370                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    383176229                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    279750987                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  44923505132                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total  45586432348                       # number of ReadReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst    223595615                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total    223595615                       # number of WriteInvalidateReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst   2548596996                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2548596996                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst   2948593769                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2948593769                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst      2234000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2234000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst  12372799630                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  12372799630                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    383176229                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    279750987                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  57296304762                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  57959231978                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    383176229                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    279750987                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  57296304762                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  57959231978                       # number of overall miss cycles
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+system.cpu0.l2cache.Writeback_accesses::writebacks      3733141                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      3733141                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst       764525                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::total       764525                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::total       195483                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst       179937                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       179937                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst           10                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadExReq_accesses::total      1126447                       # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       146450                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       475185                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       146450                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst     14185617                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     14807252                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.024923                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.056251                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.110927                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.107354                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst     0.746551                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.746551                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst     0.648936                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.648936                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst     0.813285                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.813285                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.202559                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.202559                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.087183                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.084924                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.028639                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.064069                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.087183                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.084924                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33170.077966                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35165.735131                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29995.762038                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30094.788093                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35650.181644                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 35650.181644                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 19860.391080                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19860.391080                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20244.625846                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.625846                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 326285.714286                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326285.714286                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 38109.682967                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 38109.682967                       # average ReadExReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33170.077966                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35165.735131                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31589.359448                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 31637.583562                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33170.077966                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35165.735131                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31589.359448                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 31637.583562                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs       196093                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst     0.240292                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240292                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.024923                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.056251                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.121199                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.117467                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.024923                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.056251                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.121199                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.117467                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31011.391677                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31038.754395                       # average ReadReq miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst   391.752734                       # average WriteInvalidateReq miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total   391.752734                       # average WriteInvalidateReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20090.472630                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20090.472630                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20148.925577                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20148.925577                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst       223400                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       223400                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 45710.737672                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45710.737672                       # average ReadExReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32354.659208                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33958.604880                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33325.580959                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32354.659208                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33958.604880                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33325.580959                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           82                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            2541                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    77.171586                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           82                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1602519                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1602519                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            5                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        79969                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total        79976                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst       383227                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total       383227                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         9177                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         9177                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            5                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        89146                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        89153                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            2                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            5                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        89146                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        89153                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13863                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10083                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       867202                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total       891148                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      3786879                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total      3786879                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst        63224                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total        63224                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst       123568                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       123568                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst       141888                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       141888                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst       222316                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       222316                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13863                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10083                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst      1089518                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1113464                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13863                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10083                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst      1089518                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      3786879                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      4900343                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    362187797                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    283585554                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  20498207280                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  21143980631                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 168439656794                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst   1410635970                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total   1410635970                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst   2082130886                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2082130886                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst   1980278880                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   1980278880                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst      1885000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1885000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   6408519883                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   6408519883                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    362187797                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    283585554                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  26906727163                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  27552500514                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    362187797                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    283585554                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  26906727163                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 195992157308                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6920870357                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6920870357                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   2922560102                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2922560102                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   9843430459                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9843430459                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.070068                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.068454                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.writebacks::writebacks      1399370                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1399370                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         3403                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total         3404                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst          156                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total          156                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst         9658                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         9658                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        13061                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        13062                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        13061                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        13062                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11843                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8237                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst      1445210                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total      1465290                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      1036981                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total      1036981                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst       570601                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       570601                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst       126856                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       126856                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst       146340                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       146340                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst       261018                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       261018                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11843                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8237                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst      1706228                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1726308                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11843                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8237                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst      1706228                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      1036981                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2763289                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst  34355781249                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  34877337999                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  47311809533                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  47311809533                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst  20034543782                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  20034543782                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst   2151275072                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2151275072                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst   1993779824                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   1993779824                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst      1835000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1835000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst   9532664011                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   9532664011                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  43888445260                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  44410002010                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    299835249                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    221721501                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  43888445260                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  47311809533                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  91721811543                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   9672004742                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9672004742                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst   5338553005                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5338553005                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst  15010557747                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  15010557747                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.110666                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.107106                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.085266                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.085266                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.588388                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.588388                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.795546                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.795546                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.746347                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.746347                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst     0.648936                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.648936                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.813285                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.813285                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.194529                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.194529                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.080589                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.078629                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.028634                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064037                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.080589                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst     0.231718                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.231718                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.120279                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.116585                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.024923                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.056244                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.120279                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.346044                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.186617                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst       183500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       183500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1077,68 +1190,77 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      17406363                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     13329872                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        19688                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        19687                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3741617                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      5530609                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       862152                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       741495                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       486160                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       325301                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       465486                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           67                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1278141                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1152631                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17668715                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15752783                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       346532                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1063511                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         34831541                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    565398848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    598192623                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1259640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3873096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1168724207                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   10729638                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     29561564                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.351841                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.477545                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      16482247                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13994677                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        33105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        33105                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      3733141                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1450559                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1135277                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       764525                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       439100                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       331866                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       445825                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           56                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1265717                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1135924                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19032980                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15771109                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       324159                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1044893                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         36173141                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    609055296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    597396947                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1171600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3801480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1211425323                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5254625                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     24752436                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.199831                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.399873                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          19160579     64.82%     64.82% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6          10400985     35.18%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          19806132     80.02%     80.02% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6           4946304     19.98%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      29561564                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   14119794312                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      24752436                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14477877088                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    225496496                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    203336996                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  13269247990                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14303799012                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7748577182                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7760036291                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    189385144                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    177959354                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    579874631                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    570171512                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              146637664                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted        104244557                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6464776                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           109760718                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               80092874                       # Number of BTB hits
+system.cpu1.branchPred.lookups              141025153                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted        100933183                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6236213                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           106937612                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               78176713                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.970436                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17287162                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1125459                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.104974                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16283768                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1021605                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1160,27 +1282,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   298651                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               298651                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11560                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94332                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       298651                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         298651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       298651                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       105892                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       104531     98.71%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1148      1.08%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           61      0.06%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           60      0.06%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           63      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       105892                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1172907556                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1172907556    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1172907556                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        94332     89.08%     89.08% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        11560     10.92%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       105892                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       298651                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       298651                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       105892                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       105892                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       404543                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    95196820                       # DTB read hits
-system.cpu1.dtb.read_misses                    258683                       # DTB read misses
-system.cpu1.dtb.write_hits                   82774540                       # DTB write hits
-system.cpu1.dtb.write_misses                    48918                       # DTB write misses
+system.cpu1.dtb.read_hits                    90905034                       # DTB read hits
+system.cpu1.dtb.read_misses                    248418                       # DTB read misses
+system.cpu1.dtb.write_hits                   78767149                       # DTB write hits
+system.cpu1.dtb.write_misses                    50233                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   40938                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1166                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8454                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              42371                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   43819                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      923                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8321                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11190                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                95455503                       # DTB read accesses
-system.cpu1.dtb.write_accesses               82823458                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    12272                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                91153452                       # DTB read accesses
+system.cpu1.dtb.write_accesses               78817382                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        177971360                       # DTB hits
-system.cpu1.dtb.misses                         307601                       # DTB misses
-system.cpu1.dtb.accesses                    178278961                       # DTB accesses
+system.cpu1.dtb.hits                        169672183                       # DTB hits
+system.cpu1.dtb.misses                         298651                       # DTB misses
+system.cpu1.dtb.accesses                    169970834                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1202,145 +1366,179 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   262373201                       # ITB inst hits
-system.cpu1.itb.inst_misses                     66107                       # ITB inst misses
+system.cpu1.itb.walker.walks                    67610                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                67610                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          497                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        58418                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        67610                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          67610    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        67610                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        58915                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        57403     97.43%     97.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1356      2.30%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607           66      0.11%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           56      0.10%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           19      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           10      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        58915                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1173450056                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1173450056    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1173450056                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        58418     99.16%     99.16% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          497      0.84%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        58915                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        67610                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        67610                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58915                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58915                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       126525                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   252933263                       # ITB inst hits
+system.cpu1.itb.inst_misses                     67610                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              42758                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1054                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   29545                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              42371                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1050                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   31594                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   222220                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   222493                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               262439308                       # ITB inst accesses
-system.cpu1.itb.hits                        262373201                       # DTB hits
-system.cpu1.itb.misses                          66107                       # DTB misses
-system.cpu1.itb.accesses                    262439308                       # DTB accesses
-system.cpu1.numCycles                       965776076                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               253000873                       # ITB inst accesses
+system.cpu1.itb.hits                        252933263                       # DTB hits
+system.cpu1.itb.misses                          67610                       # DTB misses
+system.cpu1.itb.accesses                    253000873                       # DTB accesses
+system.cpu1.numCycles                       943783669                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  483897990                       # Number of instructions committed
-system.cpu1.committedOps                    569285719                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     49152054                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     5850                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93733878410                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              1.995826                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.501046                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  461717275                       # Number of instructions committed
+system.cpu1.committedOps                    543187389                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     49256164                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5826                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93768369123                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.044073                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.489219                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14403                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      777604637                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      188171439                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5691678                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          432.252247                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          169393329                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5692190                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.758903                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8364525946500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   432.252247                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.844243                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.844243                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        358720623                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       358720623                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst     87552380                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       87552380                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst     77214593                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      77214593                       # number of WriteReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst       211985                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       211985                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst      1994962                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1994962                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst      1944639                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1944639                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst    164766973                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       164766973                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst    164766973                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      164766973                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst      4362572                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      4362572                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst      2362737                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2362737                       # number of WriteReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst       497251                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       497251                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst       139927                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       139927                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst       188742                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       188742                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst      6725309                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       6725309                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst      6725309                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6725309                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst  63153941750                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  63153941750                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst  37295206516                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  37295206516                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst   9223332559                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total   9223332559                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst   1921743254                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   1921743254                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst   3886161820                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3886161820                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst      3267000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3267000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 100449148266                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 100449148266                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst     91914952                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     91914952                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst     79577330                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     79577330                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst       709236                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       709236                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst      2134889                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2134889                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst      2133381                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2133381                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst    171492282                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    171492282                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.inst    171492282                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    171492282                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.047463                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.047463                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.029691                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029691                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst     0.701108                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.701108                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.065543                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.065543                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.088471                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.088471                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.039216                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.039216                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.039216                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.039216                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    5890                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      748189458                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      195594211                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5624476                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          426.107402                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          161270449                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5624987                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.670368                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8377201144000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   426.107402                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.832241                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.832241                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        342291215                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       342291215                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst     83489779                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       83489779                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst     73474609                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      73474609                       # number of WriteReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst        71990                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total        71990                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst      1908367                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1908367                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst      1854336                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1854336                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst    156964388                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       156964388                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst    156964388                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      156964388                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst      4311289                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      4311289                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst      2366929                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2366929                       # number of WriteReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst       476593                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       476593                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst       141331                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       141331                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst       193852                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       193852                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst      6678218                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       6678218                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst      6678218                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6678218                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst  60722587231                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  60722587231                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst  38093191666                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  38093191666                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst  11613108236                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  11613108236                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst   1977833980                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   1977833980                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst   3982712056                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   3982712056                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst      2357000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2357000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst  98815778897                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  98815778897                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst  98815778897                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  98815778897                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst     87801068                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     87801068                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst     75841538                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     75841538                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst       548583                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       548583                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst      2049698                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2049698                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst      2048188                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2048188                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst    163642606                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    163642606                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst    163642606                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    163642606                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.049103                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.049103                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.031209                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.031209                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst     0.868771                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.868771                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.068952                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.068952                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.094646                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094646                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.040810                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040810                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.040810                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.040810                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1349,88 +1547,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3739270                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3739270                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst       400087                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       400087                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst       959724                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       959724                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst           47                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           47                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           67                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst           75                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           75                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst      1359811                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1359811                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst      1359811                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1359811                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst      3962485                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3962485                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst      1403013                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1403013                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst       497204                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       497204                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst       139860                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       139860                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst       188667                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       188667                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst      5365498                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      5365498                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst      5365498                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5365498                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst  49100377691                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  49100377691                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst  20233474919                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20233474919                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   8220345441                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total   8220345441                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst   1640188222                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1640188222                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst   3498307132                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3498307132                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst      2504000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2504000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst  69333852610                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  69333852610                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst  69333852610                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  69333852610                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3411173732                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3411173732                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst   3123925989                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3123925989                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst   6535099721                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6535099721                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.043110                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043110                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.017631                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017631                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.701042                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.701042                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.065512                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065512                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.088436                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.088436                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.031287                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031287                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.031287                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031287                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3711348                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3711348                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst       397792                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       397792                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst       970938                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       970938                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst           60                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total           60                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           47                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total           47                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst           68                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           68                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst      1368730                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1368730                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst      1368730                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1368730                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst      3913497                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3913497                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst      1395991                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1395991                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst       476533                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       476533                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst       141284                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141284                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst       193784                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       193784                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst      5309488                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      5309488                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst      5309488                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5309488                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst  46779736993                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  46779736993                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst  20386885918                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20386885918                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst  10653380764                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  10653380764                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst   1693632498                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1693632498                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst   3584420895                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3584420895                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst  67166622911                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  67166622911                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst  67166622911                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  67166622911                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst    548139751                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    548139751                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst    613571252                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    613571252                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst   1161711003                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1161711003                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.044572                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.044572                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.018407                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018407                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.868662                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.868662                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.068929                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068929                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.094612                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094612                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.032446                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032446                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.032446                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032446                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1438,58 +1636,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements         10003641                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.113561                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          252141010                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs         10004153                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.203634                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8364450905000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.113561                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990456                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990456                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          9215030                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          507.228865                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          243489253                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9215542                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            26.421588                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8367568177500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.228865                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990681                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990681                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          148                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          256                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        534294484                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       534294484                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    252141010                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      252141010                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    252141010                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       252141010                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    252141010                       # number of overall hits
-system.cpu1.icache.overall_hits::total      252141010                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst     10004155                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total     10004155                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst     10004155                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total      10004155                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst     10004155                       # number of overall misses
-system.cpu1.icache.overall_misses::total     10004155                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  85019530358                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  85019530358                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  85019530358                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  85019530358                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  85019530358                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  85019530358                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    262145165                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    262145165                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    262145165                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    262145165                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    262145165                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    262145165                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038163                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.038163                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038163                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.038163                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038163                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.038163                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8498.421941                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8498.421941                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8498.421941                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8498.421941                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8498.421941                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8498.421941                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        514625132                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       514625132                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    243489253                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      243489253                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    243489253                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       243489253                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    243489253                       # number of overall hits
+system.cpu1.icache.overall_hits::total      243489253                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9215542                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9215542                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9215542                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9215542                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9215542                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9215542                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  91468274167                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  91468274167                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  91468274167                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  91468274167                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  91468274167                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  91468274167                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    252704795                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    252704795                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    252704795                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    252704795                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    252704795                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    252704795                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.036468                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.036468                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.036468                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.036468                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.036468                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.036468                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9925.436200                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9925.436200                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9925.436200                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9925.436200                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9925.436200                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9925.436200                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1498,353 +1696,355 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst     10004155                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total     10004155                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst     10004155                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total     10004155                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst     10004155                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total     10004155                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  70001431618                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  70001431618                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  70001431618                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  70001431618                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  70001431618                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  70001431618                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8751000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8751000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8751000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8751000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038163                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.038163                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038163                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.038163                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6997.235810                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  6997.235810                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6997.235810                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  6997.235810                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9215542                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9215542                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9215542                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9215542                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9215542                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9215542                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  77617743273                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  77617743273                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  77617743273                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  77617743273                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  77617743273                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  77617743273                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8388750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8388750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8388750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8388750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.036468                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.036468                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.036468                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.036468                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.036468                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.036468                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8422.482722                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8422.482722                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8422.482722                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8422.482722                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8422.482722                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8422.482722                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     91266400                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2590593                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     83739964                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      1124296                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       159143                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      3652396                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      7945944                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         3964575                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13771.716542                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17209014                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         3980703                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            4.323109                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9604482251250                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  4186.861890                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.243250                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    63.010570                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2902.209445                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6553.391387                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.255546                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004043                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003846                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.177137                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.399987                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.840559                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9777                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           42                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6309                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           89                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          734                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         4083                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         3317                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1554                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          691                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3097                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1911                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          531                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.596741                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002563                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.385071                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       336896441                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      336896441                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       545727                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       151675                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst     13043643                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total      13741045                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3739269                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3739269                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst       314994                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       314994                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst        88927                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        88927                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst        41659                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        41659                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.inst       944385                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       944385                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       545727                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       151675                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst     13988028                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       14685430                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       545727                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       151675                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst     13988028                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      14685430                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        14704                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10320                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst      1062508                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total      1087532                       # number of ReadReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst       180857                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total       180857                       # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst       132678                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       132678                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst       147002                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       147002                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.inst       238730                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       238730                       # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        14704                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10320                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst      1301238                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1326262                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        14704                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10320                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst      1301238                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1326262                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    525735124                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    414121710                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  33089400106                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total  34029256940                       # number of ReadReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst   5173608568                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total   5173608568                       # number of WriteInvalidateReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst   2603383383                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2603383383                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst   2990869344                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2990869344                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst      2444000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2444000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   9524400999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   9524400999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    525735124                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    414121710                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  42613801105                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  43553657939                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    525735124                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    414121710                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  42613801105                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  43553657939                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       560431                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       161995                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst     14106151                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total     14828577                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3739269                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3739269                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst       495851                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total       495851                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst       221605                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       221605                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst       188661                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       188661                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst      1183115                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1183115                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       560431                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       161995                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst     15289266                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     16011692                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       560431                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       161995                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst     15289266                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     16011692                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.075322                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.073340                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst     0.364741                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.364741                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.598714                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.598714                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.779186                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.779186                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.num_hwpf_issued     11995647                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified     12001276                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         4903                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage      1360052                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2569302                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13533.660217                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          15700970                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2584965                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            6.073958                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9611078525000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks  5526.220513                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    77.627317                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    76.256480                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  6438.113983                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1415.441924                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.337294                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004738                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004654                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.392951                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.086392                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.826029                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         2491                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13080                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          600                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1302                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          576                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           72                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4875                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5316                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2499                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.152039                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.798340                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       321109712                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      321109712                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       544517                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       158528                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.inst     11678610                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total      12381655                       # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks      3711345                       # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total      3711345                       # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst       202419                       # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total       202419                       # number of WriteInvalidateReq hits
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+system.cpu1.l2cache.UpgradeReq_hits::total        77280                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst        41809                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total        41809                       # number of SCUpgradeReq hits
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+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       544517                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       158528                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       158528                       # number of overall hits
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+system.cpu1.l2cache.overall_hits::total      13320774                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12561                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8870                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst      1591427                       # number of ReadReq misses
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+system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
+system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst       272843                       # number of WriteInvalidateReq misses
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+system.cpu1.l2cache.UpgradeReq_misses::total       137034                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst       151974                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst            1                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
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+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12561                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8870                       # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8870                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst      1835548                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1856979                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    455863233                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    358991737                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst  47206598788                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total  48021453758                       # number of ReadReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst    213581444                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total    213581444                       # number of WriteInvalidateReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst   2792930491                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   2792930491                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst   3071034580                       # number of SCUpgradeReq miss cycles
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+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst      1783500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1783500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst   9626384839                       # number of ReadExReq miss cycles
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+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  56832983627                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  57647838597                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    358991737                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  56832983627                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  57647838597                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst     13270037                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total     13994513                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3711346                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3711346                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst       475262                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total       475262                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst       214314                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       214314                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst       193783                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       193783                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst      1183240                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1183240                       # number of ReadExReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022548                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.052987                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.119926                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.115249                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst     0.574090                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.574090                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst     0.639408                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.639408                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst     0.784248                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.784248                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.201781                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.201781                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.085108                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.082831                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026237                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.063706                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.085108                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.082831                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35754.565016                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40128.072674                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31142.730319                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31290.350022                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 28606.073130                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40128.072674                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32748.660203                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32839.407251                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35754.565016                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40128.072674                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32748.660203                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32839.407251                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs        95890                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst     0.206316                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.206316                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022548                       # miss rate for demand accesses
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+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.126999                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.122349                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average ReadReq miss latency
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29663.062640                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197                       # average ReadReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst   782.799793                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total   782.799793                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20381.295817                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20207.631437                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst      1783500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1783500                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39432.842070                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30962.406664                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30962.406664                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs            1623                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    59.081947                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1340101                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1340101                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            3                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        83863                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total        83867                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst       117019                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total       117019                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst        10752                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        10752                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        94615                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        94619                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        94615                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        94619                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        14703                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10317                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       978645                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total      1003665                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      3652327                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total      3652327                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst        63838                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total        63838                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst       132678                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       132678                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst       147002                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       147002                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst       227978                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       227978                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        14703                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10317                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst      1206623                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1231643                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        14703                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10317                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst      1206623                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      3652327                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      4883970                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  24526546457                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  25289617509                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 110063206845                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   1132471294                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   1132471294                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst   2172031189                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2172031189                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst   2030926339                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2030926339                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst      2024000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2024000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   6846769063                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   6846769063                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  31373315520                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  32136386572                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    421971770                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    341099282                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  31373315520                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 142199593417                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst   3254469267                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3254469267                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst   2984537511                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2984537511                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst   6239006778                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6239006778                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.069377                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.067685                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.writebacks::writebacks      1092301                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1092301                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1805                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total         1806                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst           45                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total           45                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst         7072                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         7072                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         8877                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         8878                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         8877                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         8878                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12561                       # number of ReadReq MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst      1589622                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total      1611052                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      1032302                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total      1032302                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst       272798                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       272798                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst       137034                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       137034                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst       151974                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       151974                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst       237049                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       237049                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12561                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8869                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst      1826671                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1848101                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12561                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8869                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst      1826671                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      1032302                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2880403                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst  35897455818                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  36560910324                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  41289088164                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  41289088164                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   7103244766                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   7103244766                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst   2312644672                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2312644672                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst   2076231085                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2076231085                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst      1461500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1461500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst   7288633813                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7288633813                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  43186089631                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  43849544137                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    367223255                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    296231251                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  43186089631                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  41289088164                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  85138632301                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst    514241998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    514241998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst    574249999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    574249999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst   1088491997                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1088491997                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.119790                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.115120                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.128744                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.128744                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.598714                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.598714                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.779186                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.779186                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.573995                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.573995                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst     0.639408                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.639408                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.784248                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.784248                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.192693                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.192693                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.078920                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.076921                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026235                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.063687                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.078920                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst     0.200339                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.200339                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.126385                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.121764                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022548                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.052982                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.126385                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.305025                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.189778                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst      1461500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1461500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -1852,65 +2052,66 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      19283354                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     15081139                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        18583                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        18583                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3739269                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      5170827                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       625737                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       495851                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       477449                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       330499                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       473092                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1314338                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1188302                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     20008489                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16359278                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       359533                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1226091                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         37953391                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    640271616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    615594373                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1295960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4483448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1261645397                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   10423087                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     30921485                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.327379                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.469257                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq      16597851                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     14230777                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         5242                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5242                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3711346                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1418597                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1143341                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       475262                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       452039                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       340076                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       470072                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1342662                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1189275                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18431264                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16132557                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       369420                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1220438                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         36153679                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    589800448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    609347251                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1339184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4456624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1204943507                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5386490                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     25000724                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.203488                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.402593                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          20798445     67.26%     67.26% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6          10123040     32.74%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          19913365     79.65%     79.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6           5087359     20.35%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      30921485                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   14664539498                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      25000724                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   14152090513                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    176010242                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    175296997                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  15012316370                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  13837074197                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8461463125                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8360530852                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    197959664                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    202402154                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    666269864                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    663973984                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40348                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40348                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136740                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              30012                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40424                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40424                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136766                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30038                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48186                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1925,13 +2126,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122926                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231170                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231170                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123068                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231232                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231232                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354176                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354380                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48206                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1946,13 +2147,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156056                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338696                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338696                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156198                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338944                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338944                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496838                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36517000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7497228                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36614000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1980,71 +2181,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042881499                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1043031468                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92917000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            93033000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179159841                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179210230                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115566                       # number of replacements
-system.iocache.tags.tagsinuse               11.298842                       # Cycle average of tags in use
+system.iocache.tags.replacements               115597                       # number of replacements
+system.iocache.tags.tagsinuse               11.297216                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115582                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115613                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9120788284000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.841658                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.457184                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.240104                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466074                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706178                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9126956441000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.841188                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.456028                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.240074                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466002                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706076                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040622                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040622                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040901                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040901                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8857                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8894                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8888                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8925                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106728                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106728                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8857                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8897                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8888                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8928                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8857                       # number of overall misses
-system.iocache.overall_misses::total             8897                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1971462847                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1977169847                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8888                       # number of overall misses
+system.iocache.overall_misses::total             8928                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5659000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1934548608                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1940207608                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28907198811                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28907198811                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1971462847                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1977526847                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1971462847                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1977526847                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28977416630                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28977416630                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      6016000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1934548608                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1940564608                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      6016000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1934548608                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1940564608                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8857                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8894                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8888                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8925                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106728                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8857                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8897                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8888                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8928                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8857                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8897                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8888                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8928                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2058,55 +2259,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 222303.783112                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217390.208179                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 222588.105115                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 222268.949871                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 222588.105115                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 222268.949871                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        228015                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       150400                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 217658.484248                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 217357.146953                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       150400                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 217658.484248                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 217357.146953                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        228934                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27566                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27737                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.271603                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.253740                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106694                       # number of writebacks
 system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8857                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8894                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8888                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8925                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106728                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total       106728                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8857                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8897                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8888                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8928                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8857                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8897                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1510755865                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1514538865                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8888                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8928                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3735000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1472256614                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1475991614                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23356679475                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23356679475                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1510755865                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1514739865                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1510755865                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1514739865                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23427107084                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23427107084                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3936000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1472256614                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1476192614                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3936000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1472256614                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1476192614                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2120,493 +2321,484 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 170252.879060                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 170252.879060                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        98400                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 165344.154794                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        98400                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 165344.154794                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1797599                       # number of replacements
-system.l2c.tags.tagsinuse                64905.725288                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    8591301                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1860596                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.617499                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               6896032000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    7600.616161                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    16.639535                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     9.409863                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1890.006249                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   324.497512                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   441.216776                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst    10554.786238                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.115976                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000254                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000144                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.028839                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.258806                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004951                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006732                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.161053                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.413626                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.990383                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        43530                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          179                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        19288                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1          252                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1656                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6242                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        35370                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          173                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          846                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         1730                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        16555                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.664215                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.002731                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.294312                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 89688959                       # Number of tag accesses
-system.l2c.tags.data_accesses                89688959                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         8987                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6604                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             578381                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      2301852                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         8168                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5333                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             630016                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      2353942                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                5893283                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         2942617                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2942617                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.inst         6235                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.inst         6750                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total        12985                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.inst           39044                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst           35229                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               74273                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst          7514                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst          7779                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             15293                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.inst            64131                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst            55187                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               119318                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          8987                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6604                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              642512                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher      2301852                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          8168                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5333                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              685203                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher      2353942                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 6012601                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         8987                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6604                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             642512                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher      2301852                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         8168                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5333                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             685203                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher      2353942                       # number of overall hits
-system.l2c.overall_hits::total                6012601                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1978                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1693                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            95514                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       863521                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2685                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2512                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst           131326                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       566480                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total              1665709                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.inst        16918                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.inst         7174                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total        24092                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.inst         36442                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.inst         33251                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             69693                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.inst         9494                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.inst         9010                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18504                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.inst          45340                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.inst          52041                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              97381                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1978                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1693                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst            140854                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       863521                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2685                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2512                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst            183367                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       566480                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1763090                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1978                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1693                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst           140854                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       863521                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2685                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2512                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst           183367                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       566480                       # number of overall misses
-system.l2c.overall_misses::total              1763090                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    165226748                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    144557248                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   7974806913                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    222345248                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    209364000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst  10644136699                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total   220050587910                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst      3639850                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst      3440357                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total      7080207                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.inst    167282107                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.inst    155790979                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    323073086                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.inst     53447323                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.inst     50683879                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    104131202                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.inst   3468272337                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.inst   3934530582                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7402802919                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    165226748                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    144557248                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst  11443079250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    222345248                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    209364000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst  14578667281                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    227453390829                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    165226748                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    144557248                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst  11443079250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    222345248                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    209364000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst  14578667281                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  70875583160                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   227453390829                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        10965                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         8297                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         673895                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      3165373                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10853                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         7845                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         761342                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2920422                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            7558992                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      2942617                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2942617                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.inst        23153                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.inst        13924                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total        37077                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.inst        75486                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.inst        68480                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          143966                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.inst        17008                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.inst        16789                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         33797                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.inst       109471                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.inst       107228                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           216699                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10965                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         8297                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          783366                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher      3165373                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10853                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7845                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          868570                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2920422                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             7775691                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10965                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         8297                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         783366                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher      3165373                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10853                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7845                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         868570                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2920422                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            7775691                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.141734                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.172493                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.220361                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst     0.730704                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst     0.515226                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.649783                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.482765                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.485558                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.484093                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.558208                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.536661                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.547504                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.inst     0.414174                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.inst     0.485330                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.449384                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.179806                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.211114                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.226744                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.180392                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.204050                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.179806                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.272802                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.247397                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.320204                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.211114                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.193972                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.226744                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83493.591651                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81051.251839                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 132106.261004                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst   215.146589                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst   479.559102                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   293.882077                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  4590.365704                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  4685.302066                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4635.660482                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  5629.589530                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  5625.291787                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5627.496866                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 76018.965907                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 129008.383480                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 129008.383480                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             43295                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1473453                       # number of replacements
+system.l2c.tags.tagsinuse                64480.086956                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5089807                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1533812                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.318403                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               8003493500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   16627.933383                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    13.809416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    10.076521                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7682.914611                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5733.726218                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   373.789781                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   460.262003                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst    14361.821399                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.253722                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000211                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000154                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.117232                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.087490                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005704                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.007023                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.219144                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.293209                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.983888                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        14505                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          200                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        45654                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          147                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          696                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        13662                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          200                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1737                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4894                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        38831                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.221329                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.696625                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 65568567                       # Number of tag accesses
+system.l2c.tags.data_accesses                65568567                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         6731                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         4742                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst            1051842                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher       530462                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                3314514                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         2491671                       # number of Writeback hits
+system.l2c.Writeback_hits::total              2491671                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.inst       125819                       # number of WriteInvalidateReq hits
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+system.l2c.UpgradeReq_hits::cpu1.inst           32403                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               62168                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.inst          5875                       # number of SCUpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::total             12261                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_hits::total               109734                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6731                       # number of demand (read+write) hits
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+system.l2c.ReadReq_misses::cpu0.dtb.walker         1664                       # number of ReadReq misses
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+system.l2c.ReadReq_misses::total               870286                       # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.inst       435530                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::cpu1.inst       123517                       # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::total       559047                       # number of WriteInvalidateReq misses
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+system.l2c.UpgradeReq_misses::cpu1.inst         45474                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             90433                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.inst         8261                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           17299                       # number of SCUpgradeReq misses
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+system.l2c.demand_misses::cpu0.dtb.walker         1664                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total               1002083                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1664                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1301                       # number of overall misses
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+system.l2c.overall_misses::total              1002083                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    138961746                       # number of ReadReq miss cycles
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+system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  37505012849                       # number of ReadReq miss cycles
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+system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst     36612963                       # number of WriteInvalidateReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu0.inst    213542030                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.inst    216684315                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    430226345                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.inst     36699987                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.inst     41305269                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     78005256                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.inst   6278532917                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total  10486284499                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    138961746                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    111055248                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst  19834564997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  37505012849                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    202393999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    185177500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst  16969846032                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  31520804985                       # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::cpu0.dtb.walker    138961746                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu0.inst  19834564997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  37505012849                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    202393999                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu1.inst  16969846032                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  31520804985                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   106467817356                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         8395                       # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu0.inst        1220935                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       796553                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         9295                       # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu1.inst        1349794                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher       786977                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            4184800                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      2491671                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2491671                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.inst       561349                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu1.inst       264022                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::total       825371                       # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.inst        74724                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.inst        77877                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          152601                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.inst        14136                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.inst        15424                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         29560                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.inst       133036                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.inst       108495                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           241531                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8395                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6043                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         1353971                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       796553                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9295                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.inst         1458289                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       786977                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4426331                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8395                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6043                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        1353971                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       796553                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9295                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.inst        1458289                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       786977                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4426331                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.198213                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.215290                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.138495                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.266595                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.339160                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.120184                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.207964                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst     0.775863                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst     0.467828                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.677328                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.601667                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.583921                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.592611                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.584394                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.585970                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.585217                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.inst     0.576077                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.inst     0.508392                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.545673                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.198213                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.215290                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.181490                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.266595                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.339160                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.149066                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.226391                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.198213                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.215290                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.181490                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.266595                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.339160                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.149066                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.226391                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80169.090855                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78670.068054                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 110287.345605                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst    84.065307                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst   289.502514                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   129.455028                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  4749.705954                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  4765.015503                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4757.404321                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst  4442.559860                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  4570.178026                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4509.234985                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 76285.426992                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 79563.908883                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 80716.247770                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 78064.992028                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 106246.505884                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 106246.505884                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              5735                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      946                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      156                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     45.766385                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     36.762821                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1219289                       # number of writebacks
-system.l2c.writebacks::total                  1219289                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst            49                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            53                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               581                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             49                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             53                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                581                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            49                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          228                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            53                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          251                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               581                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1978                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1693                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        95465                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2685                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2512                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst       131273                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total         1665128                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst        16918                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst         7174                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total        24092                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst        36442                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst        33251                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        69693                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst         9494                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         9010                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18504                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst        45340                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.inst        52041                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         97381                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1978                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1693                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst       140805                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2685                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2512                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst       183314                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1762509                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1978                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1693                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst       140805                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       863293                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2685                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2512                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst       183314                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       566229                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1762509                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   6776817493                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   8997883953                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 199639162524                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst    385829647                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst    157261640                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total    543091287                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst    371667466                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst    338371346                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    710038812                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst     97958865                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     92039394                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    189998259                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   2897122081                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   3278712382                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   6175834463                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   9673939574                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst  12276596335                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 205814996987                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    140499248                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    123414748                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   9673939574                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    188732748                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    177898500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst  12276596335                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  63932898160                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 205814996987                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5245081248                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   2881233750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8126314998                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   2584862001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst   2667893000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5252755001                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   7829943249                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   5549126750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13379069999                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.141662                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.172423                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.220284                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.730704                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.515226                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.649783                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.482765                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.485558                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.484093                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.558208                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.536661                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.547504                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.414174                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.485330                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.449384                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.179744                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.211053                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.226669                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.180392                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.204050                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.179744                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.272730                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.247397                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.320204                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.211053                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.193886                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.226669                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 116773.870084                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 116773.870084                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks             1116216                       # number of writebacks
+system.l2c.writebacks::total                  1116216                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst           210                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst           177                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               387                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            210                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            177                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                387                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           210                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           177                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               387                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1664                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1301                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst       168883                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2478                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2309                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst       162046                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       256515                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          869899                       # number of ReadReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst       435530                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst       123517                       # number of WriteInvalidateReq MSHR misses
+system.l2c.WriteInvalidateReq_mshr_misses::total       559047                       # number of WriteInvalidateReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.inst        44959                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.inst        45474                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        90433                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst         8261                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst         9038                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        17299                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.inst        76639                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.inst        55158                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        131797                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker         1664                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker         1301                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst       245522                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       274703                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker         2478                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker         2309                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst       217204                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       256515                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total          1001696                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         1664                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker         1301                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst       245522                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       274703                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker         2478                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker         2309                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst       217204                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       256515                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total         1001696                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    118167746                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker     94777748                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst  11415126178                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  34136893349                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    171330499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    156241500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst  10713554460                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  28363294485                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  85169385965                       # number of ReadReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst   9786055012                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst   2515639470                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.WriteInvalidateReq_mshr_miss_latency::total  12301694482                       # number of WriteInvalidateReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst    455524094                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst    460871563                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    916395657                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst     84887682                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst     92374949                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    177262631                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   5315349505                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   3512186842                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8827536347                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    118167746                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     94777748                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst  16730475683                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  34136893349                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    171330499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    156241500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst  14225741302                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  28363294485                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  93996922312                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    118167746                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     94777748                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst  16730475683                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  34136893349                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    171330499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    156241500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst  14225741302                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  28363294485                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  93996922312                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   7718194748                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    418305498                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8136500246                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   4773990997                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst    484709502                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5258700499                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst  12492185745                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    903015000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13395200745                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.198213                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.215290                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.138323                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.266595                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.339160                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.120052                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.207871                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst     0.775863                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst     0.467828                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.677328                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.601667                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.583921                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.592611                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.584394                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.585970                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.585217                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.576077                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.508392                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.545673                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.198213                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.215290                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.181335                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.266595                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.339160                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.148944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.226304                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.198213                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.215290                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.181335                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.344865                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.266595                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.339160                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.148944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.325950                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.226304                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 93837.773448                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 93837.773448                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2617,57 +2809,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             1764688                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1764688                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38271                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38271                       # Transaction distribution
-system.membus.trans_dist::Writeback           1325983                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       130519                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       130519                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           461811                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         273493                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           92294                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            109929                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            93588                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122926                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq              969598                       # Transaction distribution
+system.membus.trans_dist::ReadResp             969598                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38347                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38347                       # Transaction distribution
+system.membus.trans_dist::Writeback           1222910                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       662686                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       662686                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           426453                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         285961                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          115017                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            144468                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127604                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123068                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24884                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5737506                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5885368                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336109                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       336109                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6221477                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25110                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5176712                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5324942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335765                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335765                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5660707                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156198                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49768                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    195441096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    195648244                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14110976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14110976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               209759220                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           661928                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3975767                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50220                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    174186440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    174394182                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14086976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14086976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               188481158                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           617229                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3621307                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3975767    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3621307    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3975767                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109763969                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3621307                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109998990                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               34484                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20835993                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            20906994                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         15443357238                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         18632739306                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        16944581187                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        10660858032                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          187180159                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          187340770                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2711,45 +2903,45 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            8566773                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           8559524                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38271                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38271                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2942617                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       143810                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp        37077                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          531990                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        288786                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         820776                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          117                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          117                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           266520                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          266520                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10703555                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10080815                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              20784370                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    361515951                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    330513413                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              692029364                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1718447                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         12650717                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.009140                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.095166                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5129422                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           5122206                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38347                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38347                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2491671                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       932101                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp       825371                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          481339                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        298222                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         779561                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          103                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          103                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           298688                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          298688                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8006212                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7112719                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15118931                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    267664595                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    231600691                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              499265286                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1616950                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9541409                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012122                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.109429                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               12535087     99.09%     99.09% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115630      0.91%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                9425751     98.79%     98.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115658      1.21%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           12650717                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        18290340474                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            9541409                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        18624671874                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          7404000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          7692000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20424320611                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       12569931680                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       19750107809                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       12640622488                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 0607c3606..3ebfb1ad5 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,135 +1,135 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.688410                       # Number of seconds simulated
-sim_ticks                                51688410348500                       # Number of ticks simulated
-final_tick                               51688410348500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.728175                       # Number of seconds simulated
+sim_ticks                                51728174627500                       # Number of ticks simulated
+final_tick                               51728174627500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152333                       # Simulator instruction rate (inst/s)
-host_op_rate                                   179011                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8275752383                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 662164                       # Number of bytes of host memory used
-host_seconds                                  6245.77                       # Real time elapsed on the host
-sim_insts                                   951433762                       # Number of instructions simulated
-sim_ops                                    1118058358                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 184836                       # Simulator instruction rate (inst/s)
+host_op_rate                                   217188                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10028441874                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 718288                       # Number of bytes of host memory used
+host_seconds                                  5158.15                       # Real time elapsed on the host
+sim_insts                                   953410832                       # Number of instructions simulated
+sim_ops                                    1120287994                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       411264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       350272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          77213320                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        415808                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78390664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10284736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10284736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     94966144                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       394816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       334912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          77628104                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        424256                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             78782088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10241472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10241472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     95103808                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.inst          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          94986724                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         6426                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5473                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst            1206471                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6497                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1224867                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1483846                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          95124388                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6169                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5233                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst            1212952                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6629                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1230983                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1485997                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.inst              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1486419                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           7957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              1493823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8045                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1516600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          198976                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             198976                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1837281                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1488570                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7633                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1500693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1523002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          197986                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             197986                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1838530                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.inst                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1837679                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1837281                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          7957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1494221                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8045                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3354280                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1224867                       # Number of read requests accepted
-system.physmem.writeReqs                      2137165                       # Number of write requests accepted
-system.physmem.readBursts                     1224867                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    2137165                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 78347456                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     44032                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 136289472                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78390664                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              136634468                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      688                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7616                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          39979                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               71039                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               73325                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               71985                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               70214                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               72864                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               82821                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               75004                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               73137                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               67826                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              129786                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              72316                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              77203                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              71594                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              74115                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              68849                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              72101                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              128045                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              133141                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              133329                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              132983                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              135529                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              141007                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              130525                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              133720                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              132879                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              138815                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             133616                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             135999                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             129210                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             131804                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             128438                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             130483                       # Per bank write bursts
+system.physmem.bw_write::total                1838928                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1838530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7633                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1501091                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3361929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1230983                       # Number of read requests accepted
+system.physmem.writeReqs                      2135785                       # Number of write requests accepted
+system.physmem.readBursts                     1230983                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2135785                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 78738176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     44736                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 136238784                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  78782088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              136546148                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      699                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7032                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          39789                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               72855                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               77589                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               71702                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               69206                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               71012                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               79882                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               74555                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               73696                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               66951                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130748                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              72702                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              77684                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              73029                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              75645                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              69035                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              73993                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              130105                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              136647                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              132594                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              132058                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              132790                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              135723                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              131916                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              135307                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              129762                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              138269                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             133041                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             135411                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             131809                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             134107                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             128778                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             130414                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51688408694500                       # Total gap between requests
+system.physmem.totGap                    51728172924500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
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 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1224852                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1230968                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
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 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                2134592                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1187733                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     30120                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      105                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19                       54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2133212                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::9                       151                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -155,118 +155,120 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::33                     4095                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42                     2151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2024                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::50                      961                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52                      680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      407                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::56                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       728572                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.598947                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     169.664587                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.125501                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         296144     40.65%     40.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       177091     24.31%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        64790      8.89%     73.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35671      4.90%     78.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        25285      3.47%     82.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        17267      2.37%     84.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13064      1.79%     86.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        11522      1.58%     87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        87738     12.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         728572                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         97844                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.511242                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      125.941708                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          97842    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::samples       724941                       # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::gmean     170.840359                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.964737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         292739     40.38%     40.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       175978     24.27%     64.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        64522      8.90%     73.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        36242      5.00%     78.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        25200      3.48%     82.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        17306      2.39%     84.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        13334      1.84%     86.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        11857      1.64%     87.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        87763     12.11%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         724941                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         98383                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.504427                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      125.607658                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          98380    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           97844                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         97844                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.764472                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.107027                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.533220                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           71394     72.97%     72.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31           19346     19.77%     92.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39            3261      3.33%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             806      0.82%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             888      0.91%     97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             399      0.41%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             342      0.35%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             242      0.25%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             261      0.27%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             243      0.25%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            222      0.23%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            63      0.06%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            71      0.07%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            48      0.05%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135           149      0.15%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            24      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            24      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             7      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            12      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             6      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            10      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             4      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           98383                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         98383                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.637183                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.054808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.113777                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           71754     72.93%     72.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31           19885     20.21%     93.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            3061      3.11%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             745      0.76%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             867      0.88%     97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             408      0.41%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             354      0.36%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             234      0.24%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             298      0.30%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             183      0.19%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            211      0.21%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            51      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            56      0.06%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            41      0.04%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           125      0.13%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            21      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            37      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             9      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            12      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             3      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             7      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           97844                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    16127261998                       # Total ticks spent queuing
-system.physmem.totMemAccLat               39080618248                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6120895000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13173.94                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           98383                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15890716010                       # Total ticks spent queuing
+system.physmem.totMemAccLat               38958541010                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6151420000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12916.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31923.94                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31666.30                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.63                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -274,36 +276,41 @@ system.physmem.busUtil                           0.03                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.82                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     946951                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1678178                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.35                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15374157.26                       # Average gap between requests
-system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49562808778250                       # Time in different power states
-system.physmem.memoryStateTime::REF      1725989460000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      399611675250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2776243680                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2731760640                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1514815500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1490544000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               4604987400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               4943562000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              6922447920                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              6876861120                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3376035383760                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3376035383760                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1310091236460                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1307916167760                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29863840623750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29865748578750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34565785738470                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34565742858030                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.733833                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.733004                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        24.58                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     953619                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1680454                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.94                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15364341.39                       # Average gap between requests
+system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2748558960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1499709750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4605829800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               6915067200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3378632599680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1310572243215                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29887277315250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34592251323855                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.731394                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49719326487750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1727317280000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    281530424750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 2731995000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1490671875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4990338600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               6879109680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3378632599680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1309819963770                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29887937201250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34592481879855                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.735851                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49720391571002                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1727317280000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    280461298998                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          704                       # Number of instructions bytes read from this memory
@@ -322,16 +329,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               261297703                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         183348683                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12210638                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            193789546                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               136743179                       # Number of BTB hits
+system.cpu.branchPred.lookups               261740307                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         183617747                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12193617                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            193974198                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               136954935                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.562722                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31690204                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2146162                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.604718                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31757981                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2120874                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -353,27 +368,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                    587644                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                587644                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20971                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       193860                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       587644                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          587644    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       587644                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       214831                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       212337     98.84%     98.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2138      1.00%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          152      0.07%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          133      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           38      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           25      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       214831                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   -243009796                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      -243009796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   -243009796                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        193861     90.24%     90.24% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         20971      9.76%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       214832                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       587644                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       587644                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       214832                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       214832                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       802476                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183672011                       # DTB read hits
-system.cpu.dtb.read_misses                     484545                       # DTB read misses
-system.cpu.dtb.write_hits                   163011983                       # DTB write hits
-system.cpu.dtb.write_misses                    101734                       # DTB write misses
+system.cpu.dtb.read_hits                    184101010                       # DTB read hits
+system.cpu.dtb.read_misses                     486113                       # DTB read misses
+system.cpu.dtb.write_hits                   163332837                       # DTB write hits
+system.cpu.dtb.write_misses                    101531                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               47436                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    80165                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       779                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  14148                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    79171                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       889                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  14871                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23574                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                184156556                       # DTB read accesses
-system.cpu.dtb.write_accesses               163113717                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23598                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                184587123                       # DTB read accesses
+system.cpu.dtb.write_accesses               163434368                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         346683994                       # DTB hits
-system.cpu.dtb.misses                          586279                       # DTB misses
-system.cpu.dtb.accesses                     347270273                       # DTB accesses
+system.cpu.dtb.hits                         347433847                       # DTB hits
+system.cpu.dtb.misses                          587644                       # DTB misses
+system.cpu.dtb.accesses                     348021491                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -395,142 +452,175 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    455292001                       # ITB inst hits
-system.cpu.itb.inst_misses                     136900                       # ITB inst misses
+system.cpu.itb.walker.walks                    136955                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                136955                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1083                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       119238                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       136955                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          136955    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       136955                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       120321                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 25178.697160                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       117467     97.63%     97.63% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         2593      2.16%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          161      0.13%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           40      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           38      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       120321                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   -243525796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      -243525796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   -243525796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        119238     99.10%     99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1083      0.90%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       120321                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136955                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       136955                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       120321                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       120321                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       257276                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    455989522                       # ITB inst hits
+system.cpu.itb.inst_misses                     136955                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               47427                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               47436                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1113                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    57667                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    56761                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    366615                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    364272                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                455428901                       # ITB inst accesses
-system.cpu.itb.hits                         455292001                       # DTB hits
-system.cpu.itb.misses                          136900                       # DTB misses
-system.cpu.itb.accesses                     455428901                       # DTB accesses
-system.cpu.numCycles                       2518825477                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                456126477                       # ITB inst accesses
+system.cpu.itb.hits                         455989522                       # DTB hits
+system.cpu.itb.misses                          136955                       # DTB misses
+system.cpu.itb.accesses                     456126477                       # DTB accesses
+system.cpu.numCycles                       2523007146                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   951433762                       # Number of instructions committed
-system.cpu.committedOps                    1118058358                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      97427430                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7769                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100859175256                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.647400                       # CPI: cycles per instruction
-system.cpu.ipc                               0.377729                       # IPC: instructions per cycle
+system.cpu.committedInsts                   953410832                       # Number of instructions committed
+system.cpu.committedOps                    1120287994                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      97416264                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7771                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100934517430                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.646296                       # CPI: cycles per instruction
+system.cpu.ipc                               0.377887                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16629                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1804872231                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       713953246                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          11184340                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.959663                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           330369377                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11184852                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.537215                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                    16631                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1807938889                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       715068257                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          11209162                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.959689                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           331084794                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11209674                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.535631                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4089991250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959663                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959689                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999921                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999921                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1387996074                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1387996074                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst    169370817                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       169370817                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst    152148495                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      152148495                       # number of WriteReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst       336885                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       336885                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst      4109295                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4109295                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst      4353813                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4353813                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst     321519312                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        321519312                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst    321519312                       # number of overall hits
-system.cpu.dcache.overall_hits::total       321519312                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst      8065146                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       8065146                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst      4327048                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4327048                       # number of WriteReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst      1245044                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1245044                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst       246250                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       246250                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1391009936                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1391009936                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    169770938                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       169770938                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    152453541                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      152453541                       # number of WriteReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst       337498                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       337498                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst      4114364                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4114364                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst      4358642                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4358642                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst     322224479                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        322224479                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    322224479                       # number of overall hits
+system.cpu.dcache.overall_hits::total       322224479                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      8085158                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       8085158                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      4338895                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4338895                       # number of WriteReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst      1245002                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1245002                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst       246013                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       246013                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.inst     12392194                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       12392194                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst     12392194                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12392194                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128575099737                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 128575099737                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 143976164605                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 143976164605                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst  29659207447                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  29659207447                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst   3578517253                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   3578517253                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.inst     12424053                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       12424053                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst     12424053                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12424053                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128824080247                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 128824080247                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 144514675403                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 144514675403                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst  29607413192                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  29607413192                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst   3571422003                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   3571422003                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       150500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       150500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 272551264342                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 272551264342                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 272551264342                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 272551264342                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst    177435963                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177435963                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst    156475543                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    156475543                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1581929                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      4355545                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4355545                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst      4353815                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4353815                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst    333911506                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    333911506                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst    333911506                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    333911506                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.045454                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.045454                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.027653                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027653                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst     0.787042                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.787042                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.056537                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056537                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.inst 273338755650                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 273338755650                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 273338755650                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 273338755650                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    177856096                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177856096                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    156792436                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    156792436                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst      1582500                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1582500                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst      4360377                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4360377                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst      4358644                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4358644                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    334648532                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    334648532                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    334648532                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    334648532                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.045459                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.045459                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.027673                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027673                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst     0.786731                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786731                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.056420                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.056420                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.037112                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037112                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.037112                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037112                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15942.067228                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15942.067228                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33273.530732                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33273.530732                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23821.814688                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23821.814688                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14532.049758                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14532.049758                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.037126                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037126                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.037126                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037126                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15933.402940                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33306.792490                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23781.016570                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14517.208452                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        75250                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75250                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21993.786116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 21993.786116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21993.786116                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22000.771862                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22000.771862                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22000.771862                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22000.771862                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -539,82 +629,82 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8574653                       # number of writebacks
-system.cpu.dcache.writebacks::total           8574653                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       754189                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       754189                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst      1894189                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1894189                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst          150                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          150                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst      2648378                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2648378                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst      2648378                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2648378                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7310957                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7310957                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      2432859                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2432859                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst      1244894                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244894                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst       246248                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       246248                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8593512                       # number of writebacks
+system.cpu.dcache.writebacks::total           8593512                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       755938                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       755938                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst      1899458                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1899458                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst          141                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::total          141                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst      2655396                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2655396                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst      2655396                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2655396                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7329220                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7329220                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      2439437                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2439437                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst      1244861                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1244861                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst       246009                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       246009                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9743816                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9743816                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9743816                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9743816                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102346476258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 102346476258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  73412590018                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  73412590018                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  27165305803                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst   3084334247                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3084334247                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9768657                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9768657                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9768657                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9768657                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102525908749                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  73694416463                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  73694416463                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  27114416558                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  27114416558                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst   3077572997                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3077572997                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       146500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 175759066276                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 175759066276                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 175759066276                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 175759066276                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5728692998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5728692998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   5585086250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5585086250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  11313779248                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11313779248                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.041203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015548                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015548                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786947                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.056537                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056537                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 176220325212                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 176220325212                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 176220325212                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 176220325212                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5727815999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5727815999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   5585117500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5585117500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  11312933499                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11312933499                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.041209                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041209                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015558                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015558                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.786642                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786642                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.056419                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056419                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029181                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.029181                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029181                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13999.053237                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13999.053237                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30175.439686                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30175.439686                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21821.380618                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21821.380618                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12525.316945                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12525.316945                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.029191                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029191                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.029191                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029191                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        73250                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73250                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18038.011625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18038.011625                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -622,58 +712,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24658250                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.931964                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           430254710                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24658762                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.448350                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       21183887000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.931964                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          24725990                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.931995                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           430886861                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24726502                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.426115                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       21192166000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.931995                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999867                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999867                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         479572253                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        479572253                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    430254710                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       430254710                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     430254710                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        430254710                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    430254710                       # number of overall hits
-system.cpu.icache.overall_hits::total       430254710                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24658772                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24658772                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total       24658772                       # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total      24658772                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 327794821206                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 327794821206                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 327794821206                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 327794821206                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 327794821206                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 327794821206                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    454913482                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total    454913482                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    454913482                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054205                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.054205                       # miss rate for ReadReq accesses
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-system.cpu.icache.overall_miss_rate::total     0.054205                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13293.233791                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13293.233791                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13293.233791                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13293.233791                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13293.233791                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         480339884                       # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_rate::total     0.054271                       # miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_miss_latency::total 13288.974753                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -682,189 +772,188 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24658772                       # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total     24658772                       # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total     24658772                       # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 278428644242                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 278428644242                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278428644242                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 278428644242                       # number of overall MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3812277750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3812277750                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   3812277750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054205                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054205                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11291.261554                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11291.261554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11291.261554                       # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11287.019446                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11287.019446                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11287.019446                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1618781                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65312.211718                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           40301488                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1682083                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.959274                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1618545                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65358.053127                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           40402502                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1681764                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            24.023883                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       5745484000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36153.667077                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   338.579375                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   416.289773                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 28403.675493                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.551661                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::total     0.996585                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63024                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2429                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5550                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.tags.tag_accesses        370683226                       # Number of tag accesses
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-system.cpu.l2cache.Writeback_hits::total      8574653                       # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total        10899                       # number of UpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst       144500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  53261752624                       # number of ReadExReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst      2383072                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.437206                       # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.782299                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782299                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.782463                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782463                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.299305                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.299305                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.018991                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.033397                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.032552                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006585                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.018991                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.033397                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.032552                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79527.955418                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75684.285080                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75775.207305                       # average ReadReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst     8.247314                       # average WriteInvalidateReq miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     8.247314                       # average WriteInvalidateReq miss latency
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11175.008324                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.300989                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        72250                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74673.056930                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74673.056930                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75101.813156                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78836.367880                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79527.955418                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75060.080480                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75101.813156                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74423.926717                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74781.655943                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74831.691446                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74781.655943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74831.691446                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -873,100 +962,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1377216                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1377216                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           23                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           23                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           23                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6426                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5473                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       442221                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       454120                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst       544275                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       544275                       # number of WriteInvalidateReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst        39165                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        39165                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1379367                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1379367                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           22                       # number of ReadReq MSHR hits
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+system.cpu.l2cache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6169                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.UpgradeReq_mshr_misses::total        38969                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       713266                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       713266                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6426                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5473                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      1155487                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1167386                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6426                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5473                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      1155487                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1167386                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    366985500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  27899659527                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  28693035027                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  12715651197                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst    392011653                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    392011653                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       719318                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       719318                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         6169                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5233                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      1161974                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1173376                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         6169                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5233                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      1161974                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1173376                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    413632000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    355518000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  27784615785                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  28553765785                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst  12667521943                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  12667521943                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst    390061961                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    390061961                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       120500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  44103603876                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  44103603876                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    366985500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  72003263403                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  72796638903                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    426390000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    366985500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  72003263403                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  72796638903                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   8007275752                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8007275752                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   5177466000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5177466000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst  13184741752                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13184741752                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.013727                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013564                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.437206                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.782299                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782299                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  44297743880                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  44297743880                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    413632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    355518000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  72082359665                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  72851509665                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    413632000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    355518000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  72082359665                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  72851509665                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   8006368251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8006368251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   5177591000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5177591000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst  13183959251                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13183959251                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006337                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.018271                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.013704                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013529                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst     0.434381                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.434381                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.782463                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782463                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.299305                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.299305                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.032551                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006585                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018991                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033397                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.032551                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63089.856716                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63183.817112                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23362.548706                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23362.548706                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.234087                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.234087                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.300989                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.300989                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006337                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.018271                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033495                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.032638                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006337                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.018271                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033495                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.032638                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62767.963803                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23426.098011                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.545049                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        60250                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61833.318672                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61833.318672                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
@@ -974,58 +1063,58 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       34021842                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      34013749                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33869                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33869                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8574653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244894                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        50067                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       34111380                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      34103268                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33870                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33870                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      8593512                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1351525                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1244861                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        49806                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        50069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2383072                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2383072                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49422067                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31180667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       697225                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2277994                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          83577953                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1581505984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1264852800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2305528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7806528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2856470840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      563561                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     46295151                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.002496                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.049898                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        49808                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2389846                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2389846                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     49557548                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     31248640                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       695589                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2279215                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          83780992                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1585841408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1267646988                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2291264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7787728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2863567388                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      571370                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     46410026                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.002490                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.049834                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           46179597     99.75%     99.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115554      0.25%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           46294483     99.75%     99.75% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115543      0.25%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       46295151                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32987192886                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       46410026                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    33063458385                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1194000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1149000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   37103090732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   37204558207                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15825165926                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15864083234                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     409755911                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     409855669                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1302956232                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1306481232                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40416                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40416                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40405                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40405                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1045,11 +1134,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231028                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231028                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231006                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354298                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354276                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1066,11 +1155,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334544                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334544                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334456                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334456                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492950                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492862                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1099,71 +1188,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042369212                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1042384689                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179072505                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179052263                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115495                       # number of replacements
-system.iocache.tags.tagsinuse               10.448328                       # Cycle average of tags in use
+system.iocache.tags.replacements               115484                       # number of replacements
+system.iocache.tags.tagsinuse               10.452585                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115511                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13141221301000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.519405                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.928922                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219963                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433058                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653020                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13141230176000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.516704                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.935881                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219794                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433493                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653287                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039983                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039983                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039884                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039884                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8850                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8887                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8839                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8876                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8850                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8890                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8839                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8879                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8850                       # number of overall misses
-system.iocache.overall_misses::total             8890                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8839                       # number of overall misses
+system.iocache.overall_misses::total             8879                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1921500610                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1926985610                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1924538358                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1930023358                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28836803097                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28836803097                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28851084068                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28851084068                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1921500610                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1927324610                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1924538358                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1930362358                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1921500610                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1927324610                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1924538358                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1930362358                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8850                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8887                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8839                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8876                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8850                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8890                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8839                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8879                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8850                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8890                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8839                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8879                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1178,54 +1267,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 216831.957916                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217442.920009                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 216796.919010                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 217732.589433                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 217407.631265                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 217118.712994                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 216796.919010                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        224459                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 217732.589433                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 217407.631265                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        225366                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27520                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27560                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.156214                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.177286                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8850                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8887                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8839                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8876                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8850                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8890                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8839                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8879                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8850                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8890                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8839                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8879                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1461199612                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1464760612                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1464798862                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1468359862                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23290267105                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23304534090                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23304534090                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1461199612                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1464943612                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1464798862                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1468542862                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1461199612                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1464943612                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1464798862                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1468542862                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1240,70 +1329,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 165395.073995                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 164785.558155                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 165395.073995                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              549050                       # Transaction distribution
-system.membus.trans_dist::ReadResp             549050                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33869                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33869                       # Transaction distribution
-system.membus.trans_dist::Writeback           1483846                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       650746                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       650746                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            39985                       # Transaction distribution
+system.membus.trans_dist::ReadReq              548979                       # Transaction distribution
+system.membus.trans_dist::ReadResp             548979                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33870                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33870                       # Transaction distribution
+system.membus.trans_dist::Writeback           1485997                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       647215                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       647215                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            39795                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           39987                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            712642                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           712642                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           39797                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            718688                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           718688                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4987889                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5118031                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335345                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335345                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5453376                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6926                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4994566                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5124714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5460180                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    200958508                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201129408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14066624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14066624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               215196032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3058                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3350229                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13852                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    201253164                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    201424076                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14075072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14075072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               215499148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2915                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3354632                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3350229    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3354632    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3350229                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113834500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3354632                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           113785000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               23328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5697498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5606499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         21359860992                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         21358745741                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        12431404244                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        12484485177                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186704495                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          186617737                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1314,11 +1403,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 4496ee012..3916ea1cc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.320621                       # Number of seconds simulated
-sim_ticks                                51320620981500                       # Number of ticks simulated
-final_tick                               51320620981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.320647                       # Number of seconds simulated
+sim_ticks                                51320647066500                       # Number of ticks simulated
+final_tick                               51320647066500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75246                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88415                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4505389037                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 667676                       # Number of bytes of host memory used
-host_seconds                                 11390.94                       # Real time elapsed on the host
-sim_insts                                   857117694                       # Number of instructions simulated
-sim_ops                                    1007133124                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  81694                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95992                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4889396972                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 723156                       # Number of bytes of host memory used
+host_seconds                                 10496.31                       # Real time elapsed on the host
+sim_insts                                   857487967                       # Number of instructions simulated
+sim_ops                                    1007562352                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       227264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       206272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5756576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          43073416                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        400256                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49663784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5756576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5756576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69780544                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       226752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       205312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5743904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          43053832                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        407232                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49637032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5743904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5743904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69718464                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69801124                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3551                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3223                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105899                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             673035                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6254                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                791962                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1090321                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69739044                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3543                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105701                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             672729                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                791544                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1089351                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1092894                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               112169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               839300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  967716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          112169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1359698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1091924                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4418                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               838918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  967194                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111922                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111922                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1358488                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1360099                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1359698                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              112169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              839701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2327815                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        791962                       # Number of read requests accepted
-system.physmem.writeReqs                      1696531                       # Number of write requests accepted
-system.physmem.readBursts                      791962                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1696531                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 50649920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     35648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 108090368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  49663784                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              108433892                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      557                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7601                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          35291                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               50546                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51810                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               46789                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               46242                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               46096                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               52242                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               46925                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               49452                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               44750                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               73148                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              48402                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51457                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              45806                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              48601                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42635                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              46504                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              106325                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              106592                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              106293                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              105191                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              106687                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              109171                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              103226                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              105745                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              103090                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              109771                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             107182                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             108709                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102154                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             106063                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             100653                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102060                       # Per bank write bursts
+system.physmem.bw_write::total                1358889                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1358488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4418                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111922                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              839319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2326083                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        791544                       # Number of read requests accepted
+system.physmem.writeReqs                      1694292                       # Number of write requests accepted
+system.physmem.readBursts                      791544                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1694292                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 50622848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     35968                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 107999616                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  49637032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              108290596                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      562                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6769                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          35256                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               48315                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               50150                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               46175                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               46946                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               45323                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               52981                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               47646                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               48748                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               44337                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               72322                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50834                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              50772                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              48451                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              47387                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              44232                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46363                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103979                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              105038                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              105754                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              105161                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              103562                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              108435                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              103867                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              105467                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              102645                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              108407                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             108582                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             107982                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             105330                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             105345                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             103911                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             104029                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          63                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51320619748500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51320645833500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  770677                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  770259                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1693958                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    524690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    218670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     33629                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     11094                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       783                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       320                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       222                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1691719                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    523893                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    218096                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8                       234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      139                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13                      123                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::15                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       49                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,122 +159,122 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                   105650                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::55                     1152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       519847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.358892                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.693203                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.458813                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         210597     40.51%     40.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       125304     24.10%     64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44434      8.55%     73.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23828      4.58%     77.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        16026      3.08%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10297      1.98%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8038      1.55%     84.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7736      1.49%     85.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        73587     14.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         519847                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         65806                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.026092                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       69.420005                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           65801     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    35494                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       519566                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.297267                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.561612                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.602188                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         210755     40.56%     40.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       125086     24.08%     64.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44418      8.55%     73.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23610      4.54%     77.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15941      3.07%     80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10357      1.99%     82.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8070      1.55%     84.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7704      1.48%     85.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        73625     14.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         519566                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         66165                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        11.954266                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-511           66159     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           65806                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         65806                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.665015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       22.295407                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       18.784846                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           44130     67.06%     67.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            6726     10.22%     77.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39            8110     12.32%     89.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            2086      3.17%     92.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            1158      1.76%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             536      0.81%     95.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             588      0.89%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             530      0.81%     97.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             479      0.73%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             220      0.33%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            383      0.58%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           149      0.23%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           276      0.42%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            79      0.12%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135           128      0.19%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            41      0.06%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            35      0.05%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            20      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            44      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            20      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            23      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            10      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            10      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           66165                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         66165                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.504330                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       22.270889                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       18.258332                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           44141     66.71%     66.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            6693     10.12%     76.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            8637     13.05%     89.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47            2199      3.32%     93.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55            1176      1.78%     94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             430      0.65%     95.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             581      0.88%     96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             510      0.77%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             438      0.66%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             204      0.31%     98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            335      0.51%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111           211      0.32%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119           211      0.32%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            55      0.08%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           142      0.21%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            25      0.04%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            36      0.05%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            19      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            38      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            22      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            24      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             2      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           65806                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15790981009                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30629824759                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3957025000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19953.10                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::256-263             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           66165                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15484448260                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30315360760                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3954910000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19576.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38703.10                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38326.23                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.10                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -282,36 +282,41 @@ system.physmem.busUtil                           0.02                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.05                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     603831                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1356638                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20623172.24                       # Average gap between requests
+system.physmem.avgWrQLen                        22.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     603455                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1355453                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20645225.93                       # Average gap between requests
 system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49368372569000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1713708100000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      238539960500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                1984348800                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                1945694520                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1082730000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1061638875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               3042748800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               3130163400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              5503010400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              5441139360                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3352013043600                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3352013043600                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1228384903950                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1226638074825                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29714838054000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29716370360250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34306848839550                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34306600114830                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.480867                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.476020                       # Core power per rank (mW)
+system.physmem_0.actEnergy                 1965463920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1072425750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3012968400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5451384240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1226370177675                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29716624044750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34306511542575                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.473889                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49436215199501                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713709140000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    170722374999                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 1962455040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1070784000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3156644400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5483576880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1227684074985                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29715471503250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34306844116395                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.480369                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49434282568001                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713709140000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    172653903249                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
@@ -334,16 +339,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               226428976                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         151471445                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12246087                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159886473                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104578062                       # Number of BTB hits
+system.cpu.branchPred.lookups               226505876                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         151515363                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12247822                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159926869                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104610641                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.407698                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31061917                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             345275                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.411548                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31076851                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             345252                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -365,27 +378,53 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.dtb.walker.walks            200647                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        200647                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       200647                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       200647    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       200647                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples   1467106000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0   1467106000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total   1467106000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K       155618     91.17%     91.17% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        15067      8.83%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       170685                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       200647                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       200647                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       170685                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       170685                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       371332                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            161215407                       # DTB read hits
-system.cpu.checker.dtb.read_misses             149229                       # DTB read misses
-system.cpu.checker.dtb.write_hits           146260364                       # DTB write hits
-system.cpu.checker.dtb.write_misses             51460                       # DTB write misses
+system.cpu.checker.dtb.read_hits            161284967                       # DTB read hits
+system.cpu.checker.dtb.read_misses             149209                       # DTB read misses
+system.cpu.checker.dtb.write_hits           146334371                       # DTB write hits
+system.cpu.checker.dtb.write_misses             51438                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            72721                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries            72843                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           7177                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           7088                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults             19208                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        161364636                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       146311824                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses        161434176                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       146385809                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 307475771                       # DTB hits
-system.cpu.checker.dtb.misses                  200689                       # DTB misses
-system.cpu.checker.dtb.accesses             307676460                       # DTB accesses
+system.cpu.checker.dtb.hits                 307619338                       # DTB hits
+system.cpu.checker.dtb.misses                  200647                       # DTB misses
+system.cpu.checker.dtb.accesses             307819985                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -407,8 +446,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits            857529218                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             120798                       # ITB inst misses
+system.cpu.checker.itb.walker.walks            120779                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        120779                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       120779                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       120779    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       120779                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples   1466561000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0   1466561000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total   1466561000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K       108783     98.83%     98.83% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M         1287      1.17%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       110070                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       120779                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       120779                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       110070                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       110070                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       230849                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            857899518                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             120779                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -417,20 +474,28 @@ system.cpu.checker.itb.flush_tlb                   20                       # Nu
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid        80016                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid            2058                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            52233                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries            52284                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        857650016                       # ITB inst accesses
-system.cpu.checker.itb.hits                 857529218                       # DTB hits
-system.cpu.checker.itb.misses                  120798                       # DTB misses
-system.cpu.checker.itb.accesses             857650016                       # DTB accesses
-system.cpu.checker.numCycles               1007708571                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        858020297                       # ITB inst accesses
+system.cpu.checker.itb.hits                 857899518                       # DTB hits
+system.cpu.checker.itb.misses                  120779                       # DTB misses
+system.cpu.checker.itb.accesses             858020297                       # DTB accesses
+system.cpu.checker.numCycles               1008137807                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -452,27 +517,95 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                    931379                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                931379                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16662                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       157071                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       405257                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       526122                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  1688.949521                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-32767       521687     99.16%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-65535         1343      0.26%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-98303         1868      0.36%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::98304-131071          570      0.11%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-163839          209      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::163840-196607          174      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-229375           58      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::229376-262143          108      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-294911            8      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::294912-327679            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-360447           36      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::360448-393215           45      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-425983           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       526122                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       461527                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       458117     99.26%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2510      0.54%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          628      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          155      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           42      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       461527                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 768881581580                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.740934                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.499994                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  767107299580     99.77%     99.77% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3     970542000      0.13%     99.90% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     364225500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     157799500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     120916000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11     94826000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     21620500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     42242000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2110500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 768881581580                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        157072     90.41%     90.41% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16662      9.59%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       173734                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       931379                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       931379                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       173734                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       173734                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1105113                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    171196432                       # DTB read hits
-system.cpu.dtb.read_misses                     671544                       # DTB read misses
-system.cpu.dtb.write_hits                   149025904                       # DTB write hits
-system.cpu.dtb.write_misses                    258759                       # DTB write misses
+system.cpu.dtb.read_hits                    171278986                       # DTB read hits
+system.cpu.dtb.read_misses                     671795                       # DTB read misses
+system.cpu.dtb.write_hits                   149102166                       # DTB write hits
+system.cpu.dtb.write_misses                    259584                       # DTB write misses
 system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72979                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       104                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10362                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    73098                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       106                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10235                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     68614                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171867976                       # DTB read accesses
-system.cpu.dtb.write_accesses               149284663                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69082                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171950781                       # DTB read accesses
+system.cpu.dtb.write_accesses               149361750                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         320222336                       # DTB hits
-system.cpu.dtb.misses                          930303                       # DTB misses
-system.cpu.dtb.accesses                     321152639                       # DTB accesses
+system.cpu.dtb.hits                         320381152                       # DTB hits
+system.cpu.dtb.misses                          931379                       # DTB misses
+system.cpu.dtb.accesses                     321312531                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -494,8 +627,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    360051885                       # ITB inst hits
-system.cpu.itb.inst_misses                     161655                       # ITB inst misses
+system.cpu.itb.walker.walks                    161841                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                161841                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1421                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       122616                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17088                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144753                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   980.521993                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  6808.510178                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       144225     99.64%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          131      0.09%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          321      0.22%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           37      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144753                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       141125                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 24337.182009                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767       134420     95.25%     95.25% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535         4577      3.24%     98.49% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303         1336      0.95%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071          512      0.36%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839           95      0.07%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607           88      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375           22      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143           28      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       141125                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 657209390884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.938693                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.240123                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     40327296652      6.14%      6.14% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    616846868232     93.86%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        34699000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          527000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 657209390884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        122616     98.85%     98.85% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1421      1.15%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       124037                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161841                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       161841                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       124037                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       124037                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       285878                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    360168043                       # ITB inst hits
+system.cpu.itb.inst_misses                     161841                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -504,111 +695,111 @@ system.cpu.itb.flush_tlb                           20                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               80016                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    2058                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53701                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    53745                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372863                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372581                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                360213540                       # ITB inst accesses
-system.cpu.itb.hits                         360051885                       # DTB hits
-system.cpu.itb.misses                          161655                       # DTB misses
-system.cpu.itb.accesses                     360213540                       # DTB accesses
-system.cpu.numCycles                       1576874693                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                360329884                       # ITB inst accesses
+system.cpu.itb.hits                         360168043                       # DTB hits
+system.cpu.itb.misses                          161841                       # DTB misses
+system.cpu.itb.accesses                     360329884                       # DTB accesses
+system.cpu.numCycles                       1576983833                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          648679854                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1010290403                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   226428976                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135639979                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     852655064                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26160452                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3389644                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                26807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9240220                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1021673                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 359662567                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6136086                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   47510                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1528093850                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.774691                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.161324                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          648826167                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1010661506                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   226505876                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135687492                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     852638415                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26165882                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3403646                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9234109                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1027275                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 359779044                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6134765                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47734                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1528240089                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.774898                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.161407                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                965958627     63.21%     63.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215893777     14.13%     77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70817340      4.63%     81.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                275424106     18.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                965897706     63.20%     63.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215974848     14.13%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70846962      4.64%     81.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                275520573     18.03%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1528093850                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.143594                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.640692                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                527180052                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             504302107                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 436284853                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              51059674                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9267164                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33905862                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3872221                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1095429909                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29099398                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9267164                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                572442291                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                46180186                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      363186865                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 441948285                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              95069059                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1075584704                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6788495                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               4945824                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 318864                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 589123                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               42956715                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            21763                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1023437611                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1659121727                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1272319582                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1685396                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             957674620                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65762988                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27435128                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23745394                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 104747763                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            175168030                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           152601618                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9963388                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9061948                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1040022976                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27737741                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1056135120                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3300763                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        53598061                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33623556                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         314928                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1528093850                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.691145                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.927830                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1528240089                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.143632                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.640883                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                527342057                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             504093722                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 436470729                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              51063982                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9269599                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33921165                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3872416                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1095869891                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29092135                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9269599                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                572608237                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46122541                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363160924                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 442135288                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              94943500                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1076024490                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6785579                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               4940621                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 314117                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 587788                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               42830435                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            21754                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1023810702                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1659713955                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1272840679                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1685189                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             958043687                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65767012                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27437914                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23747073                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 104751050                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            175241778                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           152679763                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9977994                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9053000                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1040458161                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27741753                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1056586315                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3302783                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53612674                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33630584                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         315276                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1528240089                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.691375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.927907                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           873977548     57.19%     57.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           338098484     22.13%     79.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           236626258     15.49%     94.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72801252      4.76%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6571176      0.43%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19132      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           873840021     57.18%     57.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           338263818     22.13%     79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           236701790     15.49%     94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72838134      4.77%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6577115      0.43%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19211      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1528093850                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1528240089                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58371154     35.14%     35.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100885      0.06%     35.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26756      0.02%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58408451     35.14%     35.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100871      0.06%     35.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26760      0.02%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
@@ -631,19 +822,19 @@ system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # at
 system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              767      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44544414     26.81%     62.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              63075062     37.97%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              763      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44563063     26.81%     62.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63134312     37.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 2      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             727332382     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2546997      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                123061      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                12      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             727619955     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2547357      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                123270      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -665,102 +856,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         120668      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         120690      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            175096796     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150915164     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            175181818     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150993162     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1056135120                       # Type of FU issued
-system.cpu.iq.rate                           0.669765                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   166119038                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157290                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3807304115                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1120557954                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1038099529                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2479775                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             941816                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       907592                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1220693938                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1560218                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4348848                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1056586315                       # Type of FU issued
+system.cpu.iq.rate                           0.670005                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   166234220                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157331                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3808470802                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1121012820                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1038530652                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2478919                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             941723                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       907476                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1221261060                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1559463                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4354414                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13855252                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14404                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142361                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6337064                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13859524                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14300                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143284                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6341204                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2552747                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1859122                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2565738                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1859911                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9267164                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6379535                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3965873                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1067985048                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9269599                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6359819                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3950891                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1068424262                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             175168030                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            152601618                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23314125                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  62024                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3832996                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142361                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3691152                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5135953                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8827105                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1044930592                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             171186057                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10287379                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             175241778                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            152679763                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23316187                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  61516                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3818793                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143284                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3692717                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5135549                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8828266                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1045377154                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             171268732                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10291027                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        224331                       # number of nop insts executed
-system.cpu.iew.exec_refs                    320208959                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                198322451                       # Number of branches executed
-system.cpu.iew.exec_stores                  149022902                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.662659                       # Inst execution rate
-system.cpu.iew.wb_sent                     1039793819                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1039007121                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 442154878                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 715627882                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        224348                       # number of nop insts executed
+system.cpu.iew.exec_refs                    320367802                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                198404489                       # Number of branches executed
+system.cpu.iew.exec_stores                  149099070                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.662897                       # Inst execution rate
+system.cpu.iew.wb_sent                     1040225395                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1039438128                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 442335874                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 715873221                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.658903                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.617856                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.659130                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.617897                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51471265                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27422813                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8433025                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1516084212                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.664299                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.291990                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51477037                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27426477                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8434480                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1516228883                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.664519                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.292276                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    998537580     65.86%     65.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    291350566     19.22%     85.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121957393      8.04%     93.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36696853      2.42%     95.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28610485      1.89%     97.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14255849      0.94%     98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8557612      0.56%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4232636      0.28%     99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11885238      0.78%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    998506921     65.85%     65.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    291444279     19.22%     85.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121999456      8.05%     93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36692084      2.42%     95.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28614798      1.89%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14261229      0.94%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8588058      0.57%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4227240      0.28%     99.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11894818      0.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1516084212                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            857117694                       # Number of instructions committed
-system.cpu.commit.committedOps             1007133124                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1516228883                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            857487967                       # Number of instructions committed
+system.cpu.commit.committedOps             1007562352                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      307577331                       # Number of memory references committed
-system.cpu.commit.loads                     161312777                       # Number of loads committed
-system.cpu.commit.membars                     7014752                       # Number of memory barriers committed
-system.cpu.commit.branches                  191334741                       # Number of branches committed
-system.cpu.commit.fp_insts                     896026                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 925144388                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25493443                       # Number of function calls committed.
+system.cpu.commit.refs                      307720812                       # Number of memory references committed
+system.cpu.commit.loads                     161382253                       # Number of loads committed
+system.cpu.commit.membars                     7017472                       # Number of memory barriers committed
+system.cpu.commit.branches                  191417503                       # Number of branches committed
+system.cpu.commit.fp_insts                     895898                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 925548459                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25509836                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        697181314     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2164633      0.21%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98281      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        697466429     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2165110      0.21%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98436      0.01%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
@@ -787,233 +978,232 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       161312777     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      146264554     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       161382253     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      146338559     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1007133124                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11885238                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total        1007562352                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11894818                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2555181565                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2129123637                       # The number of ROB writes
-system.cpu.timesIdled                         8137810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        48780843                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101064367400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   857117694                       # Number of Instructions Simulated
-system.cpu.committedOps                    1007133124                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.839741                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.839741                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.543555                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.543555                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1237020079                       # number of integer regfile reads
-system.cpu.int_regfile_writes               738429838                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1457787                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 228125574                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                228731881                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              5247037954                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27486572                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9822538                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.985265                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           286045243                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9823050                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.119799                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.985265                       # Average occupied blocks per requestor
+system.cpu.rob.rob_reads                   2555751551                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2129995502                       # The number of ROB writes
+system.cpu.timesIdled                         8137427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        48743744                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101064310429                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   857487967                       # Number of Instructions Simulated
+system.cpu.committedOps                    1007562352                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.839074                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.839074                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.543752                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.543752                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237547063                       # number of integer regfile reads
+system.cpu.int_regfile_writes               738733253                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1457540                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782548                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 228190122                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                228796042                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              5248690758                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27489325                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9822587                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.985266                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           286182485                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9823099                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.133625                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1485676250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.985266                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          380                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1249214859                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1249214859                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    148712432                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       148712432                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    129479125                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      129479125                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       381594                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        381594                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324870                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       324870                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352883                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3352883                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3750315                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3750315                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     278191557                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        278191557                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    278573151                       # number of overall hits
-system.cpu.dcache.overall_hits::total       278573151                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9502058                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9502058                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11465174                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11465174                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1197022                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1197022                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233022                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1233022                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       449448                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1249763399                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1249763399                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    148780016                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       148780016                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    129548885                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      129548885                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       381333                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        381333                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324563                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       324563                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352422                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3352422                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3751270                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3751270                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     278328901                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        278328901                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    278710234                       # number of overall hits
+system.cpu.dcache.overall_hits::total       278710234                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9497038                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9497038                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11468447                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11468447                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1197141                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1197141                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233328                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1233328                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       450623                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       450623                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20967232                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20967232                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22164254                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22164254                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 140935225401                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 322991667568                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38675981880                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38675981880                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6315194753                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     20965485                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20965485                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22162626                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22162626                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 140713387644                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 321962948230                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38655244426                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38655244426                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6327424004                       # number of LoadLockedReq miss cycles
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 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 463926892969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 463926892969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 463926892969                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 463926892969                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    158214490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    158214490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140944299                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140944299                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578616                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1578616                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3802331                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3802331                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3750320                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3750320                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    299158789                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    299158789                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    300737405                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    300737405                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060058                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060058                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081345                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081345                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758273                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.758273                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791468                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791468                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118203                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 462676335874                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 462676335874                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 462676335874                       # number of overall miss cycles
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+system.cpu.dcache.SoftPFReq_accesses::total      1578474                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total    300872860                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060003                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060003                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081327                       # miss rate for WriteReq accesses
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+system.cpu.dcache.SoftPFReq_miss_rate::total     0.758417                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791665                       # miss rate for WriteInvalidateReq accesses
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 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070087                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070087                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073700                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073700                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070050                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070050                       # miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187                       # average ReadReq miss latency
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+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22126.282237                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20931.310973                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     21466802                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22068.477589                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20876.422129                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     21410972                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1401851                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1402072                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.313184                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.270950                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7593763                       # number of writebacks
-system.cpu.dcache.writebacks::total           7593763                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4321399                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4321399                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9425025                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9425025                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7055                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7055                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219414                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219414                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13746424                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13746424                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13746424                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13746424                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5180659                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5180659                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2040149                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2040149                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190231                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1190231                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1225967                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1225967                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230034                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7597183                       # number of writebacks
+system.cpu.dcache.writebacks::total           7597183                       # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total       220034                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total     13745551                       # number of overall MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230589                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total      8411039                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70208074682                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  70208074682                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53752252884                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53752252884                       # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18853760746                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2809792248                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2809792248                       # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total  70110899674                       # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53589743024                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18780468745                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18780468745                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2813771248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2813771248                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 123960327566                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 142814088312                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729213249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729213249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587099983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587099983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316313232                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316313232                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014475                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014475                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753971                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753971                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060498                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 123700642698                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 142481111443                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729238749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729238749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587095483                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587095483                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316334232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316334232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.754116                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.754116                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060633                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060633                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024137                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024137                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027968                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027968                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024123                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024123                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027953                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027953                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1021,276 +1211,277 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15082585                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.954216                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           343840613                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15083097                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.796420                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       14175734000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.954216                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          15084162                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.954207                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           343955623                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15084674                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.801661                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       14174936000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.954207                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         374724467                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        374724467                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    343840613                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       343840613                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     343840613                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        343840613                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    343840613                       # number of overall hits
-system.cpu.icache.overall_hits::total       343840613                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15800655                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15800655                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15800655                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15800655                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15800655                       # number of overall misses
-system.cpu.icache.overall_misses::total      15800655                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208208668907                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208208668907                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208208668907                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208208668907                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208208668907                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    359641268                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    359641268                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    359641268                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    359641268                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    359641268                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    359641268                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043934                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.043934                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.043934                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.043934                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.043934                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.043934                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13177.217584                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13177.217584                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10839                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         374842526                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        374842526                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    343955623                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       343955623                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total       343955623                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15802123                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15802123                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15802123                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15802123                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15802123                       # number of overall misses
+system.cpu.icache.overall_misses::total      15802123                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208192919846                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208192919846                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208192919846                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208192919846                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208192919846                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    359757746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    359757746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    359757746                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    359757746                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    359757746                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    359757746                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043924                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043924                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043924                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043924                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043924                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043924                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13174.996793                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13174.996793                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        11061                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               972                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               978                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    11.151235                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    11.309816                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717456                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       717456                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       717456                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       717456                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       717456                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       717456                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15083199                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15083199                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15083199                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15083199                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15083199                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15083199                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 171815580989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 171815580989                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041940                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041940                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041940                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_hits::total       717343                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       717343                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1412899000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1412899000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041930                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1167362                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65297.852107                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29065274                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1230222                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.626040                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       2430272000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   320.853018                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   490.286692                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7518.567341                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.569512                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004896                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007481                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.114724                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.299753                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1023          285                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62575                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          285                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          565                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2655                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5044                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54243                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004349                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954819                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        273181992                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_hits::total       22433008                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7593763                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7593763                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       728839                       # number of WriteInvalidateReq hits
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-system.cpu.l2cache.UpgradeReq_hits::total         9472                       # number of UpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        36000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        36000                       # average SCUpgradeReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1299,114 +1490,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       983690                       # number of writebacks
-system.cpu.l2cache.writebacks::total           983690                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24019252031                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345346475                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345346475                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29577738885                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29577738885                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    220243499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5475082762                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47837062889                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  53771748899                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    220243499                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5475082762                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47837062889                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  53771748899                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289733251                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393715501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176071500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176071500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465804751                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569787001                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.039032                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784600                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29394156879                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29394156879                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    221074750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5441255518                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47510992143                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  53413408910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    221074750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5441255518                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47510992143                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  53413408910                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289749251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393613751                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465822751                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569687251                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.038843                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015245                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784594                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784594                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208413                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208413                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030898                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030898                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030869                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030869                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1416,32 +1607,32 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23341232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23333163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       23340437                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23332371                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7593763                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332631                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1225967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      7597183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332844                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1226180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43948                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43982                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1999866                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1999866                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30208899                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27463876                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       731462                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1967033                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          60371270                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965659760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1114918084                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2404176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6408648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2089390668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      611685                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     34508223                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        9.003348                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.057762                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43953                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2001716                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2001716                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30212060                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27467336                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       733813                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1968769                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          60381978                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965760880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1115140164                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2421064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6427336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2089749444                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      606880                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     34513008                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        9.003347                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.057757                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
@@ -1452,26 +1643,26 @@ system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Re
 system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9           34392703     99.67%     99.67% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::10            115520      0.33%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9           34397489     99.67%     99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10            115519      0.33%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value           10                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       34508223                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    26206492236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       34513008                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    26212619005                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1177500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1180500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22671590732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22673982421                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13674088224                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13673864954                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     431886005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     432131982                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1166711358                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1166119344                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40382                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40382                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40381                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40381                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1491,11 +1682,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354228                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1512,11 +1703,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492678                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492670                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1545,71 +1736,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042360658                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1042349161                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179004169                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179004202                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115462                       # number of replacements
-system.iocache.tags.tagsinuse               10.424613                       # Cycle average of tags in use
+system.iocache.tags.replacements               115461                       # number of replacements
+system.iocache.tags.tagsinuse               10.424617                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115477                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13092189065000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544618                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879995                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13092188806000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544621                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879997                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651539                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039677                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039668                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8815                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8855                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
-system.iocache.overall_misses::total             8856                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8815                       # number of overall misses
+system.iocache.overall_misses::total             8855                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1927411613                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1932938613                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1934147111                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1939674111                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28910124876                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28899223848                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28899223848                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1927411613                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1933277613                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1934147111                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1940013111                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1927411613                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1933277613                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1934147111                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1940013111                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8815                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8855                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8815                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8855                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1624,54 +1815,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 218337.130125                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 219122.696679                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 219086.743196                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 218301.446816                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        226675                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 219086.743196                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        225873                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27646                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27588                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.199197                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.187364                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8815                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8855                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8815                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8855                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1468863623                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1472466623                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1475641121                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1479244121                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1468863623                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1472649623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1475641121                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1479427121                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1468863623                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1472649623                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1475641121                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1479427121                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1686,70 +1877,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              412825                       # Transaction distribution
-system.membus.trans_dist::ReadResp             412825                       # Transaction distribution
+system.membus.trans_dist::ReadReq              411277                       # Transaction distribution
+system.membus.trans_dist::ReadResp             411277                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
-system.membus.trans_dist::Writeback           1090321                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       603637                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       603637                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35296                       # Transaction distribution
+system.membus.trans_dist::Writeback           1089351                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       602368                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       602368                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35261                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35298                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            416163                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           416163                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35263                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            417183                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           417183                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3625442                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3755550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4090619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3620810                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3750918                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4086095                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    144046540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144217012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14051136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14051136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               158268148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3264                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2503253                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    143869516                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144039988                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14058112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14058112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               158098100                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3154                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2500418                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2503253    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2500418    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2503253                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109702500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2500418                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109711500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5437999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5440999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         16337638979                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         16316164477                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7836649146                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7830132924                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186565831                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          186594798                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index e64b12ad0..828771ce9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,178 +1,178 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.422278                       # Number of seconds simulated
-sim_ticks                                47422277747000                       # Number of ticks simulated
-final_tick                               47422277747000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.345385                       # Number of seconds simulated
+sim_ticks                                47345385235500                       # Number of ticks simulated
+final_tick                               47345385235500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91986                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4717167353                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 870208                       # Number of bytes of host memory used
-host_seconds                                 10053.13                       # Real time elapsed on the host
-sim_insts                                   924745220                       # Number of instructions simulated
-sim_ops                                    1087564829                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 106392                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125133                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5453309126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 767036                       # Number of bytes of host memory used
+host_seconds                                  8681.96                       # Real time elapsed on the host
+sim_insts                                   923688991                       # Number of instructions simulated
+sim_ops                                    1086395427                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       123008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        83392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1145824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         12461528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     54523392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       250240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       244864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           679904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         13804768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     35481280                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        451200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            119249400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1145824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       679904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1825728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     92428416                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       161152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       146432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4268768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         16023832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     20180672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       179840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       156416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3463536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         11559072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     14510464                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        437312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             71087496                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4268768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3463536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7732304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     86253568                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          92449232                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1922                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1303                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             33856                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            194733                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       851928                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         3826                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10667                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            215714                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       554395                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7050                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1879304                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1444194                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          86274384                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2518                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2288                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             82652                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            250394                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       315323                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2444                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             54162                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            180625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       226726                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6833                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1126775                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1347712                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1446797                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1758                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               24162                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              262778                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      1149742                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          5277                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          5163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               14337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              291103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       748199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9515                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2514628                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          24162                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          14337                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              38499                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1949051                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1350315                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3404                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               90162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              338445                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       426244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               73155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              244144                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       306481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9237                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1501466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          90162                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          73155                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             163317                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1821795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                440                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1949489                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1949051                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              24162                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             263217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      1149742                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         5277                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         5163                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              14337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             291103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       748199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4464118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1879304                       # Number of read requests accepted
-system.physmem.writeReqs                      1600997                       # Number of write requests accepted
-system.physmem.readBursts                     1879304                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1600997                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                120227392                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     48064                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 101998144                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 119249400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              102318032                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      751                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7249                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          97584                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              111371                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              133364                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              107237                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              129396                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              116369                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              129089                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              116664                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              120571                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              118226                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              133705                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              98234                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             110272                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             110364                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             124983                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             111960                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             106748                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               99185                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              109011                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               97054                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              108172                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               98286                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              106076                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              100140                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              103851                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               98795                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               98239                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              89198                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              97505                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              95822                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102116                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              95043                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              95228                       # Per bank write bursts
+system.physmem.bw_write::total                1822234                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1821795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3404                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3093                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              90162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             338885                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       426244                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3798                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              73155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             244144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       306481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3323700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1126775                       # Number of read requests accepted
+system.physmem.writeReqs                      2040290                       # Number of write requests accepted
+system.physmem.readBursts                     1126775                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2040290                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 72094336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19264                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 130093376                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  71087496                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              130432784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      301                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7556                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         121134                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               65675                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               75833                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               67256                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               67290                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               71240                       # Per bank write bursts
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+system.physmem.perBankRdBursts::7               67787                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               61707                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               85775                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              61014                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              72520                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              65793                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              74631                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              69278                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              71471                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              122526                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              130111                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              125889                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              127486                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              126972                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              136977                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              126845                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              128268                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              123854                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              125736                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             125360                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             131761                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             119984                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             126166                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             125889                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             128885                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47422276363500                       # Total gap between requests
+system.physmem.numWrRetry                         614                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47345383810500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
-system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
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 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1857934                       # Read request sizes (log2)
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 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
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 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1598394                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::31                        1                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
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 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -188,184 +188,141 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       975956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      227.699905                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.562466                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     280.517231                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         518192     53.10%     53.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       197775     20.26%     73.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        73464      7.53%     80.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        39205      4.02%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        32875      3.37%     88.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        20645      2.12%     90.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14690      1.51%     91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        16974      1.74%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        62136      6.37%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         975956                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         85700                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.919883                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       65.914571                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           85693     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            4      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::53                     3550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     3131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     2559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     2104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                     1878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                     1591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     1280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     1141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     1049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                     1018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                     1502                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1131657                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      178.664737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     108.493979                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     249.059793                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         718344     63.48%     63.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       219262     19.38%     82.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        56669      5.01%     87.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        25497      2.25%     90.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20148      1.78%     91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11584      1.02%     92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9545      0.84%     93.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8895      0.79%     94.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        61713      5.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1131657                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         74075                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        15.207155                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       65.468886                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           74072    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           85700                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         85700                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.596511                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.559355                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.221946                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           76419     89.17%     89.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4825      5.63%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             861      1.00%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             776      0.91%     96.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             493      0.58%     97.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             137      0.16%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             117      0.14%     97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             137      0.16%     97.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             585      0.68%     98.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              72      0.08%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              76      0.09%     98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              72      0.08%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             110      0.13%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              48      0.06%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              42      0.05%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              81      0.09%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             124      0.14%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              28      0.03%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              35      0.04%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              50      0.06%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             194      0.23%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            14      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            23      0.03%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            14      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            54      0.06%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119            16      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            21      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127            26      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131           106      0.12%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            28      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             8      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             9      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            15      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151            15      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163            11      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             6      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             4      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             6      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           85700                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   131185455773                       # Total ticks spent queuing
-system.physmem.totMemAccLat              166408324523                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9392765000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       69833.25                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           74075                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         74075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.441228                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.793858                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev      451.068024                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-1023          74039     99.95%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1024-2047           13      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2048-3071            9      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3072-4095            5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4096-5119            2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5120-6143            2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26624-27647            1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33792-34815            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64512-65535            3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           74075                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    56140564025                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77261951525                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5632370000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       49837.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  88583.25                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.15                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.16                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  68587.43                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.52                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.75                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.50                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.75                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.75                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1529879                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    966437                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  60.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13625912.35                       # Average gap between requests
-system.physmem.pageHitRate                      71.89                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     45568926392500                       # Time in different power states
-system.physmem.memoryStateTime::REF      1583533900000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      269814192000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                3837713040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                3540506760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                2093990250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1931824125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               7519675800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               7132967400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              5325102000                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              5002210080                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3097392308400                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3097392308400                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1175879799405                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1172220553305                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          27421890099000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          27425099964000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            31713938687895                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            31712320334070                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.756196                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.722070                       # Core power per rank (mW)
+system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     851046                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1176475                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.55                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14949293.37                       # Average gap between requests
+system.physmem.pageHitRate                      64.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4318120800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2356117500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4401423000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               6642421200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3092370278400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1163515422960                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27386602512000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31660206295860                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.707358                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45559855793000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1580966400000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    204562609000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 4237153200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2311938750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4385027400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               6529429440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3092370278400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1165548686490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27384818947500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31660201461180                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.707256                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45556862760500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1580966400000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    207555509500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
@@ -398,16 +355,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              136692903                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         91051024                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6675955                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            96641264                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               62499971                       # Number of BTB hits
+system.cpu0.branchPred.lookups              145356452                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         96435082                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          7088203                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           101789401                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               67765064                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            64.672137                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               18343531                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            188881                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            66.573792                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               20004195                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            205158                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -429,27 +394,97 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   580611                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               580611                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13679                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        93135                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       259311                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       321300                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  1669.368192                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-32767       317448     98.80%     98.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-65535         2037      0.63%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-98303          845      0.26%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-131071          576      0.18%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-163839          232      0.07%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::163840-196607           45      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-229375           28      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::229376-262143           26      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-294911           42      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::294912-327679            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-360447            9      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       321300                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       293805                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       291279     99.14%     99.14% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         1809      0.62%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          367      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          189      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          105      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           25      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       293805                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 521650035508                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.610400                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.526555                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 520697119508     99.82%     99.82% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    543124000      0.10%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    195186500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7     85165500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     70245500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     34070500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     11934000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     12740000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       448500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 521650035508                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        93135     87.19%     87.19% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        13679     12.81%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       106814                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       580611                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       580611                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       106814                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       106814                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       687425                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    98285730                       # DTB read hits
-system.cpu0.dtb.read_misses                    371363                       # DTB read misses
-system.cpu0.dtb.write_hits                   82429878                       # DTB write hits
-system.cpu0.dtb.write_misses                   160428                       # DTB write misses
+system.cpu0.dtb.read_hits                   105404836                       # DTB read hits
+system.cpu0.dtb.read_misses                    420652                       # DTB read misses
+system.cpu0.dtb.write_hits                   86890500                       # DTB write hits
+system.cpu0.dtb.write_misses                   159959                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   34259                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      107                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  6211                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   40944                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      605                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8089                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    37781                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                98657093                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82590306                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    40127                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               105825488                       # DTB read accesses
+system.cpu0.dtb.write_accesses               87050459                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        180715608                       # DTB hits
-system.cpu0.dtb.misses                         531791                       # DTB misses
-system.cpu0.dtb.accesses                    181247399                       # DTB accesses
+system.cpu0.dtb.hits                        192295336                       # DTB hits
+system.cpu0.dtb.misses                         580611                       # DTB misses
+system.cpu0.dtb.accesses                    192875947                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -471,533 +506,588 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   214588445                       # ITB inst hits
-system.cpu0.itb.inst_misses                     81035                       # ITB inst misses
+system.cpu0.itb.walker.walks                    84622                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                84622                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          994                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61729                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         9515                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        75107                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1146.297948                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8819.384812                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        74551     99.26%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          182      0.24%     99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          223      0.30%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          112      0.15%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839            5      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375           12      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        75107                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        72238                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        70635     97.78%     97.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1318      1.82%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          148      0.20%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           80      0.11%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           29      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        72238                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 405678068016                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.851697                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.355553                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    60184359568     14.84%     14.84% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   345473805948     85.16%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       18871000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1025500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4           6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 405678068016                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        61729     98.42%     98.42% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          994      1.58%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        62723                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        84622                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        84622                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        62723                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        62723                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       147345                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   229226252                       # ITB inst hits
+system.cpu0.itb.inst_misses                     84622                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24176                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   29308                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   217359                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   225641                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               214669480                       # ITB inst accesses
-system.cpu0.itb.hits                        214588445                       # DTB hits
-system.cpu0.itb.misses                          81035                       # DTB misses
-system.cpu0.itb.accesses                    214669480                       # DTB accesses
-system.cpu0.numCycles                       723605959                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               229310874                       # ITB inst accesses
+system.cpu0.itb.hits                        229226252                       # DTB hits
+system.cpu0.itb.misses                          84622                       # DTB misses
+system.cpu0.itb.accesses                    229310874                       # DTB accesses
+system.cpu0.numCycles                       787784387                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          84128505                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     603958712                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  136692903                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          80843502                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    610845531                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               14389096                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1590613                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              145998                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6064926                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       691327                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       308415                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                214371554                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1629958                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  26989                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         710969863                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.995603                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.223531                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          93175923                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     642526185                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  145356452                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          87769259                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    654798115                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               15283958                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1702071                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              255624                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6308926                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       745987                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       671334                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                229000663                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1782311                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  27660                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         765299959                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.983676                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.220176                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               371943625     52.31%     52.31% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               132005479     18.57%     70.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                45223870      6.36%     77.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               161796889     22.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               404626902     52.87%     52.87% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               139960190     18.29%     71.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                49291261      6.44%     77.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               171421606     22.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           710969863                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.188905                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.834651                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               100859820                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            341670501                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                226894689                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             36450722                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5094131                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19684552                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2143149                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             625299942                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             23465263                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5094131                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               135677386                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               49836875                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     228336608                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                227963533                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             64061330                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             608231586                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              5949574                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              8548374                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                231810                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                263882                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              30185355                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           12581                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          579905224                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            937754781                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       718843517                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups          1013139                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            522903039                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                57002179                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15055979                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13152707                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 73956769                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            99026206                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85770687                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          8763922                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         7686093                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 586686508                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15156086                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                590156830                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2681738                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       50409396                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     34542071                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        266225                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    710969863                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.830073                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.072195                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           765299959                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.184513                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.815612                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               110781464                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            368356745                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                241543971                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             39160465                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5457314                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            20998766                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2230758                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             666506782                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             24554495                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5457314                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               147799214                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               53385858                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     247347968                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                243020975                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             68288630                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             648373688                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6354822                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              9340488                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                358878                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                691420                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              31770877                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           13042                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          618836498                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups           1000163983                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       765756832                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           980941                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            557557100                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                61279388                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          16104693                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13959035                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 79116837                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           106280749                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           90455195                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9698755                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8363084                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 625354037                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           16149817                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                628774014                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2896491                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       54006760                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     37569824                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        287316                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    765299959                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.821605                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.068919                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          390297771     54.90%     54.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          132320625     18.61%     73.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          115120103     16.19%     89.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           65333726      9.19%     98.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            7893369      1.11%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               4269      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          423230722     55.30%     55.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          141522259     18.49%     73.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          122647115     16.03%     89.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           69647275      9.10%     98.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            8247243      1.08%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               5342      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                  3      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      710969863                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      765299959                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               61459839     45.63%     45.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 50531      0.04%     45.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  24866      0.02%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              22      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              34471783     25.59%     71.27% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             38693635     28.73%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               65414267     45.68%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 59912      0.04%     45.72% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  17829      0.01%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              19      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              37349884     26.08%     71.81% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             40363750     28.19%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            403696370     68.40%     68.40% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1373917      0.23%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                72713      0.01%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  2      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         82685      0.01%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           101222055     17.15%     85.82% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           83709039     14.18%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            430163495     68.41%     68.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1578221      0.25%     68.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                81407      0.01%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                125      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         78656      0.01%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           108646479     17.28%     85.97% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           88225631     14.03%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             590156830                       # Type of FU issued
-system.cpu0.iq.rate                          0.815578                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  134700676                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.228246                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2027250728                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        651818194                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    574107974                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1415207                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            570288                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       525567                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             723981962                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 875543                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2649036                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             628774014                       # Type of FU issued
+system.cpu0.iq.rate                          0.798155                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  143205661                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.227754                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2167577171                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        695106277                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    611404783                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1372966                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            554126                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       508083                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             771129089                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 850586                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2930031                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     12005066                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        15997                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       137574                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      5832630                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     13213228                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        17078                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       150900                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      6091069                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2633268                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      3783846                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2819130                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4221569                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5094131                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                6289107                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              4809356                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          601961701                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5457314                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                7826815                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              3783393                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          641629807                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             99026206                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85770687                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12881584                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 63147                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              4682481                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        137574                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       1984191                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2898838                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4883029                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            582493668                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             98279194                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7144205                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            106280749                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            90455195                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13677015                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 59030                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              3651240                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        150900                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2214888                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3025224                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5240112                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            620548589                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            105398618                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7653008                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       119107                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   180711366                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               110157991                       # Number of branches executed
-system.cpu0.iew.exec_stores                  82432172                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.804987                       # Inst execution rate
-system.cpu0.iew.wb_sent                     575359382                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    574633541                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                278757047                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                457962623                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       125953                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   192287971                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               117275797                       # Number of branches executed
+system.cpu0.iew.exec_stores                  86889353                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.787714                       # Inst execution rate
+system.cpu0.iew.wb_sent                     612710943                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    611912866                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                297952907                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                488842231                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.794125                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.608690                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.776752                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609507                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       46943290                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14889861                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4575538                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    702085405                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.780670                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.579297                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       50177444                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15862501                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4903538                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    755787028                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.772749                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.571704                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    463334360     65.99%     65.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    122538358     17.45%     83.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     53278812      7.59%     91.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     18006181      2.56%     93.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13261797      1.89%     95.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      8597155      1.22%     96.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5895517      0.84%     97.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3809437      0.54%     98.10% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     13363788      1.90%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    501065306     66.30%     66.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    130810768     17.31%     83.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     56911365      7.53%     91.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     19253126      2.55%     93.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     13929285      1.84%     95.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      9339201      1.24%     96.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6281388      0.83%     97.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      4033068      0.53%     98.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14163521      1.87%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    702085405                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           466411686                       # Number of instructions committed
-system.cpu0.commit.committedOps             548096953                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    755787028                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           497564314                       # Number of instructions committed
+system.cpu0.commit.committedOps             584033993                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     166959196                       # Number of memory references committed
-system.cpu0.commit.loads                     87021139                       # Number of loads committed
-system.cpu0.commit.membars                    3711025                       # Number of memory barriers committed
-system.cpu0.commit.branches                 104496556                       # Number of branches committed
-system.cpu0.commit.fp_insts                    513447                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                502627891                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13679873                       # Number of function calls committed.
+system.cpu0.commit.refs                     177431645                       # Number of memory references committed
+system.cpu0.commit.loads                     93067519                       # Number of loads committed
+system.cpu0.commit.membars                    3925399                       # Number of memory barriers committed
+system.cpu0.commit.branches                 111370146                       # Number of branches committed
+system.cpu0.commit.fp_insts                    496516                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                535821487                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            14891305                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       379865208     69.31%     69.31% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1141082      0.21%     69.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           57492      0.01%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        73933      0.01%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       87021139     15.88%     85.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      79938057     14.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       405157799     69.37%     69.37% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1311833      0.22%     69.60% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           63039      0.01%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        69677      0.01%     69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       93067519     15.94%     85.55% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      84364126     14.45%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        548096953                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             13363788                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total        584033993                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14163521                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                  1279505618                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1198929363                       # The number of ROB writes
-system.cpu0.timesIdled                         780048                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       12636096                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 94120949562                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  466411686                       # Number of Instructions Simulated
-system.cpu0.committedOps                    548096953                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.551432                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.551432                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.644566                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.644566                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               688144011                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              408577767                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   842658                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  455584                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                127446024                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               128164594                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             2855519856                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15107964                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          5838402                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          504.465464                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          155155227                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5838912                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            26.572626                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1750084500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   504.465464                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.985284                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.985284                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        346167633                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       346167633                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80535549                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       80535549                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     69641264                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      69641264                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       207056                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       207056                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       203093                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       203093                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1877400                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1877400                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1900232                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1900232                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    150176813                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       150176813                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    150383869                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      150383869                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6642832                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6642832                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7191098                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7191098                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       692118                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       692118                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       798159                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total       798159                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       243998                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       243998                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       184133                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       184133                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13833930                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13833930                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     14526048                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14526048                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  99514286008                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  99514286008                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 115098035706                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  53560236062                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  53560236062                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3359260407                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3359260407                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3823760481                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   3823760481                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2172500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2172500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 214612321714                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 214612321714                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     87178381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     87178381                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     76832362                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     76832362                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       899174                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       899174                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1001252                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1001252                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2121398                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2121398                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2084365                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2084365                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    164010743                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    164010743                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    164909917                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    164909917                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076198                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.076198                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.093595                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.093595                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.769726                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.769726                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.797161                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.797161                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.115018                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.115018                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.088340                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.088340                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084348                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084348                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088085                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.088085                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541                       # average StoreCondReq miss latency
+system.cpu0.rob.rob_reads                  1371348086                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1277898548                       # The number of ROB writes
+system.cpu0.timesIdled                        1050969                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       22484428                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93902986117                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  497564314                       # Number of Instructions Simulated
+system.cpu0.committedOps                    584033993                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.583282                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.583282                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.631600                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.631600                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               732616408                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              435784003                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   812591                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  450624                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                135724425                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               136350840                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             3048491910                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15942846                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          6332598                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          484.098749                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          164710199                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6333110                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            26.007791                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       1750140500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.098749                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.945505                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.945505                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          275                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        368140426                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       368140426                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     86285504                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       86285504                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     73342402                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      73342402                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       227851                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       227851                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       264480                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       264480                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1878345                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1878345                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1911240                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1911240                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    159627906                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       159627906                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    159855757                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      159855757                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      7088092                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7088092                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7774496                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7774496                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       746133                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       746133                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       842824                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total       842824                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       281020                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       281020                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       209055                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       209055                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     14862588                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      14862588                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     15608721                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     15608721                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 105859717159                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 137077029934                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  45622327717                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  45622327717                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4025426932                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4025426932                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4395434712                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4395434712                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3232000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3232000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 242936747093                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 242936747093                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     93373596                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     93373596                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     81116898                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     81116898                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       973984                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       973984                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data      1107304                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1107304                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2159365                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2159365                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2120295                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2120295                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    174490494                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    174490494                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    175464478                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    175464478                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075911                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.075911                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095843                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.095843                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766063                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766063                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.761150                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.761150                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.130140                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.130140                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098597                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098597                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.085177                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.085177                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088957                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.088957                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     16118603                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     16176348                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           692801                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         696412                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.265848                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    23.228129                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     13488103                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     19786702                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           752105                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         757651                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    17.933803                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    26.115853                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3975125                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3975125                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3497983                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3497983                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5763188                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      5763188                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         4492                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         4492                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       123982                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       123982                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9261171                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9261171                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9261171                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9261171                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3144849                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3144849                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1427910                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1427910                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       685927                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       685927                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       793667                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       793667                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       120016                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       120016                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       184129                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       184129                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4572759                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4572759                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5258686                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5258686                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40981205496                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40981205496                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  22755476630                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  22755476630                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17996613568                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17996613568                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  51855736982                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  51855736982                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1434297417                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1434297417                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3446370519                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3446370519                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2070500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2070500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  63736682126                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  63736682126                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  81733295694                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  81733295694                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5581760391                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5581760391                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5277895398                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5277895398                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10859655789                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10859655789                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036074                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036074                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018585                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018585                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.762841                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.762841                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.792675                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.792675                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056574                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056574                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.088338                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.088338                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027881                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027881                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031888                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031888                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      4276528                       # number of writebacks
+system.cpu0.dcache.writebacks::total          4276528                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3664529                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3664529                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6233308                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6233308                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         4741                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         4741                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       141328                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       141328                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9897837                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9897837                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9897837                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9897837                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3423563                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3423563                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1541188                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1541188                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       739665                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       739665                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       838083                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       838083                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       139692                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       139692                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       209050                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       209050                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4964751                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4964751                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5704416                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5704416                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44975748199                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44975748199                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  28501279892                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  28501279892                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16804666332                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16804666332                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  43773018566                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  43773018566                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1737566757                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1737566757                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3967184288                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3967184288                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3082000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3082000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  73477028091                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  73477028091                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  90281694423                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  90281694423                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5575976491                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5575976491                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5325987989                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5325987989                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10901964480                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10901964480                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036665                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036665                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019000                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019000                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759422                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759422                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.756868                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.756868                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064691                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064691                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098595                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098595                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028453                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028453                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032510                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032510                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1005,463 +1095,461 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6042830                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.967320                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          208050611                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6043342                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.426417                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11201042000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.967320                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999936                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999936                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          6368542                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.961816                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          222275153                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6369054                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.899241                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      14184385750                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.961816                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999925                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999925                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          202                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        434737408                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       434737408                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    208050611                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      208050611                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    208050611                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       208050611                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    208050611                       # number of overall hits
-system.cpu0.icache.overall_hits::total      208050611                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6296413                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6296413                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6296413                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6296413                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6296413                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6296413                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  55127710497                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  55127710497                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  55127710497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  55127710497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  55127710497                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  55127710497                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    214347024                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    214347024                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    214347024                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    214347024                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    214347024                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    214347024                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029375                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029375                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029375                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029375                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029375                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029375                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8755.415265                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8755.415265                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8755.415265                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8755.415265                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8755.415265                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8755.415265                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      4477144                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets           62                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           570538                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.847232                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets           62                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        464315009                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       464315009                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    222275153                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      222275153                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    222275153                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       222275153                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    222275153                       # number of overall hits
+system.cpu0.icache.overall_hits::total      222275153                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6697664                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6697664                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6697664                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6697664                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6697664                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6697664                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  70928372732                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  70928372732                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  70928372732                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  70928372732                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  70928372732                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  70928372732                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    228972817                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    228972817                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    228972817                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    228972817                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    228972817                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    228972817                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029251                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029251                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029251                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029251                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029251                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029251                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10590.016569                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10590.016569                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      8781241                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          821                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           708037                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.402235                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    74.636364                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       253053                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       253053                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       253053                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       253053                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       253053                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       253053                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6043360                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6043360                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6043360                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6043360                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6043360                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6043360                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  44707631164                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  44707631164                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  44707631164                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  44707631164                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  44707631164                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  44707631164                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1699559498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1699559498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1699559498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   1699559498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028194                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028194                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028194                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028194                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7397.810351                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  7397.810351                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7397.810351                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  7397.810351                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       328289                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       328289                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       328289                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       328289                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       328289                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       328289                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6369375                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6369375                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6369375                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6369375                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6369375                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6369375                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  57966761800                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  57966761800                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  57966761800                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  57966761800                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  57966761800                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  57966761800                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1699560248                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1699560248                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1699560248                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   1699560248                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027817                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027817                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027817                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027817                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9100.855547                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9100.855547                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9100.855547                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9100.855547                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     60184765                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      4393414                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     48808124                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      3087530                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       452633                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      3443064                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      5114963                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements         4158550                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16214.275256                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          12594287                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         4174696                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            3.016815                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      9944532000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  3315.303513                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    38.862270                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.140550                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   967.067959                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2910.372119                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8960.528846                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.202350                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002372                       # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2122                       # Occupied blocks per task id
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-system.cpu0.l2cache.UpgradeReq_hits::total       121282                       # number of UpgradeReq hits
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-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000002                       # miss rate for Writeback accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.503091                       # miss rate for UpgradeReq accesses
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+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       172230                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    468497682                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    383886915                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst  20661944862                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.ReadReq_miss_latency::total  61257682252                       # number of ReadReq miss cycles
+system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data    212101792                       # number of WriteInvalidateReq miss cycles
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+system.cpu0.l2cache.UpgradeReq_miss_latency::total   2828322980                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3448129857                       # number of SCUpgradeReq miss cycles
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+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3007000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3007000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16311576734                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  16311576734                       # number of ReadExReq miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    383886915                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20661944862                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  56054929527                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  77569258986                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    468497682                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    383886915                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20661944862                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  56054929527                       # number of overall miss cycles
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+system.cpu0.l2cache.Writeback_accesses::writebacks      4276525                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total      4276525                       # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       836505                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       252875                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       252875                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       209045                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1300536                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1300536                       # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021197                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.110319                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::total     0.160610                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000001                       # miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_miss_rate::total     0.000001                       # miss rate for Writeback accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.762413                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.762413                       # miss rate for WriteInvalidateReq accesses
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.546175                       # miss rate for UpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.212950                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.025861                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.055564                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040778                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.268305                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.138650                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.025861                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.055564                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040778                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.268305                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.138650                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34658.489359                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34139.010283                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 27432.805640                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34790.290338                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33484.804522                       # average ReadReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 79701.265997                       # average WriteInvalidateReq miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 79701.265997                       # average WriteInvalidateReq miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20226.492471                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20262.343701                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20262.343701                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       288500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       288500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44702.657471                       # average ReadExReq miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 27432.805640                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36618.495379                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34139.010283                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 27432.805640                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36618.495379                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 35214.995476                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs       289229                       # number of cycles access was blocked
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39343.087545                       # average overall miss latency
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+system.cpu0.l2cache.blocked_cycles::no_mshrs          272                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs            8029                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               7                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    36.023041                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    38.857143                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1673369                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1673369                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          192                       # number of ReadReq MSHR hits
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-system.cpu0.l2cache.ReadReq_mshr_hits::total        88597                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data       467795                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total       467795                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        32791                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        32791                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          192                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        62618                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        58574                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total       121388                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          192                       # number of overall MSHR hits
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-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        58574                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total       121388                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13857                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9630                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       183817                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data      1099262                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total      1306566                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            7                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            7                       # number of Writeback MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      3442663                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total      3442663                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data       102264                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total       102264                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       122791                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       122791                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       145551                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       145551                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       221634                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       221634                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13857                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9630                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       183817                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1320896                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1528200                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      4970863                       # number of overall MSHR misses
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-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 191389904056                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 191389904056                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data   3325777104                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total   3325777104                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   2139983924                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   2139983924                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2013011425                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2013011425                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1662500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1662500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   7397496985                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   7397496985                       # number of ReadExReq MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    260281521                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4356544455                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37784374528                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total 234173879151                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1519173000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5327096604                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6846269604                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5036994556                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5036994556                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1519173000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10364091160                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11883264160                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.025853                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.278529                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.122077                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.writebacks::writebacks      1592666                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1592666                       # number of writebacks
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+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2333282169                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2482000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11186143543                       # number of ReadExReq MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    379527210                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  42799610918                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1519174250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5322353508                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6841527758                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5082599974                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5082599974                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1519174250                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10404953482                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11924127732                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.258030                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.160084                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000001                       # mshr miss rate for Writeback accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.129074                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.129074                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.503091                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.503091                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.790514                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.790514                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.762335                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.762335                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.546175                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.546175                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.823890                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.823890                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.185504                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.185504                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.025853                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256912                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.128447                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.025853                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.054478                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.030416                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256912                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.207527                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.207527                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.246303                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.164920                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021192                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.047320                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.110318                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.246303                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.417806                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       237500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       237500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229475                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       496400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       496400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1471,69 +1559,77 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq      15173335                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11005084                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        31316                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        31316                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      3975122                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      5222365                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp           14                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       963549                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       792291                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       491639                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       333223                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       494297                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1332515                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1202467                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     12129286                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16997895                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       390025                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1185916                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         30703122                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    387114336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    641181457                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1414144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4287888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1033997825                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                   10518238                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     27441081                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       5.371527                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.483213                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq      13921371                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11750633                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31686                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        31686                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback      4276525                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1274288                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1162561                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       836505                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       509905                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       381643                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       535354                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           87                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1437620                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1309284                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     12781022                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18390339                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       414542                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1294088                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         32879991                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    407960480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    693234728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1535584                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4758096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1107488888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    4767578                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     22911203                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       5.193957                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.395396                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5          17245975     62.85%     62.85% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6          10195106     37.15%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5          18467409     80.60%     80.60% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6           4443794     19.40%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      27441081                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   13452656135                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      22911203                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   14408211332                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    192867736                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    208870495                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9099601288                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9596174213                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8421572630                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   9165770534                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    213967447                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    223497560                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    651243914                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    700918244                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              133961841                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89061347                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6618163                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            94585757                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               62217505                       # Number of BTB hits
+system.cpu1.branchPred.lookups              124370032                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         83075187                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6189003                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            87824878                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               56905034                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.778936                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               18340774                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            186545                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            64.793752                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16687776                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            168367                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1555,27 +1651,98 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   538943                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               538943                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11373                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        87574                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       237839                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       301104                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  1852.353340                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       297190     98.70%     98.70% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         2030      0.67%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303          795      0.26%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          637      0.21%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          257      0.09%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607           66      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375           39      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           29      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911           48      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       301104                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       268131                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       265367     98.97%     98.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1941      0.72%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          396      0.15%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          232      0.09%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          106      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           37      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           35      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       268131                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 435751861088                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.614829                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.532518                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 434859464588     99.80%     99.80% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    474800000      0.11%     99.90% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    202701000      0.05%     99.95% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7     89682000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     62866500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     34103000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     13310500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     14713000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       214000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19         6500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 435751861088                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        87574     88.51%     88.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        11373     11.49%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        98947                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       538943                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       538943                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        98947                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        98947                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       637890                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    98830623                       # DTB read hits
-system.cpu1.dtb.read_misses                    443426                       # DTB read misses
-system.cpu1.dtb.write_hits                   80619639                       # DTB write hits
-system.cpu1.dtb.write_misses                   165440                       # DTB write misses
+system.cpu1.dtb.read_hits                    91392867                       # DTB read hits
+system.cpu1.dtb.read_misses                    373745                       # DTB read misses
+system.cpu1.dtb.write_hits                   75805429                       # DTB write hits
+system.cpu1.dtb.write_misses                   165198                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   44150                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      612                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6848                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37451                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      309                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  5879                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    42554                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                99274049                       # DTB read accesses
-system.cpu1.dtb.write_accesses               80785079                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    40297                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                91766612                       # DTB read accesses
+system.cpu1.dtb.write_accesses               75970627                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        179450262                       # DTB hits
-system.cpu1.dtb.misses                         608866                       # DTB misses
-system.cpu1.dtb.accesses                    180059128                       # DTB accesses
+system.cpu1.dtb.hits                        167198296                       # DTB hits
+system.cpu1.dtb.misses                         538943                       # DTB misses
+system.cpu1.dtb.accesses                    167737239                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1597,163 +1764,217 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   211899162                       # ITB inst hits
-system.cpu1.itb.inst_misses                     88988                       # ITB inst misses
+system.cpu1.itb.walker.walks                    85244                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                85244                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          675                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        61262                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore         9941                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        75303                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1139.330438                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8399.837182                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        74771     99.29%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          180      0.24%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          193      0.26%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          128      0.17%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839           12      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            6      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        75303                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        71878                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        70231     97.71%     97.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1324      1.84%     99.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          179      0.25%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           68      0.09%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           46      0.06%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        71878                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 397094361424                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.878531                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.326828                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    48253813024     12.15%     12.15% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   348822790900     87.84%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       16535000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        1219500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4           3000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 397094361424                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        61262     98.91%     98.91% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          675      1.09%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        61937                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        85244                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        85244                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61937                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61937                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       147181                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   196146030                       # ITB inst hits
+system.cpu1.itb.inst_misses                     85244                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44806                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   32114                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              45064                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1074                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26780                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   230833                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   213163                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               211988150                       # ITB inst accesses
-system.cpu1.itb.hits                        211899162                       # DTB hits
-system.cpu1.itb.misses                          88988                       # DTB misses
-system.cpu1.itb.accesses                    211988150                       # DTB accesses
-system.cpu1.numCycles                       705261968                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               196231274                       # ITB inst accesses
+system.cpu1.itb.hits                        196146030                       # DTB hits
+system.cpu1.itb.misses                          85244                       # DTB misses
+system.cpu1.itb.accesses                    196231274                       # DTB accesses
+system.cpu1.numCycles                       664388878                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          81258744                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     595261780                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  133961841                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          80558279                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    597026773                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               14270848                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1888771                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              137791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6543938                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       793820                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       311963                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                211646234                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1619349                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  28847                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         695097224                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.005850                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.225976                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          79880322                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     552169788                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  124370032                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          73592810                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    551328487                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13340182                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1707326                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              246511                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6080767                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       727313                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       602439                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                195911596                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1586691                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  28723                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         647243256                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.003235                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.226187                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               360486788     51.86%     51.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               129920524     18.69%     70.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                44826389      6.45%     77.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               159863523     23.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               336573756     52.00%     52.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               120960986     18.69%     70.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                40749741      6.30%     76.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               148958773     23.01%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           695097224                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.189946                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.844029                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                99752260                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            332349824                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                219841712                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             38085588                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5067840                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            18995502                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              2109796                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             616514692                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             22877728                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5067840                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               135033848                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               48639647                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     225189127                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                222148294                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             59018468                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             599774214                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5804898                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              8803158                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                361913                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                923044                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              23085631                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           14113                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          571116000                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            927515458                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       708750961                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           721490                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            514023695                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                57092304                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          16265387                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      14239236                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 76589893                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            99537313                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           83963206                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          9607701                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         8257946                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 576970515                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           16478044                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                581773999                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2685793                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       50643585                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     34938077                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        295595                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    695097224                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.836968                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.068825                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           647243256                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.187195                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.831094                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                96356177                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            306396299                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                204571849                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             35206357                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               4712574                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            17589142                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1996203                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             573391383                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             21361954                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               4712574                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               129172911                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               40460241                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     212107385                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                206565063                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             54225082                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             557977037                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5352379                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              8193976                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                222351                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                303036                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              21276416                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           13923                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          530659712                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            862978619                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       659902858                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           766208                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            478267677                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                52392029                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15246817                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13453544                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 71065053                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            91863812                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           78915989                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8629555                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7664780                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 536633802                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15513444                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                541699362                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2485495                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       46695905                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     31776612                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        271399                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    647243256                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.836933                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.069144                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          375720628     54.05%     54.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          136500819     19.64%     73.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          111041420     15.97%     89.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           64151608      9.23%     98.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7678235      1.10%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               4508      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                  6      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          349912497     54.06%     54.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          127097301     19.64%     73.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          103346931     15.97%     89.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           59640858      9.21%     98.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7242720      1.12%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               2949      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      695097224                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      647243256                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               58467261     44.14%     44.14% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 65736      0.05%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   8975      0.01%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              28      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              36077917     27.24%     71.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             37847209     28.57%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               54464030     43.99%     43.99% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 55578      0.04%     44.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  15828      0.01%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               9      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              33234382     26.84%     70.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             36043585     29.11%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            396486231     68.15%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1392625      0.24%     68.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                78812      0.01%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               12      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            369233279     68.16%     68.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1193564      0.22%     68.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                69127      0.01%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  2      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                1      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.40% # Type of FU issued
@@ -1763,367 +1984,367 @@ system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.40% # Ty
 system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.40% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         42928      0.01%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           101899765     17.52%     85.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           81873638     14.07%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         46847      0.01%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            94164053     17.38%     85.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           76992429     14.21%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             581773999                       # Type of FU issued
-system.cpu1.iq.rate                          0.824905                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  132467126                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.227695                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1992741902                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        643831652                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    565540483                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1056239                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            418449                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       388115                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             713583395                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 657730                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2682619                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             541699362                       # Type of FU issued
+system.cpu1.iq.rate                          0.815335                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  123813412                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.228565                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1855831634                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        598546046                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    526634223                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1109251                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            439129                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       408402                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             664822270                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 690492                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2431611                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     12570649                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        16823                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       158978                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5834378                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     11396985                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16347                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       143339                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5491640                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2724944                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      3729174                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2526857                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      3486247                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5067840                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                8144414                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2028582                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          593577386                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               4712574                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5829545                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1427417                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          552265728                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             99537313                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            83963206                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          14010879                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 57965                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1901764                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        158978                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2040667                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2820650                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4861317                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            574179310                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             98827451                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6993764                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             91863812                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            78915989                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13236985                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 56254                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1314129                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        143339                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1858186                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2653609                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4511795                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            534690067                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             91388435                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6481283                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       128827                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   179445358                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               107524158                       # Number of branches executed
-system.cpu1.iew.exec_stores                  80617907                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.814136                       # Inst execution rate
-system.cpu1.iew.wb_sent                     566651750                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    565928598                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                274900610                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                450009146                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       118482                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   167194328                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               100087893                       # Number of branches executed
+system.cpu1.iew.exec_stores                  75805893                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.804785                       # Inst execution rate
+system.cpu1.iew.wb_sent                     527704335                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    527042625                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                254576573                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                416898701                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.802437                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610878                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.793274                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610644                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       47337627                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       16182449                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4550579                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    686146419                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.786229                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.582193                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       43642021                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15242045                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4231486                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    638973832                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.786200                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.579868                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    448874592     65.42%     65.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    124520992     18.15%     83.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     51724584      7.54%     91.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     17115210      2.49%     93.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     12441515      1.81%     95.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8692682      1.27%     96.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5812900      0.85%     97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3666336      0.53%     98.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     13297608      1.94%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    417556945     65.35%     65.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    116379063     18.21%     83.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     48152991      7.54%     91.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     16068254      2.51%     93.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     11811974      1.85%     95.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      7886914      1.23%     96.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5403679      0.85%     97.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3345009      0.52%     98.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     12369003      1.94%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    686146419                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           458333534                       # Number of instructions committed
-system.cpu1.commit.committedOps             539467876                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    638973832                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           426124677                       # Number of instructions committed
+system.cpu1.commit.committedOps             502361434                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     165095491                       # Number of memory references committed
-system.cpu1.commit.loads                     86966664                       # Number of loads committed
-system.cpu1.commit.membars                    3858042                       # Number of memory barriers committed
-system.cpu1.commit.branches                 101991370                       # Number of branches committed
-system.cpu1.commit.fp_insts                    379596                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                495494093                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13607824                       # Number of function calls committed.
+system.cpu1.commit.refs                     153891175                       # Number of memory references committed
+system.cpu1.commit.loads                     80466826                       # Number of loads committed
+system.cpu1.commit.membars                    3635433                       # Number of memory barriers committed
+system.cpu1.commit.branches                  94895008                       # Number of branches committed
+system.cpu1.commit.fp_insts                    399904                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                461321486                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            12405087                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       373132612     69.17%     69.17% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1140635      0.21%     69.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           62088      0.01%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        37050      0.01%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       86966664     16.12%     85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      78128827     14.48%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       347396188     69.15%     69.15% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult         977319      0.19%     69.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           55389      0.01%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        41321      0.01%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       80466826     16.02%     85.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      73424349     14.62%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        539467876                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             13297608                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total        502361434                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             12369003                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                  1255653176                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1182522736                       # The number of ROB writes
-system.cpu1.timesIdled                         784634                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       10164744                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94139293558                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  458333534                       # Number of Instructions Simulated
-system.cpu1.committedOps                    539467876                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.538753                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.538753                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.649877                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.649877                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               678371688                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              402814905                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   627803                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  323588                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                123299886                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               123979632                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             2817640596                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              16155257                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5719154                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          428.720007                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          153241322                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5719665                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            26.792010                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8515430590500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   428.720007                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.837344                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.837344                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        342874086                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       342874086                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     80584085                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       80584085                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     68058878                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      68058878                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187635                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       187635                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       112453                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total       112453                       # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1764554                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1764554                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1816897                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1816897                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    148642963                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       148642963                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    148830598                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      148830598                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6869643                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6869643                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7494314                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7494314                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       706318                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       706318                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       458418                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total       458418                       # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       288948                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       288948                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       190861                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       190861                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     14363957                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      14363957                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     15070275                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     15070275                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 105402463849                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 121649241613                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  17403154350                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  17403154350                       # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4078869410                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   4078869410                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3937390159                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   3937390159                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1956500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1956500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 227051705462                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 227051705462                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     87453728                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     87453728                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     75553192                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     75553192                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       893953                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       893953                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       570871                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total       570871                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2053502                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2053502                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2007758                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2007758                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    163006920                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    163006920                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    163900873                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    163900873                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.078552                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.078552                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.099193                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.099193                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.790106                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.790106                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.803015                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.803015                       # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.140710                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.140710                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095062                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095062                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.088119                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.088119                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.091947                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.091947                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057                       # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687                       # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342                       # average StoreCondReq miss latency
+system.cpu1.rob.rob_reads                  1168820475                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1100237743                       # The number of ROB writes
+system.cpu1.timesIdled                         913492                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       17145622                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94026381638                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  426124677                       # Number of Instructions Simulated
+system.cpu1.committedOps                    502361434                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.559142                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.559142                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.641378                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.641378                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               632226075                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              374528717                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   661926                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  331836                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                114587184                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               115385602                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             2619636946                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15333141                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5236220                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          457.332610                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          143091306                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5236730                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            27.324553                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8478701081000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.332610                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.893228                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.893228                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        319394188                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       319394188                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     74655263                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       74655263                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     64023189                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      64023189                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       163779                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       163779                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data        39797                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total        39797                       # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1738928                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1738928                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1751406                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1751406                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    138678452                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       138678452                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    138842231                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      138842231                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6126939                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6126939                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      6982821                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      6982821                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       659533                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       659533                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       425377                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total       425377                       # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       260578                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       260578                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       204152                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       204152                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     13109760                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      13109760                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     13769293                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     13769293                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  92549514245                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  92549514245                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 116311286360                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data  11708163921                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total  11708163921                       # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3758503444                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   3758503444                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4320848660                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4320848660                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3489000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3489000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 208860800605                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 208860800605                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     80782202                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     80782202                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     71006010                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     71006010                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       823312                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       823312                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       465174                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total       465174                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1999506                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1999506                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1955558                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1955558                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    151788212                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    151788212                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    152611524                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    152611524                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075845                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.075845                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.098341                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.098341                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.801073                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.801073                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.914447                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.914447                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.130321                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.130321                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.104396                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.104396                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.086369                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.086369                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.090224                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.090224                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160                       # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401                       # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      4622048                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     18188306                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           368036                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         754235                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    12.558684                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    24.114906                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      2855420                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     17544431                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           337066                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         700468                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.471397                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    25.046727                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3658567                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3658567                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3579229                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3579229                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6058526                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      6058526                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3270                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total         3270                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       146042                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       146042                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9637755                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9637755                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9637755                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9637755                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3290414                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3290414                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1435788                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1435788                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       706224                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       706224                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       455148                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       455148                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       142906                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       142906                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       190858                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       190858                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4726202                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4726202                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5432426                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5432426                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  44800014998                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  44800014998                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23381887855                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23381887855                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16359112476                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16359112476                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  16414544257                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  16414544257                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1722097666                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1722097666                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3546227841                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3546227841                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1864500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1864500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  68181902853                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  68181902853                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  84541015329                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  84541015329                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    790979694                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    790979694                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    944680456                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    944680456                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1735660150                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1735660150                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037625                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037625                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019004                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019004                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.790001                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.790001                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.797287                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.797287                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.069591                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.069591                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095060                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095060                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028994                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028994                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033145                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033145                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      3392584                       # number of writebacks
+system.cpu1.dcache.writebacks::total          3392584                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3127909                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3127909                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5647115                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5647115                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3296                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total         3296                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       132105                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       132105                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      8775024                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      8775024                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      8775024                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      8775024                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2999030                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2999030                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1335706                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1335706                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       659449                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       659449                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       422081                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       422081                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       128473                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       128473                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       204145                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       204145                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4334736                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4334736                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4994185                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4994185                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38225367292                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38225367292                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  21845579142                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  21845579142                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15240654080                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15240654080                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  10753431338                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  10753431338                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1629520255                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1629520255                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3904363340                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3904363340                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3325000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3325000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  60070946434                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  60070946434                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75311600514                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  75311600514                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    796916503                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    796916503                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    897774501                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    897774501                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1694691004                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1694691004                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037125                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037125                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018811                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018811                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.800971                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.800971                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.907362                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.907362                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064252                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064252                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.104392                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.104392                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028558                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.028558                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032725                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032725                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2131,464 +2352,461 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5881686                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.904324                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          205507195                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5882198                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            34.937143                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8555135625500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.904324                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980282                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980282                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5522406                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.856310                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          190094169                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5522918                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            34.419155                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8518418347000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.856310                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980188                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.980188                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          371                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          335                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        429168724                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       429168724                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    205507195                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      205507195                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    205507195                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       205507195                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    205507195                       # number of overall hits
-system.cpu1.icache.overall_hits::total      205507195                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6136058                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6136058                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6136058                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6136058                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6136058                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6136058                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53889413624                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  53889413624                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  53889413624                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  53889413624                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  53889413624                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  53889413624                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    211643253                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    211643253                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    211643253                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    211643253                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    211643253                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    211643253                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028992                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028992                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028992                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028992                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028992                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028992                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8782.415946                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8782.415946                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8782.415946                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8782.415946                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8782.415946                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8782.415946                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      4496430                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           574651                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.824627                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        397333844                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       397333844                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    190094169                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      190094169                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    190094169                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       190094169                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    190094169                       # number of overall hits
+system.cpu1.icache.overall_hits::total      190094169                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5811281                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5811281                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5811281                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5811281                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5811281                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5811281                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  61520167992                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  61520167992                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  61520167992                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  61520167992                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  61520167992                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  61520167992                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    195905450                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    195905450                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    195905450                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    195905450                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    195905450                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    195905450                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029664                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029664                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029664                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029664                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029664                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029664                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10586.335094                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10586.335094                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      7857995                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets           39                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           642168                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.236665                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets           39                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       253840                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       253840                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       253840                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       253840                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       253840                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       253840                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5882218                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5882218                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5882218                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5882218                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5882218                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5882218                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  43727434357                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  43727434357                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  43727434357                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  43727434357                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  43727434357                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  43727434357                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6637997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6637997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6637997                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6637997                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027793                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027793                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027793                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027793                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7433.834373                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  7433.834373                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7433.834373                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  7433.834373                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       288337                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       288337                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       288337                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       288337                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       288337                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       288337                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5522944                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5522944                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5522944                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5522944                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5522944                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5522944                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50254087338                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  50254087338                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50254087338                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  50254087338                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50254087338                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  50254087338                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5802498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5802498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5802498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      5802498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028192                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.028192                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028192                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.028192                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9099.148450                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9099.148450                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9099.148450                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9099.148450                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     56932742                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2823095                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     47812216                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher      2677811                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit       382726                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      3236886                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4916498                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l2cache.tags.replacements         4092617                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13780.930785                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          12621619                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         4108487                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            3.072084                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9637211064000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  3757.362843                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    62.809020                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    56.863279                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   599.057552                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3491.075179                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  5813.762913                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.229331                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003834                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003471                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036564                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.213078                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.354844                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.841121                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8933                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6853                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           68                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          777                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         3625                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         2921                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1542                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           64                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3137                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2007                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          750                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.545227                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005127                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.418274                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       271640392                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      271640392                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       596119                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       184681                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5616426                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data      2971260                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total       9368486                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3658557                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3658557                       # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       182266                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total       182266                       # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        95807                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        95807                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        41710                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        41710                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       960995                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       960995                       # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       596119                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       184681                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5616426                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3932255                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       10329481                       # number of demand (read+write) hits
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-system.cpu1.l2cache.Writeback_misses::total            9                       # number of Writeback misses
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-system.cpu1.l2cache.UpgradeReq_misses::total       129531                       # number of UpgradeReq misses
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2603211060                       # number of UpgradeReq miss cycles
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-system.cpu1.l2cache.Writeback_accesses::writebacks      3658566                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3658566                       # number of Writeback accesses(hits+misses)
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-system.cpu1.l2cache.UpgradeReq_accesses::total       225338                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       190851                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000002                       # miss rate for Writeback accesses
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-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.574830                       # miss rate for UpgradeReq accesses
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3854.550779                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3125.340880                       # Average occupied blocks per requestor
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+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          510                       # Occupied blocks per task id
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       549260                       # number of ReadReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5522932                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3783141                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total     10046925                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks      3392582                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total      3392582                       # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       420701                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total       420701                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       217328                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       217328                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       204132                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       204132                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           13                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           13                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1126761                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1126761                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       549260                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       191592                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5522932                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4909902                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     11173686                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       549260                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       191592                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5522932                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4909902                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     11173686                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.109547                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.264770                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.162043                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000005                       # miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_miss_rate::total     0.000005                       # miss rate for Writeback accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.544196                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.544196                       # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.669881                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.669881                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.845860                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.845860                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210132                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210132                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026304                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.061819                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.045185                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.265542                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.142443                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026304                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.061819                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.045185                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.265542                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.142443                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26126.152896                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34784.106110                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33382.524504                       # average ReadReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 42960.221308                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 42960.221308                       # average WriteInvalidateReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20097.204993                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20097.204993                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20301.556024                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20301.556024                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259785.714286                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259785.714286                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46513.200378                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46513.200378                       # average ReadExReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26126.152896                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36893.285849                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35339.058829                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41386.272851                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46979.115046                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26126.152896                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36893.285849                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35339.058829                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs       176494                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.230022                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.230022                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109547                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256796                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.168898                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022465                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.047017                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109547                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.256796                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.168898                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29543.656006                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34211.758232                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32575.235811                       # average ReadReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data  1054.621929                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total  1054.621929                       # average WriteInvalidateReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20308.212070                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20308.212070                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19913.815790                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19913.815790                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 249461.538462                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 249461.538462                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41940.834914                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41940.834914                       # average ReadExReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29543.656006                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35800.552797                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 33861.459755                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39935.018154                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44132.569716                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29543.656006                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35800.552797                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 33861.459755                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            9                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs            8388                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    21.041249                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1389640                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1389640                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          164                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        69245                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         8993                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total        78405                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data       181850                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total       181850                       # number of WriteInvalidateReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        36174                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        36174                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          164                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        69245                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        45167                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total       114579                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          164                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        69245                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        45167                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total       114579                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        16101                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        12005                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       196543                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data      1157052                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total      1381701                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            9                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            9                       # number of Writeback MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      3236467                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total      3236467                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data        89970                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total        89970                       # number of WriteInvalidateReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       129531                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       129531                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       149141                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       149141                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       219483                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       219483                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        16101                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        12005                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       196543                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1376535                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1601184                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        16101                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        12005                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       196543                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1376535                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      3236467                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      4837651                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    552512324                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    478828801                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   4373003012                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  32056735781                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  37461079918                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 119200504380                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2795660291                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   2795660291                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2211789154                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2211789154                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2062142611                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2062142611                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1496500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1496500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7294562114                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7294562114                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    552512324                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    478828801                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   4373003012                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39351297895                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  44755642032                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    552512324                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    478828801                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   4373003012                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39351297895                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 119200504380                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 163956146412                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6077501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    736923302                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    743000803                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    890555024                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    890555024                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6077501                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1627478326                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1633555827                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.279663                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.127597                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000002                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.writebacks::writebacks       971322                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          971322                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          153                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         6612                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total         6768                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data           63                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total           63                       # number of WriteInvalidateReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        20490                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        20490                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          153                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        27102                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        27258                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            2                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          153                       # number of overall MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::cpu1.data        27102                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        27258                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12337                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8855                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       605019                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       995052                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total      1621263                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::writebacks           17                       # number of Writeback MSHR misses
+system.cpu1.l2cache.Writeback_mshr_misses::total           17                       # number of Writeback MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       705681                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       705681                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data       228881                       # number of WriteInvalidateReq MSHR misses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total       228881                       # number of WriteInvalidateReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       145584                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       172667                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       172667                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           13                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           13                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       238690                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       238690                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12337                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8855                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1233742                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1859953                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2565634                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of ReadReq MSHR miss cycles
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+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  39485552404                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  39485552404                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   6916972959                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total   6916972959                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   2477712924                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   2477712924                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2304203121                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2304203121                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2669000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2669000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7509818481                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7509818481                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    327287462                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13621135743                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34464397241                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  48818419677                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    405599231                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    327287462                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13621135743                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34464397241                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  39485552404                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  88303972081                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5233250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    741632996                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    746866246                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    846035990                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    846035990                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5233250                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1587668986                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1592902236                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.263023                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.161369                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000005                       # mshr miss rate for Writeback accesses
+system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000005                       # mshr miss rate for Writeback accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.198134                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.198134                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.574830                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.574830                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.781453                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.781453                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.544047                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.544047                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.669881                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.669881                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.845860                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.845860                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.180399                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.180399                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.257106                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132931                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026299                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.060986                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.033413                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.257106                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.211837                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.211837                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.251276                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.166458                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022461                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046218                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109547                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.251276                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.401623                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872                       # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.229614                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364                       # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2598,66 +2816,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq      15325840                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     11081361                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         7210                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         7210                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      3658566                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      4807205                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           18                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       637593                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       454086                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       471082                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       336358                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       477965                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1352070                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1222067                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11764566                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16293479                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       431287                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1341589                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         29830921                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    376462768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    612089908                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1574800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4897784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         995025260                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                   10166385                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     26584709                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       5.370632                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.482974                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq      12802922                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10291743                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         6895                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         6895                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback      3392582                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1076196                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           13                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1156933                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       420701                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       464615                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       376292                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       486818                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           88                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1296360                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1132878                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11046012                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15089863                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       415115                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1210522                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         27761512                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    353468736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    564735319                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1532736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4394080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         924130871                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5316111                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     20559073                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       5.243524                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.429209                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5          16731578     62.94%     62.94% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6           9853131     37.06%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5          15552442     75.65%     75.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6           5006631     24.35%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      26584709                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   12493291014                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      20559073                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   11602796673                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    175961487                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    182870488                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8832336643                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8299279905                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8528127192                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7848510644                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    235484276                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    224378946                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    730977975                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    662954125                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40396                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40396                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136775                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              30047                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40399                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40399                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136785                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              30057                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106728                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48154                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2672,13 +2890,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123062                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123088                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231200                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       231200                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354342                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48148                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354368                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48174                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2693,13 +2911,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156169                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156195                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338816                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7338816                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7497071                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36581000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7497097                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36604000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -2727,27 +2945,27 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1043032876                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1043087367                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93018000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            93034000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179190812                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179187461                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115581                       # number of replacements
-system.iocache.tags.tagsinuse               11.295325                       # Cycle average of tags in use
+system.iocache.tags.replacements               115604                       # number of replacements
+system.iocache.tags.tagsinuse               11.301402                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115597                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115620                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9153631711000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.835501                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.459825                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239719                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466239                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705958                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9117040369000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.419209                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.882193                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463701                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.242637                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706338                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2767,18 +2985,18 @@ system.iocache.overall_misses::realview.ethernet           40
 system.iocache.overall_misses::realview.ide         8872                       # number of overall misses
 system.iocache.overall_misses::total             8912                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1960529318                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1966236318                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       365000                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       365000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28841569746                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28841569746                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      6072000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1960529318                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1966601318                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      6072000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1960529318                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1966601318                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1954318592                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1960025592                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28939092314                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28939092314                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1954318592                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1960382592                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1954318592                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1960382592                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8872                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8909                       # number of ReadReq accesses(hits+misses)
@@ -2806,28 +3024,28 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 220702.246941                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 121666.666667                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       151800                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 220979.409152                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 220668.909111                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       151800                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 220979.409152                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 220668.909111                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        224453                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 220005.117522                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 220279.372408                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 219971.116697                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 220279.372408                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 219971.116697                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        228427                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27297                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27535                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.222625                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.295878                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106702                       # number of writebacks
+system.iocache.writebacks::total               106702                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::realview.ide         8872                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total         8909                       # number of ReadReq MSHR misses
@@ -2842,18 +3060,18 @@ system.iocache.overall_mshr_misses::realview.ethernet           40
 system.iocache.overall_mshr_misses::realview.ide         8872                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total         8912                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1499010380                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1502793380                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       209000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       209000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23291152308                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23291152308                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3992000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1499010380                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1503002380                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3992000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1499010380                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1503002380                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1492830122                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1496613122                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23388843706                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23388843706                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1492830122                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1496814122                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1492830122                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1496814122                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2868,569 +3086,561 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99800                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 168649.279623                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99800                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 168649.279623                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 167954.905969                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 167954.905969                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1916125                       # number of replacements
-system.l2c.tags.tagsinuse                64884.880884                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    8755676                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1978999                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.424295                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               3437261500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    8337.656958                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    17.346754                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    14.129416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      627.039592                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3445.654069                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   351.392171                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   435.207962                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      621.389971                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11403.863316                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.127223                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000265                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000216                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.009568                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.052577                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.235173                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005362                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006641                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.009482                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.174009                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.369551                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.990065                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        38428                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          201                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        24245                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           10                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1          143                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         2926                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6291                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        29058                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2           14                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          187                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1447                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2670                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        19923                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.586365                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003067                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.369949                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 93004482                       # Number of tag accesses
-system.l2c.tags.data_accesses                93004482                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         9030                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6306                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             171973                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             713080                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1991967                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         8819                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5864                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             186687                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             740221                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      2136612                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                5970559                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         3063024                       # number of Writeback hits
-system.l2c.Writeback_hits::total              3063024                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data        47241                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data        45742                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total        92983                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data           33885                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           29324                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               63209                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          7714                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          7828                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             15542                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            60878                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            59021                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               119899                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          9030                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6306                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              171973                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              773958                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher      1991967                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          8819                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5864                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              186687                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              799242                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher      2136612                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 6090458                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         9030                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6306                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             171973                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             773958                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher      1991967                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         8819                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5864                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             186687                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             799242                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher      2136612                       # number of overall hits
-system.l2c.overall_hits::total                6090458                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1923                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1303                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            12603                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           144091                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       852232                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         3910                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         3826                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            10632                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           164104                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       554912                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total              1749536                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data        29537                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data        18781                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total        48318                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         37338                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         36221                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             73559                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9578                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         9902                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           19480                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          52901                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          53544                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             106445                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1923                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1303                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             12603                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            196992                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       852232                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         3910                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         3826                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             10632                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            217648                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       554912                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1855981                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1923                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1303                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            12603                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           196992                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       852232                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         3910                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         3826                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            10632                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           217648                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       554912                       # number of overall misses
-system.l2c.overall_misses::total              1855981                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    177025748                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    119617998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   1238513239                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  13834613079                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 153097994602                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    331865247                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    326979750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   1012532239                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  14885938635                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  79345151118                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total   264370231655                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.data     10044630                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.data     10457617                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total     20502247                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    175354905                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    165935687                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    341290592                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     48698982                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     55173706                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    103872688                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4424762459                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4377056558                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   8801819017                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    177025748                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    119617998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1238513239                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  18259375538                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 153097994602                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    331865247                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    326979750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   1012532239                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  19262995193                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  79345151118                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    273172050672                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    177025748                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    119617998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1238513239                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  18259375538                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 153097994602                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    331865247                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    326979750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   1012532239                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  19262995193                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  79345151118                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   273172050672                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        10953                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         7609                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         184576                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         857171                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2844199                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        12729                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         9690                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         197319                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         904325                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2691524                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            7720095                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      3063024                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          3063024                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data        76778                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data        64523                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total       141301                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        71223                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        65545                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          136768                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        17292                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        17730                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         35022                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       113779                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       112565                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           226344                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10953                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7609                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          184576                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          970950                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2844199                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        12729                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         9690                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          197319                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1016890                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2691524                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             7946439                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10953                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7609                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         184576                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         970950                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2844199                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        12729                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         9690                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         197319                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1016890                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2691524                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            7946439                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.171245                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.068281                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.168101                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.394840                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.053882                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.181466                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.206170                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.226621                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.384707                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.291075                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.341951                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.524241                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.552613                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.537838                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.553898                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.558488                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.556222                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.464945                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.475672                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.470280                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.171245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.068281                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.202886                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.394840                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.053882                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.214033                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.206170                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.233561                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.175568                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.171245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.068281                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.202886                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.299639                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.307173                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.394840                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.053882                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.214033                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.206170                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.233561                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 98271.303579                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 96013.027038                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 95234.409236                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 90710.394841                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 151108.769214                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   340.069404                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   556.818966                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total   424.319032                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4696.419332                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4581.201154                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4639.685042                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5084.462518                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5571.975964                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5332.273511                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83642.321676                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81746.910167                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 82688.891136                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 98271.303579                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 92690.949572                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 95234.409236                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88505.270864                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 147184.723697                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92057.071243                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91801.993860                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 98271.303579                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 92690.949572                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179643.564900                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84876.022251                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 85462.558808                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 95234.409236                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88505.270864                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142986.908047                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 147184.723697                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             89319                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1613331                       # number of replacements
+system.l2c.tags.tagsinuse                64339.343113                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4797018                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1673818                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.865914                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               3243842500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   19101.398352                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   185.742619                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   228.186438                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3981.341018                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    11353.199987                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   179.349370                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   266.651363                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3248.685748                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     4974.329517                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9177.250333                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.291464                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002834                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003482                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.060750                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.173236                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.177661                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002737                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004069                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.049571                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.075902                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140034                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.981740                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10683                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          245                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49559                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           76                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          157                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          995                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9444                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          285                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3090                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         3968                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        42149                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.163010                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003738                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.756210                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 64781750                       # Number of tag accesses
+system.l2c.tags.data_accesses                64781750                       # Number of data accesses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data    214995003                       # number of UpgradeReq miss cycles
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+system.l2c.ReadReq_accesses::total            3959363                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      2564009                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          2564009                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data       629019                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.WriteInvalidateReq_accesses::total       848293                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        79513                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          158593                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        16967                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::total         31260                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data       105852                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.demand_accesses::total             4207043                       # number of demand (read+write) accesses
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+system.l2c.overall_accesses::total            4207043                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.087709                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.202206                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.inst      0.089771                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.193196                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.243473                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.779565                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.438283                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.691347                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.608561                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.587728                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.598116                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.615430                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590919                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.604223                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.618848                       # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_miss_rate::total        0.565564                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.310635                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.inst       0.089771                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.233923                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.262435                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.278972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.346299                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.087709                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.263890                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.310635                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.376754                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.089771                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.233923                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.262435                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.193733                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 94839.459967                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80261.557104                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 97242.091561                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 124447.736262                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data    77.724572                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   409.780072                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total   132.138496                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4296.060156                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4600.594946                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4446.091464                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3825.447903                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4271.781080                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4025.031237                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88845.110038                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81928.046416                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 86262.105583                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 80393.193733                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 92758.248191                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80261.557104                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 92864.390481                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 119602.960979                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85101.568308                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86813.154283                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 80393.193733                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 92758.248191                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87681.670463                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89059.019640                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80261.557104                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 92864.390481                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 119602.960979                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             13381                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     3582                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      234                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     24.935511                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     57.183761                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1337500                       # number of writebacks
-system.l2c.writebacks::total                  1337500                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.inst            17                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            30                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          247                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            23                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            31                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          305                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               654                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             30                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          247                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             23                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             31                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          305                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                654                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            30                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          247                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            23                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            31                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          305                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               654                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1922                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1303                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        12586                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       144061                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       851985                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         3910                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         3826                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst        10609                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data       164073                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       554607                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total         1748882                       # number of ReadReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data        29537                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data        18781                       # number of WriteInvalidateReq MSHR misses
-system.l2c.WriteInvalidateReq_mshr_misses::total        48318                       # number of WriteInvalidateReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        37338                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        36221                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        73559                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9578                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         9902                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        19480                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        52901                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        53544                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        106445                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1922                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1303                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        12586                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       196962                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       851985                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         3910                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         3826                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.data       217617                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       554607                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1855327                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1922                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1303                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        12586                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       196962                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.dtb.walker         3910                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.data       217617                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       554607                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1855327                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    153132498                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    103417998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1081620491                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  12045512933                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 142769903404                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    283035747                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    279220250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    879069489                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data  12846931385                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  72582930119                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 243024774314                       # number of ReadReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data    796481871                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data    524588616                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.WriteInvalidateReq_mshr_miss_latency::total   1321070487                       # number of WriteInvalidateReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    384680247                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    371145409                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    755825656                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     98663909                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    101839213                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    200503122                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3765456447                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3710047854                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7475504301                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    153132498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    103417998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1081620491                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  15810969380                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 142769903404                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    283035747                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    279220250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    879069489                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  16556979239                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  72582930119                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 250500278615                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    153132498                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    103417998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1081620491                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  15810969380                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 142769903404                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    283035747                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    279220250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    879069489                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  16556979239                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  72582930119                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 250500278615                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1103207000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4751952495                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4753250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    613999250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6473911995                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4501573998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    766793502                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5268367500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1103207000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9253526493                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4753250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1380792752                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11742279495                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.168066                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.299552                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.181431                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.226536                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.384707                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.291075                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.341951                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.524241                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.552613                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.537838                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.553898                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.558488                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.556222                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.464945                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.475672                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.470280                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.202855                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.299552                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.214002                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.233479                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.175477                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.171245                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.068189                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.202855                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.307173                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.394840                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053766                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.214002                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.206057                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.233479                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 135016.780662                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::total 135016.780662                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks             1241010                       # number of writebacks
+system.l2c.writebacks::total                  1241010                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst           230                       # number of ReadReq MSHR hits
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.193073                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.243324                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.779565                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.438283                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.691347                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.608561                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.587728                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.598116                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.615430                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590919                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.604223                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.618848                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.494171                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.565564                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.278972                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.346299                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.087381                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.263819                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.310635                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.376754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.089424                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.233817                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.262295                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.278972                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.346299                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.087381                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.263819                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.506634                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.310635                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.376754                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.089424                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.233817                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.448841                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.262295                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 82417.381349                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 84846.955925                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 45381.957713                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10183.407896                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10261.080288                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10221.673772                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10188.880770                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.651906                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10176.257889                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76299.327310                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69458.395878                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 73744.752518                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80292.648521                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 80445.957655                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 107317.450557                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 107317.450557                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -3445,57 +3655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             1817706                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1817706                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38526                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38526                       # Transaction distribution
-system.membus.trans_dist::Writeback           1444194                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       154200                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       154200                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           434662                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         279066                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           97607                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            117028                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102726                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123062                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq             1032278                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1032278                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38581                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38581                       # Transaction distribution
+system.membus.trans_dist::Writeback           1347712                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       689975                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       689975                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           447979                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         332386                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          121150                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            152231                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135895                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123088                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25796                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6008493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6157429                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336112                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       336112                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6493541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156169                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25972                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5571157                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5720295                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335903                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335903                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6056198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156195                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    207457224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    207665557                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14110208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14110208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               221775765                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           633029                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4186947                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51944                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    187423448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    187632159                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14096832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14096832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               201728991                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           678374                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3943213                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4186947    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3943213    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4186947                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98514469                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3943213                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98700492                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               45500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21244987                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21600991                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         16738053981                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         19952700228                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        17312327015                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        11115498245                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          187280188                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          187180539                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3539,49 +3749,49 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq            8653355                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           8646086                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38526                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38526                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3063024                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq       248029                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp       141301                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          493306                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        294608                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         787914                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           97                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           273153                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          273153                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10956928                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10351144                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              21308072                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    369780529                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    344544100                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              714324629                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1644746                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         12968411                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.008917                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.094008                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            4932840                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4925609                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38581                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38581                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          2564009                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq       955023                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp       848293                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          504313                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        344758                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         849071                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          157                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          157                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           306644                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          306644                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8600677                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6275419                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              14876096                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    289885704                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    198430935                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              488316639                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1740265                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9550575                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.012108                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.109370                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1               12852771     99.11%     99.11% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 115640      0.89%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                9434933     98.79%     98.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 115642      1.21%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           12968411                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        19352517195                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            9550575                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        18722164156                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          7381500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          7552500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20456793572                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       13115425494                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       20083133002                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       11201753623                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13518                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   13602                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5604                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    5345                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 5bc8e2e71..48ca1dfde 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.320621                       # Number of seconds simulated
-sim_ticks                                51320620981500                       # Number of ticks simulated
-final_tick                               51320620981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.320647                       # Number of seconds simulated
+sim_ticks                                51320647066500                       # Number of ticks simulated
+final_tick                               51320647066500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107709                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126560                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6449160479                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 667684                       # Number of bytes of host memory used
-host_seconds                                  7957.72                       # Real time elapsed on the host
-sim_insts                                   857117694                       # Number of instructions simulated
-sim_ops                                    1007133124                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 114690                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134762                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6864170011                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 721888                       # Number of bytes of host memory used
+host_seconds                                  7476.60                       # Real time elapsed on the host
+sim_insts                                   857487967                       # Number of instructions simulated
+sim_ops                                    1007562352                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       227264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       206272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5756576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          43073416                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        400256                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             49663784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5756576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5756576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69780544                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       226752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       205312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5743904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          43053832                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        407232                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49637032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5743904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5743904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69718464                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69801124                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3551                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3223                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             105899                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             673035                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6254                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                791962                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1090321                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69739044                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3543                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105701                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             672729                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                791544                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1089351                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1092894                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               112169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               839300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  967716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          112169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             112169                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1359698                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1091924                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4418                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               838918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  967194                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111922                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111922                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1358488                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1360099                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1359698                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              112169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              839701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2327815                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        791962                       # Number of read requests accepted
-system.physmem.writeReqs                      1696531                       # Number of write requests accepted
-system.physmem.readBursts                      791962                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1696531                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 50649920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     35648                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 108090368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  49663784                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              108433892                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      557                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7601                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          35291                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               50546                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51810                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               46789                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               46242                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               46096                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               52242                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               46925                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               49452                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               44750                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               73148                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              48402                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51457                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              45806                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              48601                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42635                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              46504                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              106325                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              106592                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              106293                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              105191                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              106687                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              109171                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              103226                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              105745                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              103090                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              109771                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             107182                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             108709                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102154                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             106063                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             100653                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102060                       # Per bank write bursts
+system.physmem.bw_write::total                1358889                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1358488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4418                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111922                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              839319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2326083                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        791544                       # Number of read requests accepted
+system.physmem.writeReqs                      1694292                       # Number of write requests accepted
+system.physmem.readBursts                      791544                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1694292                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 50622848                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     35968                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 107999616                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  49637032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              108290596                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      562                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6769                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          35256                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               48315                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               50150                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               46175                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               46946                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               45323                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               52981                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               47646                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               48748                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               44337                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               72322                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50834                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              50772                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              48451                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              47387                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              44232                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46363                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103979                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              105038                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              105754                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              105161                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              103562                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              108435                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              103867                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              105467                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              102645                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              108407                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             108582                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             107982                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             105330                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             105345                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             103911                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             104029                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          63                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51320619748500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51320645833500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  770677                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  770259                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1693958                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    524690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    218670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     33629                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     11094                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       783                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       320                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       222                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       146                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      143                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      115                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1691719                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    523893                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    218096                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     34112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       784                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       412                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       49                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,122 +159,122 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    35109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    66510                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    80685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    95220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    95674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   107871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   105650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   115186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   109604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   123316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   110089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    98131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    89808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    90193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    76388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    75197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    74826                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    71320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     4117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     3862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     3608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     3366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     3244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     3037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2623                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     2041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1971                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1782                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     1152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      151                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       519847                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.358892                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.693203                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.458813                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         210597     40.51%     40.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       125304     24.10%     64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44434      8.55%     73.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23828      4.58%     77.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        16026      3.08%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10297      1.98%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8038      1.55%     84.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7736      1.49%     85.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        73587     14.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         519847                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         65806                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.026092                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       69.420005                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           65801     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    35494                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    67146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    82141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    96477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    97233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   109038                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   106907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   116227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   110532                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   123491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   110542                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    98237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    89628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    89775                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    76304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    74747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    73803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    70600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     4308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     3522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     3348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     3077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     3049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     2918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     2900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     2554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     2529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     2364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     2307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     2173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1969                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      882                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       89                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       519566                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.297267                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.561612                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.602188                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         210755     40.56%     40.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       125086     24.08%     64.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44418      8.55%     73.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23610      4.54%     77.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15941      3.07%     80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10357      1.99%     82.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8070      1.55%     84.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7704      1.48%     85.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        73625     14.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         519566                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         66165                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        11.954266                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       69.214790                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           66159     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           65806                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         65806                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.665015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       22.295407                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       18.784846                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           44130     67.06%     67.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            6726     10.22%     77.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39            8110     12.32%     89.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47            2086      3.17%     92.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55            1158      1.76%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             536      0.81%     95.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             588      0.89%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             530      0.81%     97.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             479      0.73%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95             220      0.33%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            383      0.58%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111           149      0.23%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119           276      0.42%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            79      0.12%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135           128      0.19%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            41      0.06%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            35      0.05%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159            20      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            44      0.07%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            20      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            23      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191            10      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215            10      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           66165                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         66165                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        25.504330                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       22.270889                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       18.258332                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           44141     66.71%     66.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            6693     10.12%     76.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            8637     13.05%     89.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47            2199      3.32%     93.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55            1176      1.78%     94.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             430      0.65%     95.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             581      0.88%     96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             510      0.77%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             438      0.66%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95             204      0.31%     98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            335      0.51%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111           211      0.32%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119           211      0.32%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            55      0.08%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135           142      0.21%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143            25      0.04%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            36      0.05%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159            19      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167            38      0.06%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            22      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183            24      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             2      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::240-247             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           65806                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15790981009                       # Total ticks spent queuing
-system.physmem.totMemAccLat               30629824759                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3957025000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19953.10                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::256-263             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           66165                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15484448260                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30315360760                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3954910000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19576.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38703.10                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38326.23                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.10                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
@@ -282,36 +282,41 @@ system.physmem.busUtil                           0.02                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.05                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     603831                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1356638                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20623172.24                       # Average gap between requests
+system.physmem.avgWrQLen                        22.87                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     603455                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1355453                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20645225.93                       # Average gap between requests
 system.physmem.pageHitRate                      79.04                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49368372569000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1713708100000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      238539960500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                1984348800                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                1945694520                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1082730000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1061638875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               3042748800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               3130163400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              5503010400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              5441139360                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3352013043600                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3352013043600                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1228384903950                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1226638074825                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29714838054000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29716370360250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34306848839550                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34306600114830                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.480867                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.476020                       # Core power per rank (mW)
+system.physmem_0.actEnergy                 1965463920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1072425750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3012968400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5451384240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1226370177675                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29716624044750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34306511542575                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.473889                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49436215199501                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713709140000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    170722374999                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 1962455040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1070784000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3156644400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5483576880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352015077840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1227684074985                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29715471503250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34306844116395                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.480369                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49434282568001                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713709140000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    172653903249                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
@@ -334,16 +339,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               226428976                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         151471445                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12246087                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            159886473                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               104578062                       # Number of BTB hits
+system.cpu.branchPred.lookups               226505876                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         151515363                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12247822                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            159926869                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               104610641                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.407698                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31061917                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             345275                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.411548                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31076851                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             345252                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -365,27 +378,95 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                    931379                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                931379                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16662                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       157071                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       405257                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       526122                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  1688.949521                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-32767       521687     99.16%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-65535         1343      0.26%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-98303         1868      0.36%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::98304-131071          570      0.11%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-163839          209      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::163840-196607          174      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-229375           58      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::229376-262143          108      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-294911            8      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::294912-327679            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-360447           36      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::360448-393215           45      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-425983           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       526122                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       461527                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       458117     99.26%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         2510      0.54%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          628      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          155      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           42      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       461527                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 768881581580                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.740934                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.499994                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  767107299580     99.77%     99.77% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3     970542000      0.13%     99.90% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     364225500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     157799500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     120916000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11     94826000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     21620500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     42242000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2110500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 768881581580                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        157072     90.41%     90.41% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16662      9.59%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       173734                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       931379                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       931379                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       173734                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       173734                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1105113                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    171196432                       # DTB read hits
-system.cpu.dtb.read_misses                     671544                       # DTB read misses
-system.cpu.dtb.write_hits                   149025904                       # DTB write hits
-system.cpu.dtb.write_misses                    258759                       # DTB write misses
+system.cpu.dtb.read_hits                    171278986                       # DTB read hits
+system.cpu.dtb.read_misses                     671795                       # DTB read misses
+system.cpu.dtb.write_hits                   149102166                       # DTB write hits
+system.cpu.dtb.write_misses                    259584                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               40008                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1029                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72979                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       104                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10362                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    73098                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       106                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  10235                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     68614                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                171867976                       # DTB read accesses
-system.cpu.dtb.write_accesses               149284663                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69082                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                171950781                       # DTB read accesses
+system.cpu.dtb.write_accesses               149361750                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         320222336                       # DTB hits
-system.cpu.dtb.misses                          930303                       # DTB misses
-system.cpu.dtb.accesses                     321152639                       # DTB accesses
+system.cpu.dtb.hits                         320381152                       # DTB hits
+system.cpu.dtb.misses                          931379                       # DTB misses
+system.cpu.dtb.accesses                     321312531                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -407,8 +488,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                    360051885                       # ITB inst hits
-system.cpu.itb.inst_misses                     161655                       # ITB inst misses
+system.cpu.itb.walker.walks                    161841                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                161841                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1421                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       122616                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17088                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144753                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   980.521993                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  6808.510178                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       144225     99.64%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          131      0.09%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          321      0.22%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           37      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144753                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       141125                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 24337.182009                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767       134420     95.25%     95.25% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535         4577      3.24%     98.49% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303         1336      0.95%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071          512      0.36%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839           95      0.07%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607           88      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375           22      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143           28      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       141125                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 657209390884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.938693                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.240123                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     40327296652      6.14%      6.14% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    616846868232     93.86%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        34699000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          527000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 657209390884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        122616     98.85%     98.85% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1421      1.15%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       124037                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161841                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       161841                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       124037                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       124037                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       285878                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    360168043                       # ITB inst hits
+system.cpu.itb.inst_misses                     161841                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -417,111 +556,111 @@ system.cpu.itb.flush_tlb                           10                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               40008                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1029                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53701                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    53745                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    372863                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    372581                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                360213540                       # ITB inst accesses
-system.cpu.itb.hits                         360051885                       # DTB hits
-system.cpu.itb.misses                          161655                       # DTB misses
-system.cpu.itb.accesses                     360213540                       # DTB accesses
-system.cpu.numCycles                       1576874693                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                360329884                       # ITB inst accesses
+system.cpu.itb.hits                         360168043                       # DTB hits
+system.cpu.itb.misses                          161841                       # DTB misses
+system.cpu.itb.accesses                     360329884                       # DTB accesses
+system.cpu.numCycles                       1576983833                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          648679854                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1010290403                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   226428976                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135639979                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     852655064                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26160452                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3389644                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                26807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9240220                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1021673                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          362                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 359662567                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6136086                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   47510                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1528093850                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.774691                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.161324                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          648826167                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1010661506                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   226505876                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          135687492                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     852638415                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26165882                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3403646                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9234109                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1027275                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 359779044                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6134765                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47734                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1528240089                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.774898                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.161407                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                965958627     63.21%     63.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                215893777     14.13%     77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70817340      4.63%     81.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                275424106     18.02%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                965897706     63.20%     63.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                215974848     14.13%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70846962      4.64%     81.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                275520573     18.03%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1528093850                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.143594                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.640692                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                527180052                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             504302107                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 436284853                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              51059674                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9267164                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33905862                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3872221                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1095429909                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29099398                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9267164                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                572442291                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                46180186                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      363186865                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 441948285                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              95069059                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1075584704                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6788495                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               4945824                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 318864                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 589123                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               42956715                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            21763                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1023437611                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1659121727                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1272319582                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1685396                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             957674620                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65762988                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           27435128                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23745394                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 104747763                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            175168030                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           152601618                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9963388                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9061948                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1040022976                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27737741                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1056135120                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3300763                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        53598061                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33623556                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         314928                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1528093850                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.691145                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.927830                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1528240089                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.143632                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.640883                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                527342057                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             504093722                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 436470729                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              51063982                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9269599                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33921165                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3872416                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1095869891                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29092135                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9269599                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                572608237                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46122541                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      363160924                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 442135288                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              94943500                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1076024490                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6785579                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               4940621                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 314117                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 587788                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               42830435                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            21754                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1023810702                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1659713955                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1272840679                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1685189                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             958043687                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65767012                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27437914                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23747073                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 104751050                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            175241778                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           152679763                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9977994                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9053000                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1040458161                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27741753                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1056586315                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3302783                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53612674                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33630584                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         315276                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1528240089                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.691375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.927907                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           873977548     57.19%     57.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           338098484     22.13%     79.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           236626258     15.49%     94.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72801252      4.76%     99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6571176      0.43%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19132      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           873840021     57.18%     57.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           338263818     22.13%     79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           236701790     15.49%     94.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72838134      4.77%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6577115      0.43%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19211      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1528093850                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1528240089                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                58371154     35.14%     35.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100885      0.06%     35.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26756      0.02%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                58408451     35.14%     35.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100871      0.06%     35.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26760      0.02%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.21% # attempts to use FU when none available
@@ -544,19 +683,19 @@ system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.21% # at
 system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.21% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              767      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44544414     26.81%     62.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              63075062     37.97%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              763      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44563063     26.81%     62.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              63134312     37.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 2      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             727332382     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2546997      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                123061      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                12      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             727619955     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2547357      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                123270      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -578,102 +717,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         120668      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         120690      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            175096796     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           150915164     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            175181818     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           150993162     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1056135120                       # Type of FU issued
-system.cpu.iq.rate                           0.669765                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   166119038                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157290                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3807304115                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1120557954                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1038099529                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2479775                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             941816                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       907592                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1220693938                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1560218                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4348848                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1056586315                       # Type of FU issued
+system.cpu.iq.rate                           0.670005                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   166234220                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157331                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3808470802                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1121012820                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1038530652                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2478919                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             941723                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       907476                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1221261060                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1559463                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4354414                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13855252                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14404                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142361                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6337064                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13859524                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14300                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143284                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6341204                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2552747                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1859122                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2565738                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1859911                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9267164                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6379535                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3965873                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1067985048                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9269599                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6359819                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3950891                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1068424262                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             175168030                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            152601618                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           23314125                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  62024                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3832996                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142361                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3691152                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5135953                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8827105                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1044930592                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             171186057                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10287379                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             175241778                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            152679763                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           23316187                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  61516                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3818793                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143284                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3692717                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5135549                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8828266                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1045377154                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             171268732                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10291027                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        224331                       # number of nop insts executed
-system.cpu.iew.exec_refs                    320208959                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                198322451                       # Number of branches executed
-system.cpu.iew.exec_stores                  149022902                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.662659                       # Inst execution rate
-system.cpu.iew.wb_sent                     1039793819                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1039007121                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 442154878                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 715627882                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        224348                       # number of nop insts executed
+system.cpu.iew.exec_refs                    320367802                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                198404489                       # Number of branches executed
+system.cpu.iew.exec_stores                  149099070                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.662897                       # Inst execution rate
+system.cpu.iew.wb_sent                     1040225395                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1039438128                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 442335874                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 715873221                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.658903                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.617856                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.659130                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.617897                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51471265                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        27422813                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8433025                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1516084212                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.664299                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.291990                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51477037                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27426477                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8434480                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1516228883                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.664519                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.292276                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    998537580     65.86%     65.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    291350566     19.22%     85.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    121957393      8.04%     93.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36696853      2.42%     95.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28610485      1.89%     97.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14255849      0.94%     98.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8557612      0.56%     98.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4232636      0.28%     99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11885238      0.78%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    998506921     65.85%     65.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    291444279     19.22%     85.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    121999456      8.05%     93.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36692084      2.42%     95.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28614798      1.89%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14261229      0.94%     98.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8588058      0.57%     98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4227240      0.28%     99.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11894818      0.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1516084212                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            857117694                       # Number of instructions committed
-system.cpu.commit.committedOps             1007133124                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1516228883                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            857487967                       # Number of instructions committed
+system.cpu.commit.committedOps             1007562352                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      307577331                       # Number of memory references committed
-system.cpu.commit.loads                     161312777                       # Number of loads committed
-system.cpu.commit.membars                     7014752                       # Number of memory barriers committed
-system.cpu.commit.branches                  191334741                       # Number of branches committed
-system.cpu.commit.fp_insts                     896026                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 925144388                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25493443                       # Number of function calls committed.
+system.cpu.commit.refs                      307720812                       # Number of memory references committed
+system.cpu.commit.loads                     161382253                       # Number of loads committed
+system.cpu.commit.membars                     7017472                       # Number of memory barriers committed
+system.cpu.commit.branches                  191417503                       # Number of branches committed
+system.cpu.commit.fp_insts                     895898                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 925548459                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25509836                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        697181314     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2164633      0.21%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98281      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        697466429     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2165110      0.21%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98436      0.01%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
@@ -700,233 +839,232 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111523      0.01%     69.46% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       161312777     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      146264554     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       161382253     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      146338559     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total        1007133124                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11885238                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total        1007562352                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11894818                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2555181565                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2129123637                       # The number of ROB writes
-system.cpu.timesIdled                         8137810                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        48780843                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101064367400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   857117694                       # Number of Instructions Simulated
-system.cpu.committedOps                    1007133124                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.839741                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.839741                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.543555                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.543555                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1237020079                       # number of integer regfile reads
-system.cpu.int_regfile_writes               738429626                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1457787                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 228125574                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                228731881                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              5247037954                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               27486572                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9822538                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.985265                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           286045243                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9823050                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.119799                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1485814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.985265                       # Average occupied blocks per requestor
+system.cpu.rob.rob_reads                   2555751551                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2129995502                       # The number of ROB writes
+system.cpu.timesIdled                         8137427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        48743744                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101064310429                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   857487967                       # Number of Instructions Simulated
+system.cpu.committedOps                    1007562352                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.839074                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.839074                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.543752                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.543752                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1237547063                       # number of integer regfile reads
+system.cpu.int_regfile_writes               738733043                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1457540                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782548                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 228190122                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                228796042                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              5248690758                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27489325                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9822587                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.985266                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           286182485                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9823099                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.133625                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1485676250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.985266                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999971                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999971                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          380                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1249214859                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1249214859                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    148712432                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       148712432                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    129479125                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      129479125                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       381594                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        381594                       # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324870                       # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total       324870                       # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352883                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3352883                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3750315                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3750315                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     278191557                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        278191557                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    278573151                       # number of overall hits
-system.cpu.dcache.overall_hits::total       278573151                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9502058                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9502058                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11465174                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11465174                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1197022                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1197022                       # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233022                       # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total      1233022                       # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       449448                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       449448                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1249763399                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1249763399                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    148780016                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       148780016                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    129548885                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      129548885                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       381333                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        381333                       # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       324563                       # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total       324563                       # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3352422                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3352422                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3751270                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3751270                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     278328901                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        278328901                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    278710234                       # number of overall hits
+system.cpu.dcache.overall_hits::total       278710234                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9497038                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9497038                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11468447                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11468447                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1197141                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1197141                       # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1233328                       # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total      1233328                       # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       450623                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       450623                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20967232                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20967232                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     22164254                       # number of overall misses
-system.cpu.dcache.overall_misses::total      22164254                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 140935225401                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 322991667568                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38675981880                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38675981880                       # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6315194753                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6315194753                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     20965485                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20965485                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22162626                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22162626                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 140713387644                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 321962948230                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  38655244426                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total  38655244426                       # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6327424004                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6327424004                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       139001                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       139001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 463926892969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 463926892969                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 463926892969                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 463926892969                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    158214490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    158214490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    140944299                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    140944299                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578616                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1578616                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total      1557892                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3802331                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3802331                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3750320                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3750320                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    299158789                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    299158789                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    300737405                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    300737405                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060058                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060058                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081345                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081345                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758273                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.758273                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791468                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791468                       # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118203                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118203                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 462676335874                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 462676335874                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 462676335874                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 462676335874                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    158277054                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    158277054                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    141017332                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    141017332                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1578474                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1578474                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1557891                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total      1557891                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3803045                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3803045                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3751275                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3751275                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    299294386                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    299294386                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    300872860                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    300872860                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060003                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060003                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081327                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.081327                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758417                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.758417                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.791665                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.791665                       # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.118490                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.118490                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070087                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070087                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073700                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073700                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200                       # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230                       # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070050                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070050                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073661                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073661                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305                       # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609                       # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22126.282237                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20931.310973                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     21466802                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22068.477589                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20876.422129                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     21410972                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1401851                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1402072                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.313184                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.270950                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7593763                       # number of writebacks
-system.cpu.dcache.writebacks::total           7593763                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4321399                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4321399                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9425025                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9425025                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7055                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7055                       # number of WriteInvalidateReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219414                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219414                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13746424                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13746424                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13746424                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13746424                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5180659                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5180659                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2040149                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2040149                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190231                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1190231                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1225967                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1225967                       # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230034                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       230034                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7597183                       # number of writebacks
+system.cpu.dcache.writebacks::total           7597183                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4319062                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4319062                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9426489                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9426489                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data         7148                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.WriteInvalidateReq_mshr_hits::total         7148                       # number of WriteInvalidateReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       220034                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       220034                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13745551                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13745551                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13745551                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13745551                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5177976                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5177976                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2041958                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2041958                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1190352                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1190352                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1226180                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1226180                       # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       230589                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       230589                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7220808                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7220808                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8411039                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8411039                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70208074682                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  70208074682                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53752252884                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53752252884                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18853760746                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18853760746                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35977742828                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2809792248                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2809792248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      7219934                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7219934                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8410286                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8410286                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  70110899674                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  70110899674                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53589743024                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53589743024                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  18780468745                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  18780468745                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  35955294132                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2813771248                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2813771248                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       128999                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       128999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 123960327566                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 142814088312                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729213249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729213249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587099983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587099983                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316313232                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316313232                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032745                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014475                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014475                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.753971                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.753971                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786940                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060498                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 123700642698                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 142481111443                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5729238749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5729238749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5587095483                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5587095483                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11316334232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11316334232                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.754116                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.754116                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787077                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060633                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060633                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024137                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024137                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027968                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027968                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277                       # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024123                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024123                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027953                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027953                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673                       # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -934,276 +1072,277 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15082585                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.954216                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           343840613                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15083097                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.796420                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       14175734000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.954216                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          15084162                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.954207                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           343955623                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15084674                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.801661                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       14174936000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.954207                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999911                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         374724467                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        374724467                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    343840613                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       343840613                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     343840613                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        343840613                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    343840613                       # number of overall hits
-system.cpu.icache.overall_hits::total       343840613                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15800655                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15800655                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15800655                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15800655                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15800655                       # number of overall misses
-system.cpu.icache.overall_misses::total      15800655                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208208668907                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208208668907                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208208668907                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208208668907                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208208668907                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    359641268                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    359641268                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    359641268                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    359641268                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    359641268                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    359641268                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043934                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.043934                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.043934                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.043934                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.043934                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.043934                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13177.217584                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13177.217584                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10839                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         374842526                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        374842526                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    343955623                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       343955623                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total       343955623                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15802123                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15802123                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total       15802123                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15802123                       # number of overall misses
+system.cpu.icache.overall_misses::total      15802123                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 208192919846                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 208192919846                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 208192919846                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 208192919846                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 208192919846                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    359757746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    359757746                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    359757746                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    359757746                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    359757746                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    359757746                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043924                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043924                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043924                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043924                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043924                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043924                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13174.996793                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13174.996793                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        11061                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               972                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               978                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    11.151235                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    11.309816                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       717456                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       717456                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       717456                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       717456                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       717456                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       717456                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15083199                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15083199                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15083199                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15083199                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15083199                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15083199                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 171815580989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 171815580989                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1413030250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   1413030250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.041940                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.041940                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.041940                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.041940                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_hits::total       717343                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.041930                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032                       # average overall mshr miss latency
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 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1167362                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65297.852107                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           29065274                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1230222                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.626040                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       2430272000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   320.853018                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   490.286692                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7518.567341                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.569512                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004896                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007481                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62575                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          285                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          565                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2655                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5044                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954819                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.ReadReq_hits::total       22433008                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7593763                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7593763                       # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       728839                       # number of WriteInvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       497128                       # number of WriteInvalidateReq misses
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-system.cpu.l2cache.Writeback_accesses::writebacks      7593763                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        36000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        36000                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1212,114 +1351,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       983690                       # number of writebacks
-system.cpu.l2cache.writebacks::total           983690                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       982720                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           21                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34502                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    221074750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   5441255518                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18116835264                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24019252031                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  19575424791                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    345346475                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    345346475                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70001                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29577738885                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29577738885                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    220243499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5475082762                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47837062889                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  53771748899                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    239359749                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    220243499                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5475082762                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47837062889                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  53771748899                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289733251                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393715501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176071500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176071500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103982250                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465804751                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569787001                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.039032                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015316                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.405499                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784600                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784600                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29394156879                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29394156879                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    221074750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5441255518                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47510992143                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  53413408910                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    240086499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    221074750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5441255518                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47510992143                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  53413408910                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5289749251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6393613751                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5176073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5176073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1103864500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10465822751                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11569687251                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.038843                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015245                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.404389                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784594                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784594                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208413                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208413                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030898                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004433                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010725                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005612                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078433                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030898                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872                       # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460                       # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.208727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.208727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030869                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004410                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010600                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005598                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.078399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030869                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249                       # average ReadReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840                       # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1329,58 +1468,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       23341232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23333163                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq       23340437                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23332371                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33858                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33858                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      7593763                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332631                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1225967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      7597183                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1332844                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1226180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43948                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43982                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1999866                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1999866                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30208899                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27463876                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       731462                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1967033                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          60371270                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965659760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1114918084                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2404176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6408648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2089390668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      611685                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     34508223                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        5.003348                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.057762                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43953                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2001716                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2001716                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     30212060                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27467336                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       733813                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1968769                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          60381978                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    965760880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1115140164                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2421064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6427336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2089749444                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      606880                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     34513008                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        5.003347                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.057757                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5           34392703     99.67%     99.67% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6             115520      0.33%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5           34397489     99.67%     99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6             115519      0.33%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       34508223                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    26206492236                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       34513008                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    26212619005                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1177500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1180500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22671590732                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22673982421                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13674088224                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13673864954                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     431886005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     432131982                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1166711358                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1166119344                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40382                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40382                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40381                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40381                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1400,11 +1539,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354228                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1421,11 +1560,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492678                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492670                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1454,71 +1593,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042360658                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1042349161                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179004169                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179004202                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115462                       # number of replacements
-system.iocache.tags.tagsinuse               10.424613                       # Cycle average of tags in use
+system.iocache.tags.replacements               115461                       # number of replacements
+system.iocache.tags.tagsinuse               10.424617                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115477                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13092189065000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544618                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.879995                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13092188806000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544621                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.879997                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221539                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.430000                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651538                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651539                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039677                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039668                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8815                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8855                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
-system.iocache.overall_misses::total             8856                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8815                       # number of overall misses
+system.iocache.overall_misses::total             8855                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5527000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1927411613                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1932938613                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1934147111                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1939674111                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28910124876                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28910124876                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28899223848                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28899223848                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5866000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1927411613                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1933277613                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1934147111                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1940013111                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5866000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1927411613                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1933277613                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1934147111                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1940013111                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8815                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8855                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8815                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8855                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1533,54 +1672,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 218337.130125                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 219122.696679                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 218301.446816                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 219086.743196                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       146650                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 218626.544124                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 218301.446816                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        226675                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 219415.440839                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 219086.743196                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        225873                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27646                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27588                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.199197                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.187364                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8815                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8855                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8815                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8855                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3603000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1468863623                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1472466623                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1475641121                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1479244121                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23363269204                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23352302242                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3786000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1468863623                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1472649623                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1475641121                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1479427121                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3786000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1468863623                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1472649623                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1475641121                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1479427121                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1595,70 +1734,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        94650                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 166288.349481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 167072.515076                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              412825                       # Transaction distribution
-system.membus.trans_dist::ReadResp             412825                       # Transaction distribution
+system.membus.trans_dist::ReadReq              411277                       # Transaction distribution
+system.membus.trans_dist::ReadResp             411277                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33858                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33858                       # Transaction distribution
-system.membus.trans_dist::Writeback           1090321                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       603637                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       603637                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35296                       # Transaction distribution
+system.membus.trans_dist::Writeback           1089351                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       602368                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       602368                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35261                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           35298                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            416163                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           416163                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35263                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            417183                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           417183                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3625442                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3755550                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4090619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3620810                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3750918                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335177                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4086095                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    144046540                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144217012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14051136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14051136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               158268148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3264                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2503253                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    143869516                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    144039988                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14058112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14058112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               158098100                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3154                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2500418                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2503253    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2500418    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2503253                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109702500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2500418                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109711500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               42500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5437999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5440999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         16337638979                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         16316164477                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7836649146                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7830132924                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186565831                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          186594798                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index a91165258..e7103dcb2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,173 +1,173 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.234988                       # Number of seconds simulated
-sim_ticks                                51234988037500                       # Number of ticks simulated
-final_tick                               51234988037500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.234984                       # Number of seconds simulated
+sim_ticks                                51234983764500                       # Number of ticks simulated
+final_tick                               51234983764500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 253332                       # Simulator instruction rate (inst/s)
-host_op_rate                                   297695                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14683650995                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 666424                       # Number of bytes of host memory used
-host_seconds                                  3489.25                       # Real time elapsed on the host
-sim_insts                                   883939374                       # Number of instructions simulated
-sim_ops                                    1038732312                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 293597                       # Simulator instruction rate (inst/s)
+host_op_rate                                   345003                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            16999127000                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 723216                       # Number of bytes of host memory used
+host_seconds                                  3013.98                       # Real time elapsed on the host
+sim_insts                                   884896163                       # Number of instructions simulated
+sim_ops                                    1039832130                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       127040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       124736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3010420                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         25072712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        36992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        30656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           716608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          7359168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        93568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        90944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          2126784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data         17729152                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        417856                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             56936636                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3010420                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       716608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      2126784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5853812                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     77081408                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       129856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       125184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2903796                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24969352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        34560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        29888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           811648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          7348736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        94656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        89280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          2169408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data         17774080                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        413120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             56893564                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2903796                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       811648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      2169408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5884852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     77105472                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          77101988                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1949                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             87445                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            391774                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          578                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          479                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             11197                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            114987                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker         1462                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker         1421                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             33231                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            277018                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6529                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                930055                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1204397                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          77126052                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2029                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1956                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             85779                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            390159                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          467                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             12682                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            114824                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker         1479                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker         1395                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             33897                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            277720                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6455                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                929382                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1204773                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1206970                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2480                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2435                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               58757                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              489367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           722                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           598                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               13987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              143636                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          1826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker          1775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               41510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              346036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8156                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1111284                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          58757                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          13987                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          41510                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             114254                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1504468                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1207346                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2535                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               56676                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              487350                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           675                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           583                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               15842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              143432                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker          1847                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker          1743                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               42342                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              346913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1110444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          56676                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          15842                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          42342                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             114860                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1504938                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                402                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1504870                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1504468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2480                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              58757                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             489769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          598                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              13987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             143636                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         1826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker         1775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              41510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             346036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2616154                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        440433                       # Number of read requests accepted
-system.physmem.writeReqs                       603232                       # Number of write requests accepted
-system.physmem.readBursts                      440433                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     603232                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28170752                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     16960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  38511488                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28187712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               38606848                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      265                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    1490                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          18504                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25157                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28496                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28335                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27633                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27808                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               30320                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26148                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26657                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               26790                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29797                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28841                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              30668                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26625                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26518                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25131                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25244                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               36236                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               36759                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               37480                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               39199                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               39135                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               41156                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               37007                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               36943                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               37618                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               39787                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              38447                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              38818                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              34864                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              36482                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              35714                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              36097                       # Per bank write bursts
+system.physmem.bw_write::total                1505340                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1504938                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2535                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              56676                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             487751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          675                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          583                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              15842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             143432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker         1847                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker         1743                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              42342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             346913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2615783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        443127                       # Number of read requests accepted
+system.physmem.writeReqs                       607625                       # Number of write requests accepted
+system.physmem.readBursts                      443127                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     607625                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28344960                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     15168                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  38801344                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28360128                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               38888000                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      237                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1354                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          18550                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25211                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               29295                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               27890                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               27887                       # Per bank write bursts
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+system.physmem.perBankRdBursts::5               30839                       # Per bank write bursts
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+system.physmem.perBankRdBursts::11              31219                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26466                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26838                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25148                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25956                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               36103                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               37925                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               36544                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               38823                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               41056                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               42229                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               37594                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               36950                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               37999                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               38649                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              38477                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              38558                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              34649                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              36757                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              36686                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              37272                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51233791781500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51233787261500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  440433                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  443127                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 603232                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    309302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     89084                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::4                       102                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 607625                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         9                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -180,220 +180,199 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples       270943                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      246.111691                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     146.841271                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     289.814348                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         123351     45.53%     45.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        67798     25.02%     70.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        24089      8.89%     79.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        12477      4.61%     84.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8623      3.18%     87.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         5501      2.03%     89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4269      1.58%     90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3914      1.44%     92.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20921      7.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         270943                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         29531                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.905286                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       10.293446                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-15            12117     41.03%     41.03% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16-31           16080     54.45%     95.48% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-47            1080      3.66%     99.14% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-63             183      0.62%     99.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-79              43      0.15%     99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::80-95              13      0.04%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-111              6      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::112-127             3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-143             3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::176-191             2      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::320-335             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           29531                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         29531                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.376621                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.754514                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.014003                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 5      0.02%      0.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                10      0.03%      0.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               10      0.03%      0.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              38      0.13%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           24052     81.45%     81.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2161      7.32%     88.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             399      1.35%     90.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             574      1.94%     92.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             563      1.91%     94.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             287      0.97%     95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             195      0.66%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             150      0.51%     96.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             203      0.69%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              86      0.29%     97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              51      0.17%     97.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              59      0.20%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             110      0.37%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              84      0.28%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              56      0.19%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              59      0.20%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              85      0.29%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              34      0.12%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              26      0.09%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              18      0.06%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              70      0.24%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            10      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             9      0.03%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             9      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            14      0.05%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             8      0.03%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             6      0.02%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             7      0.02%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            32      0.11%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             9      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             7      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             7      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             8      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             3      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             2      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           29531                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10316676500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               18569826500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2200840000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23438.04                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::55                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       31                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       274343                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      244.749383                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     146.139289                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     288.784627                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         125431     45.72%     45.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        68607     25.01%     70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        24542      8.95%     79.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        12363      4.51%     84.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8633      3.15%     87.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         5464      1.99%     89.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4467      1.63%     90.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3979      1.45%     92.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20857      7.60%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         274343                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         29886                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.819313                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       10.330264                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-15            12451     41.66%     41.66% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16-31           16121     53.94%     95.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-47            1059      3.54%     99.15% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::48-63             175      0.59%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-79              53      0.18%     99.91% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::80-95              15      0.05%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-111              5      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::112-127             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-143             2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::160-175             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-271             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::304-319             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           29886                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         29886                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.286121                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.739916                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.649180                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                14      0.05%      0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15               35      0.12%      0.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           26501     88.67%     88.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            1006      3.37%     92.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             913      3.05%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             433      1.45%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             255      0.85%     97.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              96      0.32%     97.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             167      0.56%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             135      0.45%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              90      0.30%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              37      0.12%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             67      0.22%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            27      0.09%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            22      0.07%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127            15      0.05%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            37      0.12%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             6      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             7      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             3      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           29886                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10134279500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               18438467000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2214450000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22882.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42188.04                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  41632.16                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.75                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.76                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.55                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.75                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.76                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     332271                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    438696                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.49                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.90                       # Row buffer hit rate for writes
-system.physmem.avgGap                     49090265.35                       # Average gap between requests
-system.physmem.pageHitRate                      74.00                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49384314860250                       # Time in different power states
-system.physmem.memoryStateTime::REF      1710848620000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      139817808500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                1046447640                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                1001881440                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 570978375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 546661500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1720321200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1712989200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              1969369200                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              1929918960                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3346419900720                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3346419900720                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1177540520625                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1174853241090                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29708058483750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29710415746500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34237326021510                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34236880339410                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.241213                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.232514                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        20.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     333517                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    441289                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.30                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                     48759162.26                       # Average gap between requests
+system.physmem.pageHitRate                      73.85                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1059231600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  575701500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1730999400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1990714320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3304502351280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1163638516455                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29573392417500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34046889932055                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.714209                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48801846776250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1689418380000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    103138521750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 1014703200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  551648625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1723542600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1937720880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3304502351280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1160546619285                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29579668954500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34049945540370                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.696345                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48806318983250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1689418380000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     98691186250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -401,6 +380,14 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -422,27 +409,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   113519                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               113519                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples       113519                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         113519    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       113519                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 1125423795568                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.567721                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.495393                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   486496827068     43.23%     43.23% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   638926968500     56.77%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1125423795568                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        82853     84.60%     84.60% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        15081     15.40%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        97934                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       113519                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       113519                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        97934                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        97934                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       211453                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    78485873                       # DTB read hits
-system.cpu0.dtb.read_misses                     85123                       # DTB read misses
-system.cpu0.dtb.write_hits                   72027961                       # DTB write hits
-system.cpu0.dtb.write_misses                    28205                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1285                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    78562985                       # DTB read hits
+system.cpu0.dtb.read_misses                     85240                       # DTB read misses
+system.cpu0.dtb.write_hits                   72018023                       # DTB write hits
+system.cpu0.dtb.write_misses                    28279                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1287                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21048                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    509                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   51602                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              21013                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   51639                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4002                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3776                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9811                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                78570996                       # DTB read accesses
-system.cpu0.dtb.write_accesses               72056166                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9794                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                78648225                       # DTB read accesses
+system.cpu0.dtb.write_accesses               72046302                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        150513834                       # DTB hits
-system.cpu0.dtb.misses                         113328                       # DTB misses
-system.cpu0.dtb.accesses                    150627162                       # DTB accesses
+system.cpu0.dtb.hits                        150581008                       # DTB hits
+system.cpu0.dtb.misses                         113519                       # DTB misses
+system.cpu0.dtb.accesses                    150694527                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -464,411 +480,432 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   421004293                       # ITB inst hits
-system.cpu0.itb.inst_misses                     63363                       # ITB inst misses
+system.cpu0.itb.walker.walks                    63212                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                63212                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        63212                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          63212    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        63212                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 1125423794068                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.567766                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.495387                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   486446960568     43.22%     43.22% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   638976833500     56.78%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 1125423794068                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        54978     95.14%     95.14% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2806      4.86%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        57784                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        63212                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        63212                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        57784                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        57784                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       120996                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   421062407                       # ITB inst hits
+system.cpu0.itb.inst_misses                     63212                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1285                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1287                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21048                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    509                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   36267                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21013                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   36180                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               421067656                       # ITB inst accesses
-system.cpu0.itb.hits                        421004293                       # DTB hits
-system.cpu0.itb.misses                          63363                       # DTB misses
-system.cpu0.itb.accesses                    421067656                       # DTB accesses
-system.cpu0.numCycles                       506516508                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               421125619                       # ITB inst accesses
+system.cpu0.itb.hits                        421062407                       # DTB hits
+system.cpu0.itb.misses                          63212                       # DTB misses
+system.cpu0.itb.accesses                    421125619                       # DTB accesses
+system.cpu0.numCycles                       506570818                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  420811760                       # Number of instructions committed
-system.cpu0.committedOps                    495213745                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            454628715                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                411957                       # Number of float alu accesses
-system.cpu0.num_func_calls                   25378118                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     63987651                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   454628715                       # number of integer instructions
-system.cpu0.num_fp_insts                       411957                       # number of float instructions
-system.cpu0.num_int_register_reads          670075882                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         361231436                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              665979                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             343448                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           110680974                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          110422200                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    150607491                       # number of memory refs
-system.cpu0.num_load_insts                   78559078                       # Number of load instructions
-system.cpu0.num_store_insts                  72048413                       # Number of store instructions
-system.cpu0.num_idle_cycles              494422986.191521                       # Number of idle cycles
-system.cpu0.num_busy_cycles              12093521.808479                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023876                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976124                       # Percentage of idle cycles
-system.cpu0.Branches                         93934421                       # Number of branches fetched
+system.cpu0.committedInsts                  420869800                       # Number of instructions committed
+system.cpu0.committedOps                    495253800                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            454669961                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                407169                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25355566                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     64011433                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   454669961                       # number of integer instructions
+system.cpu0.num_fp_insts                       407169                       # number of float instructions
+system.cpu0.num_int_register_reads          669912724                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         361261423                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              658306                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             339356                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           110690043                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          110438637                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    150674741                       # number of memory refs
+system.cpu0.num_load_insts                   78636195                       # Number of load instructions
+system.cpu0.num_store_insts                  72038546                       # Number of store instructions
+system.cpu0.num_idle_cycles              494843268.961767                       # Number of idle cycles
+system.cpu0.num_busy_cycles              11727549.038232                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023151                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976849                       # Percentage of idle cycles
+system.cpu0.Branches                         93932517                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                343753597     69.37%     69.37% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1048568      0.21%     69.59% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    47671      0.01%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             50027      0.01%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
-system.cpu0.op_class::MemRead                78559078     15.85%     85.46% # Class of executed instruction
-system.cpu0.op_class::MemWrite               72048413     14.54%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                343715794     69.36%     69.36% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1059861      0.21%     69.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47874      0.01%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             49044      0.01%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
+system.cpu0.op_class::MemRead                78636195     15.87%     85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite               72038546     14.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 495507356                       # Class of executed instruction
+system.cpu0.op_class::total                 495547316                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   16313                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements         10203749                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          304434614                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10204261                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            29.834068                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements         10214702                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999720                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          304791830                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10215214                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            29.837048                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.228127                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.974365                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data    10.797225                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969196                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.009716                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.021088                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.816800                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.965643                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    10.217276                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970345                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.009699                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.019956                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          210                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          289                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          206                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1294524003                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1294524003                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     73268923                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     23739594                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     59414779                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      156423296                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68111490                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     21735522                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     49847350                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     139694362                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       193034                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        58570                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data       140375                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       391979                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       149338                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data        52269                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data       129188                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       330795                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1809029                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       564897                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1231072                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3604998                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1922189                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       609751                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data      1411604                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3943544                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    141380413                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     45475116                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data    109262129                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       296117658                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    141573447                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     45533686                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data    109402504                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      296509637                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2527678                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       793028                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data      4769702                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      8090408                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1085359                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       334528                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data      4280292                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5700179                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       626966                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       195030                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       455384                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1277380                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       755062                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       138919                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data       339873                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1233854                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       114004                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        45120                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data       230004                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       389128                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1295808199                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1295808199                       # Number of data accesses
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu2.data            4                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
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-system.cpu0.dcache.overall_misses::total     15067967                       # number of overall misses
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-system.cpu0.dcache.ReadReq_miss_latency::total  93864325662                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9781004455                       # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 167855762892                       # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  13056314208                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    651998250                       # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3879059286                       # number of LoadLockedReq miss cycles
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 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       150500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        64001                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       214501                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  21870126705                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 239849961849                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 261720088554                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  21870126705                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 239849961849                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 261720088554                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     75796601                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       820000                       # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       595759                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1669359                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       904400                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       191188                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       469061                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1564649                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1923033                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       610017                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1461076                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3994126                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1922190                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       609753                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1411608                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3943551                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    144993450                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     46602672                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data    118312123                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    309908245                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    145813450                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     46856272                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data    118907882                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    311577604                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033348                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032325                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.074312                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.049178                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015685                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015158                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.079078                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.039205                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764593                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.769046                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.764376                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765192                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.834876                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.726609                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data     0.724582                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.788582                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059283                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.073965                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.157421                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.097425                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        64501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       215001                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  21878294618                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 238126674746                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 260004969364                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  21878294618                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 238126674746                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 260004969364                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     75878111                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     24459618                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     64306963                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    164644692                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     69192221                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     22030141                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     54355609                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    145577971                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       817098                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       259394                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       592619                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1669111                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       900518                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       194664                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       469441                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1564623                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1921757                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       599224                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1474672                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3995653                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1920928                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       598966                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1426299                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3946193                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    145070332                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     46489759                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data    118662572                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    310222663                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    145887430                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     46749153                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data    119255191                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    311891774                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033396                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032272                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.073798                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.049009                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015645                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015409                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.078320                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.039011                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764812                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.772832                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.762377                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765194                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.834399                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.728409                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data     0.726372                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.788800                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059412                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.072554                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.159217                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.098218                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024919                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024195                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.076493                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044499                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029078                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028226                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079939                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048360                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.256508                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17144.719610                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11601.927327                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29238.223572                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36930.835195                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29447.454701                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17658.567244                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31197.546451                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10581.733502                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14450.315824                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14030.456149                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9968.594617                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024930                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024281                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.075869                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.044317                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029074                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028434                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079281                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048175                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15256.778584                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17154.258300                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11581.482010                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28973.297407                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36813.017170                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29327.242340                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17614.478663                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31245.049820                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10656.400668                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14692.893780                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14032.145473                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10022.927557                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        75250                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000.250000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        30643                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19396.044813                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26502.775786                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18978.168845                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16535.882510                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25233.079826                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17369.303275                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     16646814                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        16737                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          1171436                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            381                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.210605                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    43.929134                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30714.428571                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19381.596163                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26450.190545                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18911.895047                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16458.681291                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25186.241999                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17304.342992                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     16525094                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        18605                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          1165104                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            417                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.183364                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    44.616307                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7869277                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7869277                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         1021                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2728886                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2729907                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         3191                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3547950                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3551141                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data         2444                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         2444                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        10468                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       139963                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       150431                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         4212                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data      6276836                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      6281048                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         4212                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data      6276836                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      6281048                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       792007                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2040816                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2832823                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       331337                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       732342                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1063679                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       194976                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       448304                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       643280                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       138919                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data       337429                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       476348                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        34652                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        90041                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       124693                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7876656                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7876656                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         1060                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2696706                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2697766                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         3203                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3527121                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3530324                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data         2450                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         2450                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        10619                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       143143                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       153762                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         4263                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data      6223827                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      6228090                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         4263                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data      6223827                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      6228090                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       788301                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2049006                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2837307                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       336254                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       730001                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1066255                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       200411                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       444940                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       645351                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       141795                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data       338539                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       480334                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        32857                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        91650                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       124507                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      1123344                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      2773158                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      3896502                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1318320                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      3221462                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4539782                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10425295500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30694668987                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41119964487                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8981852045                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  24997038072                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33978890117                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2907550500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   9282645690                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  12190196190                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2175272497                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data   9841405614                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  12016678111                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    423668250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1137848378                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1561516628                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      1124555                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      2779007                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      3903562                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1324966                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      3223947                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4548913                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10385481000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30772790199                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41158271199                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9025287882                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  24823347673                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33848635555                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2966996500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   9186505955                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  12153502455                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   2214054998                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data   9890086456                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  12104141454                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    409377500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1158107131                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1567484631                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       146500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        55999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       202499                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19407147545                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  55691707059                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  75098854604                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22314698045                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  64974352749                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  87289050794                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    887936500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1414128501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2302065001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    802092250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1441281461                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2243373711                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1690028750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2855409962                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4545438712                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032284                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031796                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017219                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015013                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013530                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007316                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.768833                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.752492                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.385346                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.726609                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.719371                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.304444                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056805                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.061626                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.031219                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        56499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       202999                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19410768882                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  55596137872                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  75006906754                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22377765382                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  64782643827                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  87160409209                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    886387500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1429299000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2315686500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    799886500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1453115957                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2253002457                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1686274000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2882414957                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4568688957                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032229                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031863                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017233                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015263                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013430                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007324                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.772612                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.750803                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.386644                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.728409                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.721153                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.306997                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054833                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.062149                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.031161                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024105                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023439                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.012573                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028135                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027092                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.014570                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13163.135553                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15040.390210                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14515.543148                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27107.905380                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34133.011724                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31944.684550                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14912.350751                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20706.140677                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18950.062477                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15658.567201                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29165.855970                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25226.679048                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12226.372215                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12637.002899                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12522.889240                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024189                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023419                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.012583                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028342                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027034                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.014585                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13174.512020                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15018.399262                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14506.104274                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26840.685559                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34004.539272                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31745.347553                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14804.559131                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20646.617420                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18832.391141                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15614.478635                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29214.023956                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25199.426761                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12459.369389                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12636.193464                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12589.530155                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        73250                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13999.750000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33749.833333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17276.228426                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20082.414006                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19273.403325                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16926.617244                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20169.212845                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19227.586433                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33833.166667                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17260.844407                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20005.756686                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19214.990502                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16889.312920                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20094.202488                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19160.711407                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -879,143 +916,151 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         14506041                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.977027                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          610832898                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         14506553                       # Sample count of references to valid blocks.
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 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
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 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
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-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.850868                       # average overall mshr miss latency
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+system.cpu0.icache.demand_mshr_misses::cpu1.inst      2066459                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      5847297                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      7913756                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      2066459                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      5847297                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      7913756                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  23615838750                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  68291553899                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  91907392649                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  23615838750                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  68291553899                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  91907392649                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  23615838750                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  68291553899                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  91907392649                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015337                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.083401                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012642                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015337                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.083401                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012642                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015337                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.083401                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012642                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11428.167096                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11679.166271                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11613.624763                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11428.167096                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11679.166271                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11613.624763                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11428.167096                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11679.166271                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11613.624763                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1037,27 +1082,80 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                    39379                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                39379                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         5977                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        28234                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        39373                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.279379                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    55.436197                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-1023        39372    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::10240-11263            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        39373                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        34217                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21462.701289                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17640.355852                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13201.639709                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        33415     97.66%     97.66% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535          571      1.67%     99.32% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          171      0.50%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071           26      0.08%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            5      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607            9      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            6      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            6      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        34217                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1508431008                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.298098                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.457423                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1058770000     70.19%     70.19% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1      449661008     29.81%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1508431008                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        28234     82.53%     82.53% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         5977     17.47%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        34211                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        39379                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        39379                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        34211                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        34211                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        73590                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    25401715                       # DTB read hits
-system.cpu1.dtb.read_misses                     30145                       # DTB read misses
-system.cpu1.dtb.write_hits                   22878884                       # DTB write hits
-system.cpu1.dtb.write_misses                     9290                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    25323699                       # DTB read hits
+system.cpu1.dtb.read_misses                     30085                       # DTB read misses
+system.cpu1.dtb.write_hits                   22831654                       # DTB write hits
+system.cpu1.dtb.write_misses                     9294                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1278                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               6765                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    155                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   21663                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               6693                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    149                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   21869                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1295                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  1270                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     3011                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                25431860                       # DTB read accesses
-system.cpu1.dtb.write_accesses               22888174                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     3016                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25353784                       # DTB read accesses
+system.cpu1.dtb.write_accesses               22840948                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         48280599                       # DTB hits
-system.cpu1.dtb.misses                          39435                       # DTB misses
-system.cpu1.dtb.accesses                     48320034                       # DTB accesses
+system.cpu1.dtb.hits                         48155353                       # DTB hits
+system.cpu1.dtb.misses                          39379                       # DTB misses
+system.cpu1.dtb.accesses                     48194732                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1079,98 +1177,143 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   134812630                       # ITB inst hits
-system.cpu1.itb.inst_misses                     23831                       # ITB inst misses
+system.cpu1.itb.walker.walks                    23659                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                23659                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1141                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        20683                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        23659                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          23659    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        23659                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        21824                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24542.418897                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21182.327207                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14187.388293                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        20284     92.94%     92.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         1308      5.99%     98.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          160      0.73%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071           37      0.17%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.04%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607            6      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375            7      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            4      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            4      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        21824                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        20683     94.77%     94.77% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1141      5.23%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        21824                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        23659                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        23659                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        21824                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        21824                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        45483                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   134740091                       # ITB inst hits
+system.cpu1.itb.inst_misses                     23659                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1276                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1278                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               6765                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    155                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   16095                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               6693                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    149                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   16092                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               134836461                       # ITB inst accesses
-system.cpu1.itb.hits                        134812630                       # DTB hits
-system.cpu1.itb.misses                          23831                       # DTB misses
-system.cpu1.itb.accesses                    134836461                       # DTB accesses
-system.cpu1.numCycles                      1276129163                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               134763750                       # ITB inst accesses
+system.cpu1.itb.hits                        134740091                       # DTB hits
+system.cpu1.itb.misses                          23659                       # DTB misses
+system.cpu1.itb.accesses                    134763750                       # DTB accesses
+system.cpu1.numCycles                      1278124825                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  134717323                       # Number of instructions committed
-system.cpu1.committedOps                    158229449                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            145215192                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                135383                       # Number of float alu accesses
-system.cpu1.num_func_calls                    7898602                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     20639469                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   145215192                       # number of integer instructions
-system.cpu1.num_fp_insts                       135383                       # number of float instructions
-system.cpu1.num_int_register_reads          211626069                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         115298933                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              217457                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             117636                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            35416182                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           35358802                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     48278390                       # number of memory refs
-system.cpu1.num_load_insts                   25401257                       # Number of load instructions
-system.cpu1.num_store_insts                  22877133                       # Number of store instructions
-system.cpu1.num_idle_cycles              1248602360.762588                       # Number of idle cycles
-system.cpu1.num_busy_cycles              27526802.237412                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.021571                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.978429                       # Percentage of idle cycles
-system.cpu1.Branches                         30073331                       # Number of branches fetched
+system.cpu1.committedInsts                  134646225                       # Number of instructions committed
+system.cpu1.committedOps                    158126706                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            145069492                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                137737                       # Number of float alu accesses
+system.cpu1.num_func_calls                    7885244                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     20644863                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   145069492                       # number of integer instructions
+system.cpu1.num_fp_insts                       137737                       # number of float instructions
+system.cpu1.num_int_register_reads          212132646                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         115229722                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              221669                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             118820                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            35576682                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           35511484                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     48152949                       # number of memory refs
+system.cpu1.num_load_insts                   25322940                       # Number of load instructions
+system.cpu1.num_store_insts                  22830009                       # Number of store instructions
+system.cpu1.num_idle_cycles              1251340382.439470                       # Number of idle cycles
+system.cpu1.num_busy_cycles              26784442.560530                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.020956                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.979044                       # Percentage of idle cycles
+system.cpu1.Branches                         30070128                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                109658909     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                  355788      0.22%     69.49% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    13920      0.01%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             17708      0.01%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
-system.cpu1.op_class::MemRead                25401257     16.04%     85.55% # Class of executed instruction
-system.cpu1.op_class::MemWrite               22877133     14.45%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                109684380     69.32%     69.32% # Class of executed instruction
+system.cpu1.op_class::IntMult                  350403      0.22%     69.55% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    14329      0.01%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             18470      0.01%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::MemRead                25322940     16.00%     85.57% # Class of executed instruction
+system.cpu1.op_class::MemWrite               22830009     14.43%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 158324756                       # Class of executed instruction
+system.cpu1.op_class::total                 158220572                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               96972708                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         66097998                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          4361259                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            65994487                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               47080178                       # Number of BTB hits
+system.cpu2.branchPred.lookups               97203672                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         66186757                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          4359750                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            65808751                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               47109720                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.339562                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS               12396082                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            131444                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            71.585799                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS               12465679                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            131865                       # Number of incorrect RAS predictions.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1192,27 +1335,89 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu2.dtb.walker.walks                   641865                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong               641865                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2        11159                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        66692                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksSquashedBefore       388613                       # Table walks squashed before starting
+system.cpu2.dtb.walker.walkWaitTime::samples       253252                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::mean  1931.812977                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::stdev 11499.357470                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0-65535       251854     99.45%     99.45% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::65536-131071         1074      0.42%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::131072-196607          172      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::196608-262143           83      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::262144-327679           31      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::327680-393215           33      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total       253252                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples       288612                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 20860.236245                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 16529.214515                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 15237.417207                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-65535       285772     99.02%     99.02% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-131071         2386      0.83%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-196607          259      0.09%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-262143          137      0.05%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-327679           41      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-393215            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total       288612                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 644386966916                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::mean     0.557890                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::stdev     0.603276                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0-3 643756648416     99.90%     99.90% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::4-7    358289000      0.06%     99.96% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::8-11    119891000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::12-15     74898000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::16-19     28944500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::20-23     14290500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::24-27     13699500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::28-31     16934500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::32-35      3107500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::36-39       253000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::40-43        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 644386966916                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K        66692     85.67%     85.67% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M        11159     14.33%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        77851                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data       641865                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total       641865                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        77851                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        77851                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       719716                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    77639620                       # DTB read hits
-system.cpu2.dtb.read_misses                    447330                       # DTB read misses
-system.cpu2.dtb.write_hits                   59480935                       # DTB write hits
-system.cpu2.dtb.write_misses                   199454                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    77755602                       # DTB read hits
+system.cpu2.dtb.read_misses                    445998                       # DTB read misses
+system.cpu2.dtb.write_hits                   59736492                       # DTB write hits
+system.cpu2.dtb.write_misses                   195867                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1279                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid              14382                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    391                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   38430                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       78                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  6154                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid              14489                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    395                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   38251                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      105                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  6104                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                    38837                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                78086950                       # DTB read accesses
-system.cpu2.dtb.write_accesses               59680389                       # DTB write accesses
+system.cpu2.dtb.perms_faults                    37697                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                78201600                       # DTB read accesses
+system.cpu2.dtb.write_accesses               59932359                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                        137120555                       # DTB hits
-system.cpu2.dtb.misses                         646784                       # DTB misses
-system.cpu2.dtb.accesses                    137767339                       # DTB accesses
+system.cpu2.dtb.hits                        137492094                       # DTB hits
+system.cpu2.dtb.misses                         641865                       # DTB misses
+system.cpu2.dtb.accesses                    138133959                       # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1234,161 +1439,221 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                    70053409                       # ITB inst hits
-system.cpu2.itb.inst_misses                     78615                       # ITB inst misses
+system.cpu2.itb.walker.walks                    80363                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                80363                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         2481                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        55642                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksSquashedBefore        10291                       # Table walks squashed before starting
+system.cpu2.itb.walker.walkWaitTime::samples        70072                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::mean  1335.283708                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::stdev  8007.621087                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0-32767        69580     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::32768-65535          258      0.37%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::65536-98303          168      0.24%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::98304-131071           29      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::131072-163839           18      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::163840-196607            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::196608-229375            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::262144-294911            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        70072                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        68414                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 25615.416172                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 21446.317164                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 15929.809681                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        60316     88.16%     88.16% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535         7055     10.31%     98.48% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303          610      0.89%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071          277      0.40%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839           68      0.10%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           37      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375           13      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143           11      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::360448-393215            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        68414                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 468293315780                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::mean     0.887572                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::stdev     0.316276                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0    52695891356     11.25%     11.25% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::1   415558218424     88.74%     99.99% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::2       33808000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::3        3984500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::4         940500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::5         404000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::6          21500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::7          47500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 468293315780                       # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K        55642     95.73%     95.73% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         2481      4.27%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        58123                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        80363                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        80363                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        58123                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        58123                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total       138486                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    70281222                       # ITB inst hits
+system.cpu2.itb.inst_misses                     80363                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1277                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1279                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid              14382                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    391                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   29938                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid              14489                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    395                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   29841                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                   146701                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                   147172                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                70132024                       # ITB inst accesses
-system.cpu2.itb.hits                         70053409                       # DTB hits
-system.cpu2.itb.misses                          78615                       # DTB misses
-system.cpu2.itb.accesses                     70132024                       # DTB accesses
-system.cpu2.numCycles                       464363800                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                70361585                       # ITB inst accesses
+system.cpu2.itb.hits                         70281222                       # DTB hits
+system.cpu2.itb.misses                          80363                       # DTB misses
+system.cpu2.itb.accesses                     70361585                       # DTB accesses
+system.cpu2.numCycles                       465003102                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles         179489584                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     430854602                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   96972708                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          59476260                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    257591256                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                9826419                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                   1844126                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                7503                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             2868                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles      3763568                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       118840                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         3975                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                 69883749                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes              2672352                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                  30337                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         447734787                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.124399                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.366335                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles         180276648                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     431826640                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   97203672                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          59575399                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    257301281                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                9838745                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                   1858453                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                8409                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1979                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles      3769521                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       119476                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         4195                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                 70111000                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes              2676908                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                  31653                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         448259178                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.125687                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.367693                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0               341635028     76.30%     76.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                13406310      2.99%     79.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                13636635      3.05%     82.34% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 9872032      2.20%     84.55% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                19981367      4.46%     89.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                 6599798      1.47%     90.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 7144304      1.60%     92.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                 6328128      1.41%     93.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                29131185      6.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0               341932387     76.28%     76.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                13442109      3.00%     79.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                13673824      3.05%     82.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 9898176      2.21%     84.54% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                19945540      4.45%     88.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                 6633561      1.48%     90.47% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 7181223      1.60%     92.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                 6340938      1.41%     93.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                29211420      6.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           447734787                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.208829                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.927838                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles               146627317                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles            209331987                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 78382912                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              9473245                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               3917341                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved            14361500                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred              1009950                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts             470418171                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts              3106090                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               3917341                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles               152067726                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               18239112                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles     166025180                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 82266415                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             25216691                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             459074168                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                65027                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               1852942                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents               1258209                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents              11783264                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.FullRegisterEvents            3675                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands          439034296                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            699577887                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       541505861                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups           695779                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            366271083                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                72763213                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts          10011965                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts       8575733                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 52414102                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads            74518711                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores           62619461                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads          9405778                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores        10283621                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 436211457                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded            9985811                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                434881060                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           606856                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined       56709441                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     39627449                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        236091                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    447734787                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.971292                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.683506                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           448259178                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.209039                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.928653                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles               147221492                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles            209051737                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 78610938                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              9453516                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               3919439                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved            14421531                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred              1013878                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts             471467563                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts              3120361                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               3919439                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles               152659562                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               18224952                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles     165892682                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 82476717                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             25083567                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             460107253                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                59923                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               1862817                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents               1245864                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents              11710592                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.FullRegisterEvents            3796                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands          439693345                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            700325975                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       542687716                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups           700561                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            367082877                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                72610468                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts           9962331                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts       8523572                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 52244758                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads            74674759                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores           62877107                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads          9528051                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores        10323504                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 437324992                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded            9951593                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                435965427                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           606984                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined       56598171                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     39504404                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        237598                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    448259178                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.972574                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.684760                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0          279611354     62.45%     62.45% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1           68418670     15.28%     77.73% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2           31957007      7.14%     84.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3           22824194      5.10%     89.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           17260103      3.85%     93.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5           11876528      2.65%     96.47% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6            7949958      1.78%     98.25% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7            4742790      1.06%     99.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8            3094183      0.69%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0          279914977     62.44%     62.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1           68317821     15.24%     77.69% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2           32057682      7.15%     84.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3           22901153      5.11%     89.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           17277675      3.85%     93.80% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5           11955785      2.67%     96.47% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6            7990147      1.78%     98.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7            4753228      1.06%     99.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8            3090710      0.69%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      447734787                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      448259178                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                2194515     25.29%     25.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                 17472      0.20%     25.49% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                   1369      0.02%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               1      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.50% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               3568581     41.12%     66.62% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite              2897037     33.38%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                2208249     25.46%     25.46% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                 17979      0.21%     25.67% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                   1386      0.02%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               1      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               3543832     40.86%     66.55% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite              2901485     33.45%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            294218561     67.65%     67.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult             1060208      0.24%     67.90% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                49487      0.01%     67.91% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                203      0.00%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            294954302     67.66%     67.66% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult             1046783      0.24%     67.90% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                49286      0.01%     67.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                204      0.00%     67.91% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     67.91% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     67.91% # Type of FU issued
 system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     67.91% # Type of FU issued
@@ -1410,156 +1675,156 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.91% # Ty
 system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.91% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.91% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.91% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc         49890      0.01%     67.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc         50291      0.01%     67.92% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     67.92% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.92% # Type of FU issued
 system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.92% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            79213886     18.22%     86.14% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite           60288825     13.86%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            79323839     18.19%     86.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite           60540722     13.89%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             434881060                       # Type of FU issued
-system.cpu2.iq.rate                          0.936509                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    8678975                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.019957                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads        1325952907                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        503003259                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    418204813                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             829831                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            395434                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       359511                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             443116084                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 443951                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads         3398365                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             435965427                       # Type of FU issued
+system.cpu2.iq.rate                          0.937554                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    8672932                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.019894                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads        1328634186                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        503978442                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    419353037                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             835762                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            397688                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       361980                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             444191291                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 447068                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads         3425545                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads     12383710                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses        15996                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation       500564                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores      6611339                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads     12352202                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses        15972                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation       509888                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores      6626020                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      2691934                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked      6258076                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      2713782                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked      6189069                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               3917341                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               10960428                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              5883186                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          446296417                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts          1350381                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts             74518711                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts            62619461                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts           8384922                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                176072                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              5630257                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents        500564                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect       2018361                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect      1727301                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts             3745662                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            429773841                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             77626990                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts          4469356                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               3919439                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               10963120                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              5851568                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          447374999                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts          1338773                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts             74674759                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts            62877107                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts           8331773                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                175433                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              5598830                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents        509888                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect       2010429                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect      1729641                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts             3740070                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            430866261                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             77742862                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts          4466264                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        99149                       # number of nop insts executed
-system.cpu2.iew.exec_refs                   137107534                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                79765421                       # Number of branches executed
-system.cpu2.iew.exec_stores                  59480544                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.925511                       # Inst execution rate
-system.cpu2.iew.wb_sent                     419443427                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    418564324                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                206922501                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                359375214                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        98414                       # number of nop insts executed
+system.cpu2.iew.exec_refs                   137478821                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                79993995                       # Number of branches executed
+system.cpu2.iew.exec_stores                  59735959                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.926588                       # Inst execution rate
+system.cpu2.iew.wb_sent                     420591447                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    419715017                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                207428552                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                360230847                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.901372                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.575784                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.902607                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.575821                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts       60955622                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls        9749720                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts          3365248                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    437429844                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.880802                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.877626                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts       60870503                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls        9713995                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts          3359660                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    437963055                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.882384                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.879484                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0    298552711     68.25%     68.25% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1     66327454     15.16%     83.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2     24603217      5.62%     89.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     11085486      2.53%     91.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4      7951378      1.82%     93.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5      4924801      1.13%     94.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6      4385642      1.00%     95.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7      3037837      0.69%     96.21% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8     16561318      3.79%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0    298875540     68.24%     68.24% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1     66218430     15.12%     83.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2     24721461      5.64%     89.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     11149325      2.55%     91.55% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      8001884      1.83%     93.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5      4923567      1.12%     94.50% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6      4422174      1.01%     95.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7      3021510      0.69%     96.20% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8     16629164      3.80%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    437429844                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           328410291                       # Number of instructions committed
-system.cpu2.commit.committedOps             385289118                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    437963055                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           329380138                       # Number of instructions committed
+system.cpu2.commit.committedOps             386451624                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                     118143123                       # Number of memory references committed
-system.cpu2.commit.loads                     62135001                       # Number of loads committed
-system.cpu2.commit.membars                    2566531                       # Number of memory barriers committed
-system.cpu2.commit.branches                  73369628                       # Number of branches committed
-system.cpu2.commit.fp_insts                    345769                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                353907438                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls             9528374                       # Number of function calls committed.
+system.cpu2.commit.refs                     118573644                       # Number of memory references committed
+system.cpu2.commit.loads                     62322557                       # Number of loads committed
+system.cpu2.commit.membars                    2596368                       # Number of memory barriers committed
+system.cpu2.commit.branches                  73601182                       # Number of branches committed
+system.cpu2.commit.fp_insts                    348235                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                355043998                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls             9589619                       # Number of function calls committed.
 system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       266264239     69.11%     69.11% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult         801904      0.21%     69.32% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           36966      0.01%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc        42886      0.01%     69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.34% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead       62135001     16.13%     85.46% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite      56008122     14.54%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       267002089     69.09%     69.09% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult         796041      0.21%     69.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           36743      0.01%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc        43107      0.01%     69.32% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.32% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.32% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.32% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead       62322557     16.13%     85.44% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite      56251087     14.56%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        385289118                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events             16561318                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        386451624                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events             16629164                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   864512984                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  902807617                       # The number of ROB writes
-system.cpu2.timesIdled                        2960923                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       16629013                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                 99452987332                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  328410291                       # Number of Instructions Simulated
-system.cpu2.committedOps                    385289118                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.413975                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.413975                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.707226                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.707226                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               505452117                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              299365113                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                   681432                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                  426556                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                 91860984                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes                92633679                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads             1668736685                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes               9854923                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40323                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40323                       # Transaction distribution
+system.cpu2.rob.rob_reads                   866035132                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  904953656                       # The number of ROB writes
+system.cpu2.timesIdled                        2976137                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       16743924                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                 99448354933                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  329380138                       # Number of Instructions Simulated
+system.cpu2.committedOps                    386451624                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.411752                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.411752                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.708340                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.708340                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               506713870                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              300217827                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                   684649                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                  429068                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                 91867416                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes                92641749                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads             1672272175                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes               9817116                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40335                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40335                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136665                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30001                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1579,11 +1844,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230968                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230968                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354000                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48090                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1600,18 +1865,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156082                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334304                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13663000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492472                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13687000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             7273000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             7449000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy               33000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
@@ -1619,67 +1884,67 @@ system.iobus.reqLayer25.occupancy            16992000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           330247943                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           331631076                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            38409000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            38629000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36054619                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36767371                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              144000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115453                       # number of replacements
-system.iocache.tags.tagsinuse               10.417239                       # Cycle average of tags in use
+system.iocache.tags.replacements               115465                       # number of replacements
+system.iocache.tags.tagsinuse               10.417241                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13085938891009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         13085934181009                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.549977                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.867262                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.867264                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221874                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.429204                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651077                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651078                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039605                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039713                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039713                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8820                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8857                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8808                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8848                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8820                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8860                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8808                       # number of overall misses
-system.iocache.overall_misses::total             8848                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8820                       # number of overall misses
+system.iocache.overall_misses::total             8860                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      2752000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide     58617716                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     61369716                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9336377608                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   9336377608                       # number of WriteInvalidateReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     78330160                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     81082160                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9376503545                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   9376503545                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      2752000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide     58617716                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     61369716                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide     78330160                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     81082160                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      2752000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide     58617716                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     61369716                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide     78330160                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     81082160                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8820                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8857                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8808                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8848                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8820                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8860                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8808                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8848                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8820                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8860                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1694,414 +1959,415 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide  6655.054042                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total  6938.351159                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87530.728343                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 87530.728343                       # average WriteInvalidateReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide  8880.970522                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total  9154.585074                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87906.918407                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 87906.918407                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide  6655.054042                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total  6935.998644                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide  8880.970522                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total  9151.485327                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide  6655.054042                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total  6935.998644                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         56930                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide  8880.970522                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total  9151.485327                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         58174                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7229                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7340                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.875225                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.925613                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           16                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide          391                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          407                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        34376                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        34376                       # number of WriteInvalidateReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          459                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        34504                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        34504                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           16                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          391                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          407                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          459                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          475                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           16                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          391                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          407                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          459                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          475                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      1920000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     38284716                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     40204716                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7548587846                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7548587846                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     54458660                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     56378660                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7582053787                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7582053787                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      1920000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     38284716                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     40204716                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     54458660                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     56378660                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      1920000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     38284716                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     40204716                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     54458660                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     56378660                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet     0.432432                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.046015                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.322283                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.322283                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.052041                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.053630                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide     0.323483                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.323483                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.045999                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.052041                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.053612                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.044391                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.045999                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.052041                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.053612                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet       120000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 97914.874680                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 98783.085995                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219588.894752                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219588.894752                       # average WriteInvalidateReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 118646.318083                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 118691.915789                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219744.197397                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219744.197397                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 97914.874680                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 98783.085995                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 118646.318083                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 118691.915789                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 97914.874680                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 98783.085995                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 118646.318083                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 118691.915789                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1295349                       # number of replacements
-system.l2c.tags.tagsinuse                65279.372199                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   28812912                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1358291                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.212621                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1296056                       # number of replacements
+system.l2c.tags.tagsinuse                65324.265743                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   28829950                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1358778                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.217557                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37161.709727                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   165.709328                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   242.089797                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3863.683177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8425.677492                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    52.724328                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    79.048207                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      858.449063                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3027.055416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker   115.755562                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker   187.843721                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2139.828130                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     8959.798251                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.567043                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002529                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003694                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.058955                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.128566                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000805                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001206                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.013099                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.046189                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001766                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.002866                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.032651                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.136716                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996084                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          299                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62643                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          299                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          576                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2774                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4979                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54179                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004562                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.955856                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                273263421                       # Number of tag accesses
-system.l2c.tags.data_accesses               273263421                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       201117                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       129157                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            6577739                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3133333                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        70837                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        49793                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            2053111                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             984012                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       392546                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker       149888                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst            5786914                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data            2465786                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               21994233                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7869277                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7869277                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       350049                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       108782                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu2.data       265889                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       724720                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data            4870                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1538                       # number of UpgradeReq hits
+system.l2c.tags.occ_blocks::writebacks   37285.924880                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   168.149057                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   240.751709                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3675.446789                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     8312.608354                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    50.722331                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    75.631311                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1066.604817                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3135.281683                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker   117.351685                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker   183.998379                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2140.151911                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     8871.642837                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.568938                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002566                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003674                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.056083                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.126840                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000774                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.001154                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.016275                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.047841                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001791                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.002808                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.032656                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.135371                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996769                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          311                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62411                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          310                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          160                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2760                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_percent::1023     0.004745                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.952316                       # Percentage of cache occupancy per task id
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-system.l2c.ReadReq_accesses::total           22373062                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      7869277                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          7869277                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       755062                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       138919                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu2.data       337429                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total      1231410                       # number of WriteInvalidateReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data         7163                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data        16107                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           45609                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_latency::cpu1.data   5737082423                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total  21802258043                       # number of ReadExReq miss cycles
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+system.l2c.demand_miss_latency::cpu1.itb.walker     37951500                       # number of demand (read+write) miss cycles
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+system.l2c.Writeback_accesses::writebacks      7876656                       # number of Writeback accesses(hits+misses)
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+system.l2c.WriteInvalidateReq_accesses::cpu1.data       141795                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data         7073                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data        16243                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           45591                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu2.data            4                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1063020                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       324174                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       720412                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2107606                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       203102                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       131106                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.dtb.walker       394019                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.dtb.walker       203102                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total           24480668                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009773                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.014866                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.006698                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.041398                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008094                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu1.data      0.036826                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003738                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.009535                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.005710                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.042407                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016932                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.536397                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.216939                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu2.data     0.212015                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.411471                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781996                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.785285                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.784317                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.783332                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data      1060258                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.010093                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.data      0.036848                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.inst      0.005797                       # miss rate for ReadReq accesses
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+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.537673                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.214838                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu2.data     0.215089                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.411847                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782536                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783402                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.786123                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.783949                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.250000                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total     0.571429                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.241984                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.239097                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.233358                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.238592                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009773                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.014866                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006698                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.090623                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008094                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.009528                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005424                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.085549                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003738                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.009535                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.005710                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.084151                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.036016                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009773                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.014866                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006698                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.090623                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008094                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.009528                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005424                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.085549                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003738                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.009535                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005710                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.084151                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.036016                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78041.955017                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78783.924843                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73976.779495                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 75894.153842                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 78834.688391                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 83610.358974                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78597.774735                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 86759.793678                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 42471.035597                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data     2.339218                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu2.data    11.964817                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total     1.828455                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11361.022578                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11846.201615                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5977.518879                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.241473                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.234895                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.235279                       # miss rate for ReadExReq accesses
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+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.010093                       # miss rate for demand accesses
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+system.l2c.WriteInvalidateReq_avg_miss_latency::total     1.509943                       # average WriteInvalidateReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11888.790900                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6038.673204                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        72250                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        36125                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74312.678786                       # average ReadExReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2110,185 +2376,185 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1097767                       # number of writebacks
-system.l2c.writebacks::total                  1097767                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu2.data             4                       # number of ReadReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 37                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::total    183164309                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       120500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total       130501                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14083669373                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  18850280453                       # number of ReadExReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     31757500                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::total  32500766397                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     37895750                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total  32500766397                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    816699000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1310911000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2127610000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    743754000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1345310999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2089064999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1560453000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2656221999                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4216674999                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::total     0.008724                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.216939                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data     0.212015                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.082570                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.785285                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.784317                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.400316                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    815320500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1356119999                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.UpgradeReq_mshr_miss_rate::total     0.401614                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.239097                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::total     0.116541                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.084150                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.018006                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008094                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005424                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003710                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.009390                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005710                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.084150                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.018006                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61294.498526                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63316.887276                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66080.983690                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74343.104475                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 69935.784042                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20452.168530                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 27030.577817                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25080.741367                       # average WriteInvalidateReq mshr miss latency
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 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10007.846988                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.737540                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10004.602396                       # average UpgradeReq mshr miss latency
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 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        60250                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333                       # average SCUpgradeReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80060.763927                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 73729.815854                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61294.498526                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62092.053730                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66080.983690                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80060.763927                       # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60948.982810                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62052.824983                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66302.482521                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 79214.264043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 73157.282017                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60948.982810                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62052.824983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66302.482521                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 79214.264043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 73157.282017                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -2299,57 +2565,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              464434                       # Transaction distribution
-system.membus.trans_dist::ReadResp             464434                       # Transaction distribution
+system.membus.trans_dist::ReadReq              464425                       # Transaction distribution
+system.membus.trans_dist::ReadResp             464425                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33772                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33772                       # Transaction distribution
-system.membus.trans_dist::Writeback           1204397                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       613284                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       613284                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36382                       # Transaction distribution
+system.membus.trans_dist::Writeback           1204773                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       613884                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       613884                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36393                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36386                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            502275                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           502275                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36397                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            501696                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           501696                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122952                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4037051                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4166813                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337307                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       337307                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4504120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4037435                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4167195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       337326                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       337326                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4504521                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156082                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159247392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    159417170                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14194688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14194688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               173611858                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              579                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2743991                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159270496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    159440210                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14195136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14195136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               173635346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              600                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2744389                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2743991    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2744389    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2743991                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42257500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2744389                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            42480999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1290500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1323000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6097591000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6141947499                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4309666748                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4337026701                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           38158381                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           38901629                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2393,55 +2657,55 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           22879889                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          22879700                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq           22911195                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          22910936                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33772                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33772                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7869277                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1265786                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1231410                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45609                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          7876656                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1266229                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1231725                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           45591                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45616                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2107606                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2107606                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29099470                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28504181                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       848529                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1761011                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              60213191                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    928591700                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1156912126                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3110208                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6320128                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2094934162                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          368424                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         34177702                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003380                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.058037                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp          45598                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2107463                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2107463                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29129582                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28533410                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       850957                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1760816                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              60274765                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    929555284                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1158084670                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3113192                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6291728                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2097044874                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          377016                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         34216462                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003376                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.058008                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               34062190     99.66%     99.66% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115512      0.34%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               34100938     99.66%     99.66% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115524      0.34%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           34177702                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        26362663917                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           34216462                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        26470973727                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           981000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           972000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       35502866905                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       35634626823                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       21222039348                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       21264279204                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         273701566                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         276240027                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         651522269                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         654460701                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index cd3f04231..726dee18b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,157 +1,157 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.358466                       # Number of seconds simulated
-sim_ticks                                51358465585500                       # Number of ticks simulated
-final_tick                               51358465585500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.358448                       # Number of seconds simulated
+sim_ticks                                51358448410500                       # Number of ticks simulated
+final_tick                               51358448410500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 124397                       # Simulator instruction rate (inst/s)
-host_op_rate                                   146176                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7088870517                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677952                       # Number of bytes of host memory used
-host_seconds                                  7244.94                       # Real time elapsed on the host
-sim_insts                                   901249371                       # Number of instructions simulated
-sim_ops                                    1059038863                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 129809                       # Simulator instruction rate (inst/s)
+host_op_rate                                   152542                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7366025588                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 732256                       # Number of bytes of host memory used
+host_seconds                                  6972.34                       # Real time elapsed on the host
+sim_insts                                   905073903                       # Number of instructions simulated
+sim_ops                                    1063573170                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       144192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       134400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3960256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         28248856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       172736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       160128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3375488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         26920496                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        423040                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             63539592                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3960256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3375488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7335744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     82068736                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       167040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       151040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3952000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         28582936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       161216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       144320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3546944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         27869040                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        401920                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             64976456                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3952000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3546944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7498944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     83152960                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          82089316                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2253                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2100                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             61879                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            441396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2502                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             52742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            420638                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6610                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                992819                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1282324                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          83173540                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2360                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             61750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            446616                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2519                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2255                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             55421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            435459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6280                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1015270                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1299265                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1284897                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2808                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2617                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               77110                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              550033                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               65724                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              524169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8237                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1237179                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          77110                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          65724                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             142834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1597959                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1301838                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2941                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               76949                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              556538                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               69063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              542638                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1265156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          76949                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          69063                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             146012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1619071                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1598360                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1597959                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2808                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2617                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              77110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             550434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              65724                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             524169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2835539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        992819                       # Number of read requests accepted
-system.physmem.writeReqs                      1909642                       # Number of write requests accepted
-system.physmem.readBursts                      992819                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1909642                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 63506944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 121761344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  63539592                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              122072996                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    7111                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          37069                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               60948                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               60211                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               58469                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               57182                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               59427                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               69894                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               60719                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               60135                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57063                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               84498                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              60252                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              64911                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              58664                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              62105                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              58293                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              59525                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              119395                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              117730                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              117506                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              117615                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              116969                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              124824                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              116994                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              119672                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              117205                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              123532                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             118074                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             121555                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             115761                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             122535                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             116498                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             116656                       # Per bank write bursts
+system.physmem.bw_write::total                1619471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1619071                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2941                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              76949                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             556939                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              69063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             542638                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2884628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1015270                       # Number of read requests accepted
+system.physmem.writeReqs                      1929008                       # Number of write requests accepted
+system.physmem.readBursts                     1015270                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1929008                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 64941248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     36032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 123000896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  64976456                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              123312420                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      563                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    7116                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          37405                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               61592                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               63105                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               59504                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               58627                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               63182                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               72471                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               63664                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               61386                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               55404                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               84358                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              61903                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              68457                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              58658                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              64087                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              58698                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              59611                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              118843                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              118980                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              119959                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              120276                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              119980                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              124689                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              121042                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              120315                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              116178                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              121715                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             120153                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             124890                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             118317                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             123673                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             117041                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             115838                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          94                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51358464467000                       # Total gap between requests
+system.physmem.numWrRetry                          47                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51358447292000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  992804                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1015255                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1907069                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    594810                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    261742                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     92458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     39543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1048                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       420                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       158                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1926435                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    609091                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    267826                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     93793                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     40314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1010                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       457                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       411                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       328                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       239                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       161                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      115                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                       99                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       71                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       52                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -162,207 +162,211 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    38063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    69896                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    79199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    93003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                   104514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   119076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   117779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   128388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   124328                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   136701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   126686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   112871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   105936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   106364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    92202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    90503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    89684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    85602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     4975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     4275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     4024                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     3728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     3450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     3239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     3237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     3041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     2905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     2816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     2728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     2633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     2541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     2466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     2243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     2077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     1161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      225                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       619163                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      299.223151                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     170.216009                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.259099                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         254617     41.12%     41.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       146485     23.66%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55354      8.94%     73.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        28104      4.54%     78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        20475      3.31%     81.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12983      2.10%     83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10576      1.71%     85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9506      1.54%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        81063     13.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         619163                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         77925                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        12.733693                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       58.402560                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           77917     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                       816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       754                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       749                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::11                      745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      748                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15                    38881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    70996                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19                   107299                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                      113                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       633988                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.443718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     168.837628                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.480307                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         262069     41.34%     41.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       150940     23.81%     65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        56528      8.92%     74.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28800      4.54%     78.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        20482      3.23%     81.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        13112      2.07%     83.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10788      1.70%     85.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9843      1.55%     87.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        81426     12.84%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         633988                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         79397                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        12.779954                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       57.830581                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           79390     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           77925                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         77925                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.414771                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       21.404795                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       17.389828                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                83      0.11%      0.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                12      0.02%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               10      0.01%      0.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              84      0.11%      0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           52239     67.04%     67.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2830      3.63%     70.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             709      0.91%     71.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            6561      8.42%     80.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35            7338      9.42%     89.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39            1031      1.32%     90.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43            1085      1.39%     92.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47            1174      1.51%     93.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             800      1.03%     94.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             285      0.37%     95.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59             381      0.49%     95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63             214      0.27%     96.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             366      0.47%     96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71             298      0.38%     96.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75             251      0.32%     97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             217      0.28%     97.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             385      0.49%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87             175      0.22%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91             111      0.14%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95             109      0.14%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             293      0.38%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            79      0.10%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            56      0.07%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            98      0.13%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115           168      0.22%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119            47      0.06%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            31      0.04%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127            43      0.06%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131           108      0.14%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            28      0.04%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139            23      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143            23      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            29      0.04%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151            14      0.02%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155            15      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159            12      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163            14      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167            22      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171            10      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             7      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179            16      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             7      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           79397                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         79397                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.206066                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       21.327441                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       16.891492                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                78      0.10%      0.10% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::8-11                8      0.01%      0.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              74      0.09%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           53395     67.25%     67.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2838      3.57%     71.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             719      0.91%     71.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            6583      8.29%     80.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            7477      9.42%     89.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39            1320      1.66%     91.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43            1452      1.83%     93.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             838      1.06%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             841      1.06%     95.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             314      0.40%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59             349      0.44%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63             180      0.23%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             342      0.43%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71             280      0.35%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75             234      0.29%     97.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             238      0.30%     97.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             362      0.46%     98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87             134      0.17%     98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              99      0.12%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              90      0.11%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             295      0.37%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            94      0.12%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            72      0.09%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111           132      0.17%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115           106      0.13%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            42      0.05%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            41      0.05%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            32      0.04%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131           104      0.13%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            22      0.03%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139            10      0.01%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143            15      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            22      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            21      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155            15      0.02%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159            11      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            20      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167            17      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             9      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             4      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             9      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             7      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             5      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             3      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::200-203             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             6      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             3      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::224-227             1      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::228-231             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::236-239             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::244-247             1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::248-251             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           77925                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    27174725250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               45780275250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4961480000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27385.70                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::252-255             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           79397                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    27026112263                       # Total ticks spent queuing
+system.physmem.totMemAccLat               46051868513                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5073535000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26634.40                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46135.70                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.24                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.37                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.24                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.38                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45384.40                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.39                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.40                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     765740                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1509913                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.36                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17694799.16                       # Average gap between requests
-system.physmem.pageHitRate                      78.61                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49399135941008                       # Time in different power states
-system.physmem.memoryStateTime::REF      1714971960000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      244357347492                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2363029200                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                2317843080                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1289351250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1264696125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               3798436200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               3941425800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              6160568400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              6167767680                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3354485153760                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3354485153760                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1233743623290                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1233089726130                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29732846799750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29733420393750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34334686961850                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34334687006325                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.530261                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.530262                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        10.31                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     781715                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1520891                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.14                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17443477.58                       # Average gap between requests
+system.physmem.pageHitRate                      78.41                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2437517880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1329994875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3927541800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               6247264320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3354484136640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1237564295100                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29729485998000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34335476748615                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.545842                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49457442122001                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1714971440000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    186034306749                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 2355431400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1285205625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3987126000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               6206576400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3354484136640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1235795450580                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29731037607750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34335151534395                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.539510                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49460023829001                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1714971440000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    183452804499                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst         1408                       # Number of bytes read from this memory
@@ -391,16 +395,24 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              131952150                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         89649773                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5822015                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            90992883                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               64634149                       # Number of BTB hits
+system.cpu0.branchPred.lookups              134182977                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         91246699                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5930019                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            92418572                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               65829087                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.032093                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17244860                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            187476                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.229284                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17386110                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            187768                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -422,27 +434,105 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   898809                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               898809                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17395                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94113                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       544060                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       354749                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2049.828188                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 11956.771667                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-32767       349905     98.63%     98.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-65535         2560      0.72%     99.36% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-98303         1330      0.37%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-131071          450      0.13%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-163839          167      0.05%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::163840-196607          126      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-229375           45      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::229376-262143           59      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-294911           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::294912-327679           16      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-360447           24      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::360448-393215           21      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-425983            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       354749                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       411281                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 21163.528109                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 16798.259479                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15588.127658                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767       367100     89.26%     89.26% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535        39499      9.60%     98.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303         2985      0.73%     99.59% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          830      0.20%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839          180      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607          394      0.10%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375          143      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           73      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679           14      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447           12      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215           17      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       411281                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 359646036796                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.131612                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.643594                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 358749976796     99.75%     99.75% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    501279000      0.14%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    178636500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    105104000      0.03%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     41922000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     20797500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     20431000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     22734000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      4793500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       308500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        38000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47         8500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51         4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::52-55         3500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 359646036796                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        94113     84.40%     84.40% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17395     15.60%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       111508                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       898809                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       898809                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       111508                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       111508                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total      1010317                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   105327476                       # DTB read hits
-system.cpu0.dtb.read_misses                    614604                       # DTB read misses
-system.cpu0.dtb.write_hits                   81433492                       # DTB write hits
-system.cpu0.dtb.write_misses                   261715                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1084                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   106848795                       # DTB read hits
+system.cpu0.dtb.read_misses                    623268                       # DTB read misses
+system.cpu0.dtb.write_hits                   83024984                       # DTB write hits
+system.cpu0.dtb.write_misses                   275541                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1088                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21241                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   54785                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      190                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  8902                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   56194                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      160                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9669                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    53829                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               105942080                       # DTB read accesses
-system.cpu0.dtb.write_accesses               81695207                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56033                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               107472063                       # DTB read accesses
+system.cpu0.dtb.write_accesses               83300525                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        186760968                       # DTB hits
-system.cpu0.dtb.misses                         876319                       # DTB misses
-system.cpu0.dtb.accesses                    187637287                       # DTB accesses
+system.cpu0.dtb.hits                        189873779                       # DTB hits
+system.cpu0.dtb.misses                         898809                       # DTB misses
+system.cpu0.dtb.accesses                    190772588                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -464,619 +554,673 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    94794688                       # ITB inst hits
-system.cpu0.itb.inst_misses                    101824                       # ITB inst misses
+system.cpu0.itb.walker.walks                   108604                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               108604                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3026                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        75552                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14309                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        94295                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1394.214964                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8384.902945                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        93563     99.22%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          326      0.35%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          303      0.32%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           55      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        94295                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        92887                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25650.201395                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 21071.590317                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 17522.957706                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        91125     98.10%     98.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1488      1.60%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          173      0.19%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           55      0.06%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           22      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        92887                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 604413242668                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.909243                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.287630                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    54912274056      9.09%      9.09% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   549448743612     90.91%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       47582500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        4106500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         406500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5         121000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6           8500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 604413242668                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        75552     96.15%     96.15% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         3026      3.85%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        78578                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       108604                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       108604                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        78578                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        78578                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       187182                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    96451691                       # ITB inst hits
+system.cpu0.itb.inst_misses                    108604                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1084                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1088                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21241                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    529                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41122                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   42484                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   203923                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   204587                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                94896512                       # ITB inst accesses
-system.cpu0.itb.hits                         94794688                       # DTB hits
-system.cpu0.itb.misses                         101824                       # DTB misses
-system.cpu0.itb.accesses                     94896512                       # DTB accesses
-system.cpu0.numCycles                       673746678                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                96560295                       # ITB inst accesses
+system.cpu0.itb.hits                         96451691                       # DTB hits
+system.cpu0.itb.misses                         108604                       # DTB misses
+system.cpu0.itb.accesses                     96560295                       # DTB accesses
+system.cpu0.numCycles                       678169162                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         246770894                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     586838334                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  131952150                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          81879009                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    386930341                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13253583                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2358226                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               20576                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             5110                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5338145                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       169787                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         2046                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 94573624                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3603023                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  38939                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         648221646                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.060144                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.307830                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         248888472                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     597668364                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  134182977                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          83215197                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    388705337                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13495131                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2539677                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               21156                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             4430                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5365960                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       171714                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         1942                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 96228071                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3656691                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  42208                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         652445982                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.071952                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.318616                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               503028040     77.60%     77.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18376002      2.83%     80.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18277372      2.82%     83.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13314289      2.05%     85.31% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28669690      4.42%     89.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 8974243      1.38%     91.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9730545      1.50%     92.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8410547      1.30%     93.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39440918      6.08%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               504779765     77.37%     77.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                18600914      2.85%     80.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18675892      2.86%     83.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13601130      2.08%     85.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28939785      4.44%     89.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 9186194      1.41%     91.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9881419      1.51%     92.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8590984      1.32%     93.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                40189899      6.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           648221646                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.195848                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.871007                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               200186064                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            323821330                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105067312                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13887509                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5257280                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19546951                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1388336                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             640651678                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4275147                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5257280                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               207892852                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               28836524                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     254594010                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                111072647                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             40565977                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             625329125                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                73391                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2369804                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1783636                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              20590537                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            4721                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          598881072                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            965488055                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       739733763                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           970310                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            502829107                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96051965                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15333341                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13384841                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 78497988                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           100792231                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85691546                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13482087                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14436592                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 593155856                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15408534                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                593869164                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           811141                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       75391106                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     52735595                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        350692                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    648221646                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.916151                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.637744                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           652445982                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.197861                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.881297                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               202230502                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            323725330                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                107157055                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13964232                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5366791                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19957602                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1400195                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             652122035                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4310941                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5366791                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               210017200                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               28890111                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     254295095                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                113145299                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             40729265                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             636448025                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                83808                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2425012                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1797238                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              20704845                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            5054                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          608929978                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            980367872                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       752692960                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           918645                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            510273791                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                98656187                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15296129                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13303285                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 78526904                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           102548023                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           87419598                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13782768                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14655222                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 603808817                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15342366                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                603678166                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           829707                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       77491896                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     54214041                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        352970                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    652445982                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.925254                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.646571                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          413675393     63.82%     63.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           99838135     15.40%     79.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43354420      6.69%     85.91% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           30999055      4.78%     90.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           23185151      3.58%     94.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           15937923      2.46%     96.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10813303      1.67%     98.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6331141      0.98%     99.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4087125      0.63%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          415092251     63.62%     63.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          100237257     15.36%     78.98% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           44034564      6.75%     85.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           31483239      4.83%     90.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           23657330      3.63%     94.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           16258445      2.49%     96.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10998020      1.69%     98.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6466609      0.99%     99.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4218267      0.65%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      648221646                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      652445982                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2980479     25.39%     25.39% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 23946      0.20%     25.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2481      0.02%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               3      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4885958     41.63%     67.25% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3844513     32.75%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                3031745     25.47%     25.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 22352      0.19%     25.65% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2380      0.02%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               2      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4899657     41.16%     66.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3948703     33.17%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            402330448     67.75%     67.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1450246      0.24%     67.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                67448      0.01%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         71724      0.01%     68.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            408914830     67.74%     67.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1483700      0.25%     67.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                67594      0.01%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                189      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd             10      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             26      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.99% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         67735      0.01%     68.01% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.01% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.01% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           107439270     18.09%     86.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82509979     13.89%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           109003987     18.06%     86.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           84140078     13.94%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             593869164                       # Type of FU issued
-system.cpu0.iq.rate                          0.881443                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11737380                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019764                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1847356027                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        684092325                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    571253396                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1152468                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            551459                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       500772                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             604990335                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 616209                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4719298                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             603678166                       # Type of FU issued
+system.cpu0.iq.rate                          0.890159                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11904839                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019721                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1871435984                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        696824280                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    580857585                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1100876                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            525941                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       475487                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             614994656                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 588349                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4797344                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16584124                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        22051                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       699484                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8981937                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16957941                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        22519                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       718505                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      9238289                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3863484                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      8859794                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3918093                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8730401                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5257280                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15355080                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles             11717568                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          608700724                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1772426                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            100792231                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85691546                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13094550                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                251810                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents             11354978                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        699484                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2666409                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2277536                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4943945                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            587171511                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            105317678                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5833659                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5366791                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15638409                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles             11458161                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          619287399                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1818065                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            102548023                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            87419598                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13010956                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                256814                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents             11089494                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        718505                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2724850                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2330540                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5055390                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            596785117                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            106839289                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          6007087                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       136334                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   186754203                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               108711734                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81436525                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.871502                       # Inst execution rate
-system.cpu0.iew.wb_sent                     572939308                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    571754168                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                281506422                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                489082927                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       136216                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   189866682                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               110402162                       # Number of branches executed
+system.cpu0.iew.exec_stores                  83027393                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.879994                       # Inst execution rate
+system.cpu0.iew.wb_sent                     582539449                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    581333072                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                286508471                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                497555384                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.848619                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575580                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.857210                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575832                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       81075036                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15057842                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4452233                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    634439872                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.831521                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.823079                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       83249738                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14989396                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4548973                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    638320811                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.839633                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.833868                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    439457438     69.27%     69.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     96886239     15.27%     84.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33460731      5.27%     89.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15060049      2.37%     92.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10644464      1.68%     93.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6550765      1.03%     94.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5894426      0.93%     95.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      4022234      0.63%     96.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22463526      3.54%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    441333872     69.14%     69.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     97259629     15.24%     84.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     33853962      5.30%     89.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15327337      2.40%     92.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10781377      1.69%     93.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6688169      1.05%     94.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6042869      0.95%     95.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      4086388      0.64%     96.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22947208      3.59%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    634439872                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           448815056                       # Number of instructions committed
-system.cpu0.commit.committedOps             527549931                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    638320811                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           456208771                       # Number of instructions committed
+system.cpu0.commit.committedOps             535955511                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     160917716                       # Number of memory references committed
-system.cpu0.commit.loads                     84208107                       # Number of loads committed
-system.cpu0.commit.membars                    3677805                       # Number of memory barriers committed
-system.cpu0.commit.branches                 100249360                       # Number of branches committed
-system.cpu0.commit.fp_insts                    481111                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                484287281                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13244362                       # Number of function calls committed.
+system.cpu0.commit.refs                     163771391                       # Number of memory references committed
+system.cpu0.commit.loads                     85590082                       # Number of loads committed
+system.cpu0.commit.membars                    3686850                       # Number of memory barriers committed
+system.cpu0.commit.branches                 101715990                       # Number of branches committed
+system.cpu0.commit.fp_insts                    455933                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                492018334                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13342246                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       365417797     69.27%     69.27% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1102287      0.21%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           49909      0.01%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        62180      0.01%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84208107     15.96%     85.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      76709609     14.54%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       370951931     69.21%     69.21% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1123996      0.21%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           50135      0.01%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        58016      0.01%     69.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       85590082     15.97%     85.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      78181309     14.59%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        527549931                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22463526                       # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total        535955511                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22947208                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                  1216684794                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1231052317                       # The number of ROB writes
-system.cpu0.timesIdled                        4081993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       25525032                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 47131326354                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  448815056                       # Number of Instructions Simulated
-system.cpu0.committedOps                    527549931                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.501168                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.501168                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.666148                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.666148                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               692564361                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              407943900                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   896391                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  528896                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                125905812                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               126977702                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             2322757937                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15198906                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10638925                       # number of replacements
+system.cpu0.rob.rob_reads                  1230638929                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1252557383                       # The number of ROB writes
+system.cpu0.timesIdled                        4102528                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       25723180                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 48923483834                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  456208771                       # Number of Instructions Simulated
+system.cpu0.committedOps                    535955511                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.486532                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.486532                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.672706                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.672706                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               703703491                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              414789220                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   851205                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  517790                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                127713204                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               128825628                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             2353610328                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15112961                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10694855                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.983549                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          304517896                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10639437                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.621617                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs          305873629                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10695367                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.598703                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1654841000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   289.769940                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   222.213609                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.565957                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.434011                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   310.817389                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   201.166160                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.607065                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.392903                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1345465491                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1345465491                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     79979109                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     80848758                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      160827867                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67346505                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     67891780                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135238285                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204132                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       199440                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       403572                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       171160                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       153591                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       324751                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1784441                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1798021                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3582462                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2031437                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2062591                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4094028                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147325614                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    148740538                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       296066152                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147529746                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    148939978                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      296469724                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6500737                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6533272                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     13034009                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6519313                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6481267                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     13000580                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       668156                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       654202                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1322358                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       633593                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       607646                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1241239                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       311874                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       325474                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       637348                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           10                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13020050                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     13014539                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      26034589                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13688206                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13668741                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     27356947                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111607932917                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111225009746                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 222832942663                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 259750103307                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 246979475075                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 506729578382                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  25310357673                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  23982059689                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  49292417362                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4526632473                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4625804945                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   9152437418                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       268001                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       294001                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 371358036224                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 358204484821                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 729562521045                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 371358036224                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 358204484821                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 729562521045                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     86479846                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     87382030                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    173861876                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73865818                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74373047                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    148238865                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       872288                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       853642                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1725930                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       804753                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       761237                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1565990                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2096315                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2123495                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4219810                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2031439                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2062601                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4094040                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    160345664                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    161755077                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    322100741                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    161217952                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    162608719                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    323826671                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075171                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074767                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.074968                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088259                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087145                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087700                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.765981                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.766366                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766171                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.787314                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.798235                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.792623                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.148772                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.153273                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.151037                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081200                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.080458                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.080827                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.084905                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.084059                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.084480                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17168.504574                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17024.396006                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17096.270431                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39843.171099                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.665730                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38977.459343                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39947.344230                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39467.156353                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39712.269242                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14514.298957                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14212.517574                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14360.188497                       # average LoadLockedReq miss latency
+system.cpu0.dcache.tags.tag_accesses       1351414929                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1351414929                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     81475453                       # number of ReadReq hits
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074126                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.075676                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.074895                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.086198                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.089359                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.087760                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.767067                       # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766793                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.786244                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.798028                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.791998                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.152208                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.149500                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.150836                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079694                       # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.083310                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.085649                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.084468                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17204.957373                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17150.855600                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17177.845377                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39744.999328                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38310.744619                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39023.360359                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40129.339617                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39355.041701                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39748.361854                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.591141                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14306.130662                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14372.106828                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26800.100000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24500.083333                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28522.013066                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27523.409382                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 28022.816917                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27129.781377                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26206.106680                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 26668.272635                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     59155859                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        42706                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3724749                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            967                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.881838                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    44.163392                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        24750                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23071.428571                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28450.326623                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27750.318970                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 28098.826597                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27072.312839                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26412.896053                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 26741.236737                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     59451650                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        40861                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3737259                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            929                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.907822                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    43.983854                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8137324                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8137324                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3661999                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3663033                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      7325032                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5427863                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5389700                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10817563                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         3334                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3491                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         6825                       # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       189406                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       198198                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       387604                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9089862                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      9052733                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     18142595                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9089862                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      9052733                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     18142595                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2838738                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2870239                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5708977                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1091450                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1091567                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2183017                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       661474                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       648177                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1309651                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       630259                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       604155                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1234414                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122468                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127276                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       249744                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           10                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3930188                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3961806                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7891994                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4591662                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4609983                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9201645                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43024166867                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  43656462738                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  86680629605                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  40600883832                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38849310828                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  79450194660                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13171462044                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12577725489                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25749187533                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  23923452719                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  22638090123                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  46561542842                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1614671914                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1630090692                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3244762606                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        22000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       247999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       269999                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83625050699                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82505773566                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 166130824265                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  96796512743                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  95083499055                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 191880011798                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2877179750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2839380752                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5716560502                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2798393044                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2781680461                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5580073505                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5675572794                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5621061213                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11296634007                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032825                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032847                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032836                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014776                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014677                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014726                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758321                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759308                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758809                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.783171                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.793649                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.788264                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058421                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059937                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059184                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024511                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024493                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024502                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028481                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028350                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028415                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15156.089384                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15210.044438                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15183.215768                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37199.032326                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35590.404279                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36394.675195                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19912.289892                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19404.769822                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19661.106305                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37958.129466                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37470.665844                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37719.551821                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13184.439315                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12807.526101                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12992.354595                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      8181117                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8181117                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3664959                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3663666                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      7328625                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5405222                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5470276                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10875498                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data         3366                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data         3580                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total         6946                       # number of WriteInvalidateReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       193804                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       194772                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       388576                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9070181                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      9133942                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     18204123                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9070181                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      9133942                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     18204123                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2858002                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2888833                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5746835                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1089265                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1106445                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2195710                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       655865                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       659095                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1314960                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       626876                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       606885                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1233761                       # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       124685                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       126170                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       250855                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3947267                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3995278                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7942545                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4603132                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4654373                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9257505                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43426889493                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44103833792                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  87530723285                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  40333598117                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  39629888189                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  79963486306                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12970544028                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12958416533                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25928960561                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  23908668069                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  22678349912                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  46587017981                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1638689162                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1618682187                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3257371349                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        11000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       136500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       147500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83760487610                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83733721981                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 167494209591                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  96731031638                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  96692138514                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 193423170152                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2840564251                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2875998253                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5716562504                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2826497047                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2753568465                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5580065512                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5667061298                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5629566718                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11296628016                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032478                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033364                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032917                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014457                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015033                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014742                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759266                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759942                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.759604                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.782045                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.793348                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.787564                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059588                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058772                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059175                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024166                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024942                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024550                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028033                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028900                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028462                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15194.842233                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15267.007055                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15231.118222                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37028.269629                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35817.314181                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36418.054436                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19776.240580                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19660.923741                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19718.440531                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38139.389718                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37368.446925                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37760.164230                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.632730                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12829.374550                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12985.076435                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24799.900000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22499.916667                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21277.620994                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20825.293708                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21050.551263                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21080.931642                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20625.563924                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20852.794451                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        22750                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21071.428571                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21219.868737                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20958.171617                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21088.229225                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21014.177225                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20774.471344                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20893.660889                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1087,137 +1231,137 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16118591                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.955303                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          173100510                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16119103                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.738843                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      13625340000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   274.422577                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   237.532726                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.535982                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.463931                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999913                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         16173930                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.955160                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          173933615                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16174442                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.753608                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13621642000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   273.473305                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   238.481855                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.534128                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.465785                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999912                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           65                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        206488523                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       206488523                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     85967347                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     87133163                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      173100510                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     85967347                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     87133163                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       173100510                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     85967347                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     87133163                       # number of overall hits
-system.cpu0.icache.overall_hits::total      173100510                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8593751                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8674986                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17268737                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8593751                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8674986                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17268737                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8593751                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8674986                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17268737                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 114914016470                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 115519885429                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 230433901899                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 114914016470                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 115519885429                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 230433901899                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 114914016470                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 115519885429                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 230433901899                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     94561098                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     95808149                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    190369247                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     94561098                       # number of demand (read+write) accesses
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-system.cpu0.icache.demand_accesses::total    190369247                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     94561098                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     95808149                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    190369247                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.090880                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.090545                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.090712                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.090880                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.090545                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.090712                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.090880                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.090545                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.090712                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13371.811270                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13316.434796                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13343.992783                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13371.811270                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13316.434796                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13343.992783                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13371.811270                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13316.434796                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13343.992783                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        69035                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        207440760                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       207440760                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     87577793                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     86355822                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      173933615                       # number of ReadReq hits
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+system.cpu0.icache.overall_hits::total      173933615                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8637755                       # number of ReadReq misses
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+system.cpu0.icache.demand_misses::cpu0.inst      8637755                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu0.inst      8637755                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      8694581                       # number of overall misses
+system.cpu0.icache.overall_misses::total     17332336                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115405674014                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116006330283                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 231412004297                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 115405674014                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 116006330283                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 231412004297                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 115405674014                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 116006330283                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 231412004297                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     96215548                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     95050403                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    191265951                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.overall_accesses::total    191265951                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.089775                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091473                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.090619                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.089775                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091473                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.090619                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.089775                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091473                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.090619                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13360.609790                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13342.371563                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13351.460778                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13360.609790                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13342.371563                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13351.460778                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13360.609790                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13342.371563                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13351.460778                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        66509                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             6155                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             6230                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.216084                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    10.675602                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       567050                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       582411                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1149461                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       567050                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       582411                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1149461                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       567050                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       582411                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1149461                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8026701                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8092575                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16119276                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8026701                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8092575                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16119276                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8026701                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8092575                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16119276                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  93925882851                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  94357511095                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 188283393946                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  93925882851                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  94357511095                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 188283393946                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  93925882851                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  94357511095                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 188283393946                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       574540                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       582987                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total      1157527                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       574540                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst       582987                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total      1157527                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       574540                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst       582987                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total      1157527                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8063215                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8111594                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     16174809                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8063215                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      8111594                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     16174809                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8063215                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      8111594                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     16174809                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  94312224420                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  94761792489                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 189074016909                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  94312224420                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  94761792489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 189074016909                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  94312224420                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  94761792489                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 189074016909                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    916338250                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    595537750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1511876000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    916338250                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    595537750                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1511876000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084674                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.084674                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084884                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084466                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.084674                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11680.635901                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11680.635901                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11701.679538                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11659.763560                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11680.635901                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.083804                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085340                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084567                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.083804                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085340                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.084567                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.083804                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085340                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.084567                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11696.602958                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.265223                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.412648                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11696.602958                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.265223                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.412648                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11696.602958                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.265223                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.412648                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1225,15 +1369,23 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              133577738                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90779695                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5949901                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            90899106                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               65330171                       # Number of BTB hits
+system.cpu1.branchPred.lookups              132595782                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89991047                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5894262                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            90157022                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               64704998                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.871082                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17378415                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            188946                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.769227                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17429206                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            189878                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1255,27 +1407,103 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   890417                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               890417                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17386                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91593                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       535956                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       354461                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2058.191169                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12119.324471                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       349672     98.65%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         2519      0.71%     99.36% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303         1342      0.38%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          424      0.12%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          149      0.04%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607          114      0.03%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375           53      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           71      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679           10      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447           34      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215           29      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-425983            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       354461                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       404532                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20689.820452                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 16434.872295                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15113.304602                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767       363916     89.96%     89.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        36589      9.04%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303         2703      0.67%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          595      0.15%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839          189      0.05%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607          278      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375          138      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           43      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           30      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679           13      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447           13      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-491519            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       404532                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 334236526020                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.086173                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.625283                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 333380386520     99.74%     99.74% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    477486500      0.14%     99.89% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    168839000      0.05%     99.94% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    100636500      0.03%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     41145500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     20471500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     20409500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     23342000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      3487500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       317500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43         4000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 334236526020                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        91594     84.05%     84.05% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17386     15.95%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       108980                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       890417                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       890417                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108980                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108980                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       999397                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   106064392                       # DTB read hits
-system.cpu1.dtb.read_misses                    610373                       # DTB read misses
-system.cpu1.dtb.write_hits                   82025488                       # DTB write hits
-system.cpu1.dtb.write_misses                   271302                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1088                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   105460349                       # DTB read hits
+system.cpu1.dtb.read_misses                    614707                       # DTB read misses
+system.cpu1.dtb.write_hits                   81263219                       # DTB write hits
+system.cpu1.dtb.write_misses                   275710                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1092                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              22250                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   55877                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      229                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8683                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              21988                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    544                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55487                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      238                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  9789                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    56886                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               106674765                       # DTB read accesses
-system.cpu1.dtb.write_accesses               82296790                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    55163                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               106075056                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81538929                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        188089880                       # DTB hits
-system.cpu1.dtb.misses                         881675                       # DTB misses
-system.cpu1.dtb.accesses                    188971555                       # DTB accesses
+system.cpu1.dtb.hits                        186723568                       # DTB hits
+system.cpu1.dtb.misses                         890417                       # DTB misses
+system.cpu1.dtb.accesses                    187613985                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1297,126 +1525,182 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    96043604                       # ITB inst hits
-system.cpu1.itb.inst_misses                    103294                       # ITB inst misses
+system.cpu1.itb.walker.walks                   101825                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               101825                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2978                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        69124                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        13788                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        88037                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1472.687620                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8948.821118                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        87265     99.12%     99.12% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          389      0.44%     99.56% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          275      0.31%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071           48      0.05%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839           27      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        88037                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        85890                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25260.851287                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 20589.361475                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17130.840101                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        84234     98.07%     98.07% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1438      1.67%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          145      0.17%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           40      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           24      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        85890                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 299874193152                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     1.837074                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0   -250957583628    -83.69%    -83.69% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   550779312780    183.67%     99.98% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       46468000      0.02%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        5344000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         484000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          65500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6          54500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::7          48000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 299874193152                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        69124     95.87%     95.87% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         2978      4.13%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        72102                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101825                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101825                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72102                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72102                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       173927                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    95285493                       # ITB inst hits
+system.cpu1.itb.inst_misses                    101825                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1088                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1092                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              22250                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   41299                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              21988                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    544                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   40874                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   205516                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   205822                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                96146898                       # ITB inst accesses
-system.cpu1.itb.hits                         96043604                       # DTB hits
-system.cpu1.itb.misses                         103294                       # DTB misses
-system.cpu1.itb.accesses                     96146898                       # DTB accesses
-system.cpu1.numCycles                       675301208                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                95387318                       # ITB inst accesses
+system.cpu1.itb.hits                         95285493                       # DTB hits
+system.cpu1.itb.misses                         101825                       # DTB misses
+system.cpu1.itb.accesses                     95387318                       # DTB accesses
+system.cpu1.numCycles                       677360427                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         248765293                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     593949498                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  133577738                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          82708586                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    386843919                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13545666                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2415137                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               21504                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             4007                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5459319                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       169387                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         1822                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 95816300                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3685759                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  39432                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         650452950                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.068285                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.315163                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         248549507                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     588684684                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  132595782                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          82134204                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    389145480                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13431349                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2335492                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               20294                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             4597                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5447640                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       169416                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         1942                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 95058557                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3668998                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  40025                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         652389771                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.056521                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.304488                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               503682671     77.44%     77.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18498717      2.84%     80.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18563467      2.85%     83.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13597541      2.09%     85.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28733288      4.42%     89.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9099977      1.40%     91.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9814186      1.51%     92.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8571904      1.32%     93.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                39891199      6.13%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               506719262     77.67%     77.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18449281      2.83%     80.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18323109      2.81%     83.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13434339      2.06%     85.37% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                28729534      4.40%     89.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 8986163      1.38%     91.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9758970      1.50%     92.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8450464      1.30%     93.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39538649      6.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           650452950                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.197805                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.879533                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               201647992                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            323236826                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                106239229                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13947017                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5379639                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19860273                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1413177                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             647237018                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4350385                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5379639                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               209424655                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               28067269                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     255930457                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                112228565                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             39419858                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             631550288                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                96632                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2287540                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1813390                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              19429955                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            4996                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          604714007                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            972949887                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       746652224                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           816553                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            506435319                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                98278683                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15335388                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13342018                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 78452935                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           101901110                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           86377507                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13921613                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14837029                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 598946566                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15418828                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                598874973                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           821829                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       77129289                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     53862821                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        352968                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    650452950                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.920705                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.641335                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           652389771                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.195754                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.869086                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               201147393                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            326816283                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                105097642                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             14007460                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5318954                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19647868                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1416154                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             641757938                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4369017                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5318954                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               208911045                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               28047403                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     258823969                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                111174433                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             40111705                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             626286274                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                89729                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2292362                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1848085                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              19940508                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            5105                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          599962292                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            966932024                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       740689310                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           881849                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            503173353                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                96788934                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15525446                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13560324                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 79127309                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101049697                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           85573282                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13915572                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14825014                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 593826390                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15642550                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                594476204                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           818225                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       76136612                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     53142905                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        356951                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    652389771                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.911229                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.632553                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          414330356     63.70%     63.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          100076970     15.39%     79.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43847279      6.74%     85.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31289942      4.81%     90.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23378361      3.59%     94.23% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16103120      2.48%     96.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10912961      1.68%     98.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6384879      0.98%     99.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4129082      0.63%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          416908971     63.90%     63.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          100667120     15.43%     79.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43571359      6.68%     86.01% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           31041594      4.76%     90.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           23116047      3.54%     94.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           15866958      2.43%     96.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10833871      1.66%     98.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6331428      0.97%     99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4052423      0.62%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      650452950                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      652389771                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3013028     25.67%     25.67% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 23161      0.20%     25.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   2816      0.02%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2996828     25.66%     25.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 24624      0.21%     25.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   2734      0.02%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.89% # attempts to use FU when none available
@@ -1439,19 +1723,19 @@ system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.89% # at
 system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               2      0.00%     25.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               3      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.89% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4848351     41.30%     67.19% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3852019     32.81%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4869636     41.69%     67.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3787065     32.42%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            405949153     67.79%     67.79% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1474390      0.25%     68.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66030      0.01%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                142      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            402964828     67.78%     67.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1445986      0.24%     68.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                66608      0.01%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                132      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
@@ -1464,7 +1748,7 @@ system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.04% # Ty
 system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
@@ -1473,156 +1757,156 @@ system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Ty
 system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.04% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         56962      0.01%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         61370      0.01%     68.05% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.05% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.05% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           108207982     18.07%     86.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           83120313     13.88%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           107585906     18.10%     86.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82351372     13.85%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             598874973                       # Type of FU issued
-system.cpu1.iq.rate                          0.886826                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11739377                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019602                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1859775645                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        691731884                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    576296193                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             988457                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            469794                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       425393                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             610086136                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 528213                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4764786                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             594476204                       # Type of FU issued
+system.cpu1.iq.rate                          0.877636                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11680890                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019649                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1852781725                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        685800777                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    571863197                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1059569                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            502092                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       457373                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             605590748                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 566345                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4749876                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16932520                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        21750                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       718636                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      9175857                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16757289                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        22108                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       708788                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      9117452                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3929336                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      8527630                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3937125                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      8714130                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5379639                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               15396107                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles             10835641                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          614503705                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1815595                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            101901110                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            86377507                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13042378                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                259470                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents             10465486                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        718636                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2720399                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2342418                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5062817                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            592014750                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            106053814                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5994040                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5318954                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               15381414                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             10835277                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          609605144                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1787029                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            101049697                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            85573282                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13260611                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                256865                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents             10466220                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        708788                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2676587                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2314011                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4990598                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            587727574                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            105451218                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5872593                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       138311                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   188080635                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               109728675                       # Number of branches executed
-system.cpu1.iew.exec_stores                  82026821                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.876668                       # Inst execution rate
-system.cpu1.iew.wb_sent                     577948748                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    576721586                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                284303568                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                493660086                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       136204                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   186716455                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               109034476                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81265237                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.867673                       # Inst execution rate
+system.cpu1.iew.wb_sent                     573536970                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    572320570                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                281697554                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                489376492                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.854021                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575910                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.844928                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575625                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       82926260                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15065860                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4556436                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    636355753                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.835207                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.827690                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       81905872                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15285599                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4497270                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    638458448                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.826393                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.816586                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    440359254     69.20%     69.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     97084176     15.26%     84.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33726039      5.30%     89.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15156809      2.38%     92.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10762314      1.69%     93.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6601636      1.04%     94.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5939289      0.93%     95.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      4020807      0.63%     96.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22705429      3.57%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    442788562     69.35%     69.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     97620349     15.29%     84.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     33589881      5.26%     89.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     14950626      2.34%     92.25% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10704317      1.68%     93.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6546690      1.03%     94.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5838446      0.91%     95.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3972340      0.62%     96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22447237      3.52%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    636355753                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           452434315                       # Number of instructions committed
-system.cpu1.commit.committedOps             531488932                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    638458448                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           448865132                       # Number of instructions committed
+system.cpu1.commit.committedOps             527617659                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     162170239                       # Number of memory references committed
-system.cpu1.commit.loads                     84968589                       # Number of loads committed
-system.cpu1.commit.membars                    3740598                       # Number of memory barriers committed
-system.cpu1.commit.branches                 101032588                       # Number of branches committed
-system.cpu1.commit.fp_insts                    407528                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                487762142                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13294479                       # Number of function calls committed.
+system.cpu1.commit.refs                     160748237                       # Number of memory references committed
+system.cpu1.commit.loads                     84292407                       # Number of loads committed
+system.cpu1.commit.membars                    3769330                       # Number of memory barriers committed
+system.cpu1.commit.branches                 100442689                       # Number of branches committed
+system.cpu1.commit.fp_insts                    439800                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                484228202                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13335340                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       368091914     69.26%     69.26% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1129647      0.21%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           49240      0.01%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        47892      0.01%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       84968589     15.99%     85.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77201650     14.53%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       365655543     69.30%     69.30% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1112211      0.21%     69.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           49677      0.01%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        51991      0.01%     69.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84292407     15.98%     85.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      76455830     14.49%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        531488932                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22705429                       # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total        527617659                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22447237                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                  1224024924                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1242947045                       # The number of ROB writes
-system.cpu1.timesIdled                        4091922                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       24848258                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 54236174505                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  452434315                       # Number of Instructions Simulated
-system.cpu1.committedOps                    531488932                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.492595                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.492595                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.669974                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.669974                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               697864723                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              411651158                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   767907                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  473740                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                126991866                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               128085324                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             2338745159                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15183498                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40379                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40379                       # Transaction distribution
+system.cpu1.rob.rob_reads                  1221498833                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1232997569                       # The number of ROB writes
+system.cpu1.timesIdled                        4096806                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       24970656                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 52437515063                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  448865132                       # Number of Instructions Simulated
+system.cpu1.committedOps                    527617659                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.509051                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.509051                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.662668                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.662668                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               693047790                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              408438474                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   823112                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  494780                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                126134775                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               127188255                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             2330176021                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15424448                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40375                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40375                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1642,11 +1926,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354224                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354216                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1663,11 +1947,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334216                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334216                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492654                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492622                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1696,71 +1980,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042420321                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1042399628                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           178996533                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           178994733                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115458                       # number of replacements
-system.iocache.tags.tagsinuse               10.429567                       # Cycle average of tags in use
+system.iocache.tags.replacements               115455                       # number of replacements
+system.iocache.tags.tagsinuse               10.429644                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13090570223000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.541524                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.888043                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221345                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430503                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651848                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13090563453000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.541528                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.888116                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221346                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430507                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651853                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039650                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039614                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039614                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8809                       # number of overall misses
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 system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1921756799                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1927241799                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1920259350                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1925744350                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28951102989                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28951102989                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28938987545                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28938987545                       # number of WriteInvalidateReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1921756799                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1927580799                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1920259350                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1926083350                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1921756799                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1927580799                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1920259350                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1926083350                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8809                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8846                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8809                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8849                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8809                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8849                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1775,54 +2059,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 218059.321343                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 217767.434915                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 217988.347145                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 217696.625593                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271423.376106                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 271423.376106                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271309.790979                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 271309.790979                       # average WriteInvalidateReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 218059.321343                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 217731.932565                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 217988.347145                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 217661.131201                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 218059.321343                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 217731.932565                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        227766                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 217988.347145                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 217661.131201                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        227974                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27719                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27752                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.216963                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.214687                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8809                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8846                       # number of ReadReq MSHR misses
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 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
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 system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
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-system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
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-system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
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+system.iocache.overall_mshr_misses::total         8849                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1463357813                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1466918813                       # number of ReadReq MSHR miss cycles
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 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23404023041                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23404023041                       # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23392010493                       # number of WriteInvalidateReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1463357813                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1467101813                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1462065868                       # number of demand (read+write) MSHR miss cycles
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 system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1463357813                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1467101813                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1462065868                       # number of overall MSHR miss cycles
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 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1837,291 +2121,291 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166045.366277                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 165753.538192                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165974.102395                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 165682.440425                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219418.201464                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219418.201464                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219305.581011                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219305.581011                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 166045.366277                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 165718.040551                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 165974.102395                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 165646.950842                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 166045.366277                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 165718.040551                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 165974.102395                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 165646.950842                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1389484                       # number of replacements
-system.l2c.tags.tagsinuse                65352.106394                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   31455593                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1452181                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.660931                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               2484843000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35806.671040                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   143.176301                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   245.153324                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3359.514416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11467.907347                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   184.237244                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   273.594467                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3844.520884                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    10027.331371                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.546366                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002185                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003741                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.051262                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.174986                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002811                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004175                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.058663                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.153005                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997194                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          343                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62354                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          341                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          538                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2779                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5047                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53889                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005234                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                295633480                       # Number of tag accesses
-system.l2c.tags.data_accesses               295633480                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       538849                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       186240                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            7977279                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3458474                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       540473                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       189439                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            8047769                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3485516                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               24424039                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         8137324                       # number of Writeback hits
-system.l2c.Writeback_hits::total              8137324                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       356242                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       359953                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       716195                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data            4893                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5150                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               10043                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             7                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 9                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           790931                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           806807                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1597738                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        538849                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu0.inst             7977279                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4249405                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        540473                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        189439                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             8047769                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4292323                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                26021777                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       538849                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       186240                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7977279                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4249405                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       540473                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       189439                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            8047769                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4292323                       # number of overall hits
-system.l2c.overall_hits::total               26021777                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2272                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2136                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            49402                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           157936                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2713                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2545                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            44633                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           153451                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               415088                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       274017                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       244202                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       518219                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         17737                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         18576                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             36313                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            3                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         284159                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         267759                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             551918                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2272                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2136                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             49402                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            442095                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2713                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2545                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             44633                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            421210                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                967006                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2272                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2136                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            49402                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           442095                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2713                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2545                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            44633                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           421210                       # number of overall misses
-system.l2c.overall_misses::total               967006                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    184273245                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    176430743                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   3875377998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  13368382174                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    220451240                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    205887741                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst   3497850741                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data  13033563402                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    34562217284                       # number of ReadReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu0.data      1654929                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::cpu1.data      1558933                       # number of WriteInvalidateReq miss cycles
-system.l2c.WriteInvalidateReq_miss_latency::total      3213862                       # number of WriteInvalidateReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data    209908987                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    215407746                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    425316733                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       146000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       146000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  27816673691                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  25868839673                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  53685513364                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    184273245                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    176430743                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3875377998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  41185055865                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    220451240                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    205887741                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.data  38902403075                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     88247730648                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    184273245                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    176430743                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3875377998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  41185055865                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    220451240                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    205887741                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3497850741                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  38902403075                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    88247730648                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       541121                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       188376                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.data        3638967                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total           24839127                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      8137324                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          8137324                       # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data       630259                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data       604155                       # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total      1234414                       # number of WriteInvalidateReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data        23726                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46356                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::cpu1.data           10                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            12                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1075090                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total          2149656                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       541121                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu0.data         4691500                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.itb.walker       191984                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.data         4713533                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            26988783                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       541121                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       188376                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu0.data        4691500                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       543186                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       191984                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        8092402                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        4713533                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           26988783                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004199                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011339                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.006155                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.043672                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004995                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.005515                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.042169                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016711                       # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.434769                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.404204                       # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total     0.419810                       # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.783783                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782939                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.783351                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.300000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.264312                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.249179                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.256747                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004199                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.011339                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006155                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.094233                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004995                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005515                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.089362                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.035830                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004199                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.011339                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006155                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.094233                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004995                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005515                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.089362                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.035830                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81106.181778                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82598.662453                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 78445.771386                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 84644.300058                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81257.368227                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80898.915914                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78369.160509                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 84936.321054                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 83264.795137                       # average ReadReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data     6.039512                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data     6.383785                       # average WriteInvalidateReq miss latency
-system.l2c.WriteInvalidateReq_avg_miss_latency::total     6.201745                       # average WriteInvalidateReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11834.525963                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11596.024225                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 11712.519841                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 48666.666667                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 48666.666667                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 97891.228823                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96612.400229                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 97270.814440                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81106.181778                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82598.662453                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 78445.771386                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 93158.836596                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81257.368227                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80898.915914                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 78369.160509                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 92358.688243                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 91258.720885                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81106.181778                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82598.662453                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 78445.771386                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 93158.836596                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81257.368227                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80898.915914                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 78369.160509                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 92358.688243                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 91258.720885                       # average overall miss latency
+system.l2c.tags.replacements                  1414814                       # number of replacements
+system.l2c.tags.tagsinuse                65356.208679                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   31586438                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1477430                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.379313                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               2484527000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35855.564521                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   171.544585                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   252.706280                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3390.645466                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    10658.750636                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   169.049447                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   250.456312                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3915.870098                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    10691.621334                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.547112                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002618                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003856                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.051737                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.162640                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002579                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003822                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.059751                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.163141                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997257                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          354                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62262                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          353                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2774                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5014                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53845                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005402                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.950043                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                297087469                       # Number of tag accesses
+system.l2c.tags.data_accesses               297087469                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker       549429                       # number of ReadReq hits
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+system.l2c.Writeback_hits::writebacks         8181117                       # number of Writeback hits
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+system.l2c.UpgradeReq_hits::cpu1.data            5155                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               10120                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_misses::total             36624                       # number of UpgradeReq misses
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+system.l2c.overall_misses::total               989783                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    212400491                       # number of ReadReq miss cycles
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+system.l2c.WriteInvalidateReq_miss_latency::cpu0.data      1493436                       # number of WriteInvalidateReq miss cycles
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+system.l2c.WriteInvalidateReq_miss_latency::total      3523350                       # number of WriteInvalidateReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data    214252799                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    214249795                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    428502594                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total        80500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  27645550958                       # number of ReadExReq miss cycles
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+system.l2c.ReadReq_accesses::total           24960177                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      8181117                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          8181117                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data       626876                       # number of WriteInvalidateReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        23672                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46744                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::total          2162441                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.demand_accesses::total            27122618                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       552049                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.dtb.walker       545115                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       186401                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total           27122618                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004746                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011813                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.006111                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.044095                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004649                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012275                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.005833                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.043500                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.017071                       # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.445498                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.397744                       # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total     0.422008                       # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784804                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782232                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.783502                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.166667                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.142857                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.267625                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.253828                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.260672                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004746                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.011813                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006111                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.095057                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004649                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.012275                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005833                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.091687                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.036493                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004746                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.011813                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006111                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.095057                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004649                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.012275                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005833                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.091687                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.036493                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81068.889695                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82289.614679                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 78225.269585                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 84017.766201                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80469.510260                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81079.106206                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78355.014564                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 84748.983776                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 82928.205163                       # average ReadReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data     5.347604                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data     8.409445                       # average WriteInvalidateReq miss latency
+system.l2c.WriteInvalidateReq_avg_miss_latency::total     6.767123                       # average WriteInvalidateReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11832.595074                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11570.437706                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 11700.048984                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96306.498889                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95968.799873                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 96140.773333                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81068.889695                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82289.614679                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 78225.269585                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 91905.612656                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80469.510260                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81079.106206                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 78355.014564                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 91865.272220                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 90452.837243                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81068.889695                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82289.614679                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 78225.269585                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 91905.612656                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80469.510260                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81079.106206                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 78355.014564                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 91865.272220                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 90452.837243                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2130,200 +2414,197 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1175694                       # number of writebacks
-system.l2c.writebacks::total                  1175694                       # number of writebacks
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+system.l2c.writebacks::writebacks             1192634                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu0.data            13                       # number of ReadReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu0.data             13                       # number of demand (read+write) MSHR hits
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2623804750                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2619741250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6356764499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2581434500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2590216000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5171650500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2653037250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6356765499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2607030000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2564595500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5171625500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    654614249                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5238534250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5230834750                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    425309250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5209957250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11528414999                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.043668                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.042167                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016706                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.434769                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.404204                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.419810                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.783783                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782939                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.783351                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.300000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.264312                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.249179                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.256747                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.094230                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.089360                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035825                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004164                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011148                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.094230                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004969                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013032                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005515                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.089360                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035825                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72215.099662                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72505.449672                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 70810.722538                       # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38285.106698                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39123.441561                       # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38680.157922                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.757738                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10013.677326                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.181946                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 44000.333333                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44000.333333                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85430.788076                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84150.197823                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 84809.519037                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80709.806083                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79908.040638                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 78801.657987                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65897.186275                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80709.806083                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65814.719791                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79908.040638                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 78801.657987                       # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5217632750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11528390999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004728                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011626                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.006111                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.044091                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004621                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012098                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005833                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.043497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.017066                       # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.445498                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.397744                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.422008                       # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784804                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782232                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.783502                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.142857                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.267625                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.253828                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.260672                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004728                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011626                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006111                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.095054                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004621                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012098                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005833                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.091685                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.036489                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004728                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011626                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006111                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.095054                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004621                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012098                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005833                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.091685                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.036489                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65676.173835                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 71586.782929                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65799.360833                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72316.823373                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 70470.064489                       # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37932.216105                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39412.539959                       # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38618.518168                       # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.220688                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.286547                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10013.737194                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        68500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83846.404002                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 83507.798698                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 83680.233686                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65676.173835                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79456.172080                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65799.360833                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79414.965722                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 77994.234960                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65676.173835                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79456.172080                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65799.360833                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79414.965722                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 77994.234960                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -2338,57 +2619,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              478201                       # Transaction distribution
-system.membus.trans_dist::ReadResp             478201                       # Transaction distribution
+system.membus.trans_dist::ReadReq              489224                       # Transaction distribution
+system.membus.trans_dist::ReadResp             489224                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33860                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33860                       # Transaction distribution
-system.membus.trans_dist::Writeback           1282324                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       624745                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       624745                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37074                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           37077                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            551298                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           551298                       # Transaction distribution
+system.membus.trans_dist::Writeback           1299265                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       627170                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       627170                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37411                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           37412                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            563054                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           563054                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4264222                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4394358                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335421                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       335421                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4729779                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4332246                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4462384                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335088                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       335088                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4797472                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    171538732                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    171711000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14073856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14073856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               185784856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2907                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2919339                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13740                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    174236076                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    174408348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14052800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14052800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               188461148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3233                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2961771                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2919339    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2961771    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2919339                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            99723000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2961771                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            99708500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54328                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5540499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5504999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         18597273982                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         18802986477                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         9904783124                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        10120184001                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186654467                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          186568267                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2432,58 +2713,58 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           25451799                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25443711                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq           25574289                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25566182                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33860                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33860                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8137324                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1341081                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1234414                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46359                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46371                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2149656                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2149656                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     32279635                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29644963                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       905204                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2573359                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              65403161                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1032942144                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1201952920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3042880                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8674456                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2246612400                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          665707                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         37265900                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003100                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.055590                       # Request fanout histogram
+system.toL2Bus.trans_dist::Writeback          8181117                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1340428                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1233761                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46747                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46754                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2162441                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2162441                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     32390529                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29801361                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       923404                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2600212                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              65715506                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1036485248                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1208333724                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3115152                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8777312                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2256711436                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          667123                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         37442651                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003085                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.055458                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               37150380     99.69%     99.69% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115520      0.31%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               37327135     99.69%     99.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115516      0.31%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           37265900                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        56232033216                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           37442651                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        56492183787                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          3430500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          3327000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       72693447528                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       72944134855                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       43148678653                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       43405971950                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         527770675                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         537017212                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1503131700                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1517407654                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16411                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   16420                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 549c3e2c6..b93c1aabd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,158 +1,158 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.781932                       # Number of seconds simulated
-sim_ticks                                51781931516000                       # Number of ticks simulated
-final_tick                               51781931516000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.861398                       # Number of seconds simulated
+sim_ticks                                51861397612000                       # Number of ticks simulated
+final_tick                               51861397612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 513884                       # Simulator instruction rate (inst/s)
-host_op_rate                                   603881                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31103019215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 672564                       # Number of bytes of host memory used
-host_seconds                                  1664.85                       # Real time elapsed on the host
-sim_insts                                   855540358                       # Number of instructions simulated
-sim_ops                                    1005371984                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 682840                       # Simulator instruction rate (inst/s)
+host_op_rate                                   802417                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            40752483757                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 728928                       # Number of bytes of host memory used
+host_seconds                                  1272.59                       # Real time elapsed on the host
+sim_insts                                   868978236                       # Number of instructions simulated
+sim_ops                                    1021151568                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       107200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       102528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2434152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20994800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        96832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       103680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2545804                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         20458904                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        379200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             47223100                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2434152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2545804                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4979956                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68447104                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       110912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       113344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2519016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         22396080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       118144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       113984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2612108                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         22226264                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        390656                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             50600508                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2519016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2612108                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5131124                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     71823424                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68467684                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1675                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1602                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             65448                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            328047                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1513                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1620                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             52771                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            319680                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           5925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                778281                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1069486                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          71844004                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1733                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1771                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             66774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            349942                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1846                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1781                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             53807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            347295                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6104                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                831053                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1122241                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1072059                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2070                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1980                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               47008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              405446                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2002                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               49164                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              395097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7323                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  911961                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          47008                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          49164                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              96172                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1321834                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1124814                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               48572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              431845                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2278                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2198                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               50367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              428570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  975687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          48572                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          50367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              98939                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1384911                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1322231                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1321834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1980                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              47008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             405447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2002                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              49164                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             395495                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7323                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2234192                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        778281                       # Number of read requests accepted
-system.physmem.writeReqs                      1672780                       # Number of write requests accepted
-system.physmem.readBursts                      778281                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1672780                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 49778368                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     31616                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 106609920                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  47223100                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              106913828                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      494                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    6998                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          34417                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               49121                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               48968                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               43998                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               44044                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               46923                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               50978                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               43709                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               43367                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               43043                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               89491                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              47224                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              49584                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              42821                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              45810                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42383                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              46323                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              104557                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              105414                       # Per bank write bursts
-system.physmem.perBankWrBursts::2              105583                       # Per bank write bursts
-system.physmem.perBankWrBursts::3              103819                       # Per bank write bursts
-system.physmem.perBankWrBursts::4              104348                       # Per bank write bursts
-system.physmem.perBankWrBursts::5              108141                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              101114                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              100245                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               99850                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              106510                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102540                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             107777                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             103459                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             105336                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             101779                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             105308                       # Per bank write bursts
+system.physmem.bw_write::total                1385308                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1384911                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2186                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              48572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             431845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2278                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              50367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             428967                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7533                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2360995                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        831053                       # Number of read requests accepted
+system.physmem.writeReqs                      1733697                       # Number of write requests accepted
+system.physmem.readBursts                      831053                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1733697                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 53155264                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     32128                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 110517504                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  50600508                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              110812516                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      502                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    6857                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          35215                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               52772                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               58055                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               48746                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               51625                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               50901                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               53731                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               47545                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               46576                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               47759                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               90120                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              47452                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              51057                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              47939                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              45720                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              43868                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              46685                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              110572                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              116599                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              110707                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              112437                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              109828                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              113045                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              105073                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              102356                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              103784                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              107644                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             104570                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             108123                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             106842                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             106503                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             103411                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             105342                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51781928959500                       # Total gap between requests
+system.physmem.totGap                    51861395055500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  735165                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  787937                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1670207                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    745946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     26414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1937                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       535                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       685                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       348                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       204                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1731124                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::6                       363                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::9                       140                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      125                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                      110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       77                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       78                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -165,178 +165,207 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1453                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1436                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    55685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    67964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    89945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    92025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    95463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                   110001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                   113998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    99922                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24                    98621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    96222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    93100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    89862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    88090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    83497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    82653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    82465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    81037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1910                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1714                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       531423                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.281520                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     167.194093                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.137010                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         219913     41.38%     41.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       131435     24.73%     66.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44338      8.34%     74.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23886      4.49%     78.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15966      3.00%     81.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10709      2.02%     83.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7995      1.50%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7287      1.37%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        69894     13.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         531423                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         80476                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean         9.664621                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       89.984802                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          80471     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                      1646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1586                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::3                      1541                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                    93700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    91898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    87418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    86273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    85861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    84522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1575                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      799                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      525                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       563789                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      290.307984                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     165.321614                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.078407                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         235457     41.76%     41.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       139953     24.82%     66.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        46694      8.28%     74.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        25357      4.50%     79.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        16838      2.99%     82.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11479      2.04%     84.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8496      1.51%     85.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7843      1.39%     87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        71672     12.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         563789                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         84234                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean         9.859653                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       88.079162                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          84229     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::5120-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-7167            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           80476                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         80476                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.699090                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.496721                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.527834                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7               200      0.25%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15              177      0.22%      0.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           72247     89.77%     90.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            4200      5.22%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39            1327      1.65%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             446      0.55%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             582      0.72%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             137      0.17%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             223      0.28%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             119      0.15%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             159      0.20%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              60      0.07%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            172      0.21%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            43      0.05%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            70      0.09%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127            53      0.07%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135           161      0.20%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143            11      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            23      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167            15      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183            11      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             4      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             4      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           80476                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9983720499                       # Total ticks spent queuing
-system.physmem.totMemAccLat               24567226749                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3888935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12836.06                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           84234                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         84234                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.500463                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.372295                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.059087                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3               108      0.13%      0.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                80      0.09%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               54      0.06%      0.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15             121      0.14%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           46153     54.79%     55.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23           30225     35.88%     91.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            2462      2.92%     94.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1364      1.62%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             933      1.11%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             416      0.49%     97.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             269      0.32%     97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             164      0.19%     97.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             538      0.64%     98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              68      0.08%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              77      0.09%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              53      0.06%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             163      0.19%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              54      0.06%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              29      0.03%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              79      0.09%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             145      0.17%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              43      0.05%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              17      0.02%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              33      0.04%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             176      0.21%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            15      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            19      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            14      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            61      0.07%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            20      0.02%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            40      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            24      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131           103      0.12%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            13      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.00%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             9      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            13      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            10      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             9      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            10      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             6      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             4      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             4      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           84234                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10578626250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               26151457500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4152755000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12736.88                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31586.06                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.06                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.91                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.06                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31486.88                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.02                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.13                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.17                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     580589                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1331554                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.94                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21126332.21                       # Average gap between requests
-system.physmem.pageHitRate                      78.25                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     49696712332000                       # Time in different power states
-system.physmem.memoryStateTime::REF      1729112320000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      356106481500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                2031447600                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                1986110280                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                1108428750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                1083691125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               2894642400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               3172057200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0              5399272080                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1              5394982320                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          3382143697920                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          3382143697920                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          1286313063165                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          1285469654400                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          29940811051500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          29941550883750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            34620701603415                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            34620801076995                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.586590                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.588511                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        12.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     620179                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1373418                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.53                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20220838.31                       # Average gap between requests
+system.physmem.pageHitRate                      77.95                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2224749240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1213900875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3197578800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5706398160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3387334061280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1303736226660                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29973207455250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34676620370265                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.640359                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49862520204500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1731765880000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    267111145000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                 2037495600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1111728750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3280680000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5483499120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3387334061280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1287848520900                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29987144039250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34674240024900                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.594461                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49885777301500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1731765880000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    243849706000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -360,6 +389,14 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -381,27 +418,76 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   125209                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               125209                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        19669                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90325                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           16                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       125193                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         125193    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       125193                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       110010                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22089.371421                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18317.414501                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 13164.465309                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767       107059     97.32%     97.32% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         2114      1.92%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          606      0.55%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          110      0.10%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           25      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           28      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           25      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           18      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       110010                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   3295703864                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.071233                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     -234762296     -7.12%     -7.12% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1     3530466160    107.12%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   3295703864                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        90326     82.12%     82.12% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        19669     17.88%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       109995                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       125209                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       125209                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       109995                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       109995                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       235204                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    80391901                       # DTB read hits
-system.cpu0.dtb.read_misses                     93388                       # DTB read misses
-system.cpu0.dtb.write_hits                   73043030                       # DTB write hits
-system.cpu0.dtb.write_misses                    28813                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51784                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    81853035                       # DTB read hits
+system.cpu0.dtb.read_misses                     95759                       # DTB read misses
+system.cpu0.dtb.write_hits                   74321037                       # DTB write hits
+system.cpu0.dtb.write_misses                    29450                       # DTB write misses
+system.cpu0.dtb.flush_tlb                       51862                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   70641                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              20132                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    528                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   71205                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4105                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4306                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9619                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                80485289                       # DTB read accesses
-system.cpu0.dtb.write_accesses               73071843                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9531                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                81948794                       # DTB read accesses
+system.cpu0.dtb.write_accesses               74350487                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        153434931                       # DTB hits
-system.cpu0.dtb.misses                         122201                       # DTB misses
-system.cpu0.dtb.accesses                    153557132                       # DTB accesses
+system.cpu0.dtb.hits                        156174072                       # DTB hits
+system.cpu0.dtb.misses                         125209                       # DTB misses
+system.cpu0.dtb.accesses                    156299281                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -423,242 +509,284 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                   427471663                       # ITB inst hits
-system.cpu0.itb.inst_misses                     76376                       # ITB inst misses
+system.cpu0.itb.walker.walks                    77027                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                77027                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4349                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67368                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        77027                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          77027    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        77027                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        71717                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25312.366663                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 21958.347721                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 14763.140629                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        66172     92.27%     92.27% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         4523      6.31%     98.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303          706      0.98%     99.56% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          175      0.24%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           37      0.05%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           34      0.05%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           34      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            9      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        71717                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   -294463796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     -294463796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   -294463796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        67368     93.94%     93.94% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         4349      6.06%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        71717                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77027                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77027                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71717                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71717                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       148744                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   434570813                       # ITB inst hits
+system.cpu0.itb.inst_misses                     77027                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51784                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                       51862                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   52019                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              20132                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    528                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   52030                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               427548039                       # ITB inst accesses
-system.cpu0.itb.hits                        427471663                       # DTB hits
-system.cpu0.itb.misses                          76376                       # DTB misses
-system.cpu0.itb.accesses                    427548039                       # DTB accesses
-system.cpu0.numCycles                     51782412762                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               434647840                       # ITB inst accesses
+system.cpu0.itb.hits                        434570813                       # DTB hits
+system.cpu0.itb.misses                          77027                       # DTB misses
+system.cpu0.itb.accesses                    434647840                       # DTB accesses
+system.cpu0.numCycles                     51862348340                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  427217866                       # Number of instructions committed
-system.cpu0.committedOps                    502133426                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            461356318                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                442453                       # Number of float alu accesses
-system.cpu0.num_func_calls                   25480565                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     64997329                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   461356318                       # number of integer instructions
-system.cpu0.num_fp_insts                       442453                       # number of float instructions
-system.cpu0.num_int_register_reads          669433821                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         365789159                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              711452                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             379824                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           111391626                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          111077654                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    153423964                       # number of memory refs
-system.cpu0.num_load_insts                   80387324                       # Number of load instructions
-system.cpu0.num_store_insts                  73036640                       # Number of store instructions
-system.cpu0.num_idle_cycles              50249111943.842865                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1533300818.157139                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.029610                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.970390                       # Percentage of idle cycles
-system.cpu0.Branches                         95379703                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                347836061     69.23%     69.23% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1052847      0.21%     69.44% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    47944      0.01%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  6      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  5      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  9      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.45% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             55653      0.01%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::MemRead                80387324     16.00%     85.46% # Class of executed instruction
-system.cpu0.op_class::MemWrite               73036640     14.54%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                  434316413                       # Number of instructions committed
+system.cpu0.committedOps                    510251172                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            468762245                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                455279                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25833192                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     66107864                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   468762245                       # number of integer instructions
+system.cpu0.num_fp_insts                       455279                       # number of float instructions
+system.cpu0.num_int_register_reads          680505745                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         371520195                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              735714                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             382992                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           113236512                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          112912982                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    156164016                       # number of memory refs
+system.cpu0.num_load_insts                   81849666                       # Number of load instructions
+system.cpu0.num_store_insts                  74314350                       # Number of store instructions
+system.cpu0.num_idle_cycles              50300563806.190483                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1561784533.809517                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.030114                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.969886                       # Percentage of idle cycles
+system.cpu0.Branches                         96959859                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                353181248     69.18%     69.18% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1084077      0.21%     69.39% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49491      0.01%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  6      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  8      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                 12      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             55978      0.01%     69.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
+system.cpu0.op_class::MemRead                81849666     16.03%     85.44% # Class of executed instruction
+system.cpu0.op_class::MemWrite               74314350     14.56%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 502416489                       # Class of executed instruction
+system.cpu0.op_class::total                 510534837                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16160                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          9666641                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.969685                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          297154926                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9667153                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.738618                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   16221                       # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements          9866178                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.969728                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          301750178                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9866690                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.582716                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       3092948250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   283.466253                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   228.503431                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.553645                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.446296                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   290.086465                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   221.883263                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.566575                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.433366                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1237347722                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1237347722                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     75260834                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     75246301                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      150507135                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     69349664                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     69346777                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     138696441                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190562                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       191577                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       382139                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       171619                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       160816                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total       332435                       # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1711920                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1739353                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3451273                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1857030                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1885244                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3742274                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    144610498                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    144593078                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       289203576                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    144801060                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    144784655                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      289585715                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2479823                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2539735                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      5019558                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1027548                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1051512                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2079060                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       586953                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604316                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1191269                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       612872                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       613029                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total      1225901                       # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145963                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       146688                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       292651                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1256728908                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1256728908                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     76588751                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     76163346                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      152752097                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     70555546                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total     140883010                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190561                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       196148                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       386709                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       172423                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       161036                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total       333459                       # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1750003                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1777885                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3527888                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1897893                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1924897                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3822790                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147144297                       # number of demand (read+write) hits
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+system.cpu0.dcache.demand_hits::total       293635107                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147334858                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total      294021816                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2557843                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      2571612                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      5129455                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1050273                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1078042                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2128315                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       601274                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       625393                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1226667                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       620770                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       607819                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total      1228589                       # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148787                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       147781                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       296568                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3507371                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3591247                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       7098618                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4094324                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      4195563                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      8289887                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38409075253                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  39279047002                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  77688122255                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  27659575882                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  27687644531                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  55347220413                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  13571753508                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13540403000                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27112156508                       # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2071723750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2095160250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4166884000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        75000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        75000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  66068651135                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  66966691533                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 133035342668                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  66068651135                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  66966691533                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 133035342668                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     77740657                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     77786036                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    155526693                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     70377212                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     70398289                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    140775501                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       777515                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       795893                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1573408                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       784491                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       773845                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total      1558336                       # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1857883                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1886041                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3743924                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1857031                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1885244                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3742275                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    148117869                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    148184325                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    296302194                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    148895384                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    148980218                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    297875602                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031899                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032650                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032275                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014601                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014937                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.014769                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754909                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.759293                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757127                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.781235                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.792186                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078564                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077776                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078167                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3608116                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      3649654                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       7257770                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4209390                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      4275047                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      8484437                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  39628260752                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  40050042255                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  79678303007                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29258978305                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  29205004656                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  58463982961                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  13856629500                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13463537506                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27320167006                       # number of WriteInvalidateReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2109696250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2149698750                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4259395000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        26501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        75000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       101501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  68887239057                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  69255046911                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 138142285968                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  68887239057                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  69255046911                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 138142285968                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     79146594                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     78734958                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    157881552                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     71605819                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     71405506                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    143011325                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       791835                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       821541                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1613376                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       793193                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       768855                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.WriteInvalidateReq_accesses::total      1562048                       # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1898790                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1925666                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3824456                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1897894                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1924898                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3822792                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    150752413                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    150140464                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    300892877                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    151544248                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    150962005                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    302506253                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032318                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032662                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032489                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014667                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015097                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.014882                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759343                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.761244                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760311                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.782622                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.790551                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786524                       # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078359                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076743                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077545                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023680                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024235                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.023957                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027498                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028162                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027830                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15488.635783                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15465.805291                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15477.084288                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26918.037777                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26331.268241                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 26621.271350                       # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 22144.515507                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 22087.703844                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 22116.106038                       # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14193.485678                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14283.105980                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14238.406840                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        75000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18837.086563                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18647.197348                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18741.020107                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16136.644568                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15961.312351                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16047.907851                       # average overall miss latency
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023934                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024308                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.024121                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027777                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028319                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028047                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15492.843287                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15573.905494                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15533.483188                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 27858.450427                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27090.785569                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 27469.609978                       # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 22321.680332                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 22150.570328                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 22237.027196                       # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14179.304980                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14546.516467                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14362.287907                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        26501                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        75000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 50750.500000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19092.301649                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18975.784255                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19033.709523                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16365.135817                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16199.832870                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16281.844743                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -667,124 +795,128 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7479557                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7479557                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3745                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2865                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total         6610                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10175                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11006                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21181                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        34675                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35236                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        69911                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        13920                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        13871                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        27791                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        13920                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        13871                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        27791                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2476078                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2536870                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5012948                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1017373                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1040506                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2057879                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       586808                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       604126                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1190934                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       612872                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       613029                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1225901                       # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       111288                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       111452                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       222740                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7621991                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7621991                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3442                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3110                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total         6552                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10246                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        10994                       # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35721                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        70539                       # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::cpu1.data        14104                       # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::cpu0.data        13688                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data        14104                       # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2554401                       # number of ReadReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_misses::total      5122903                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1040027                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       226029                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3493451                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3577376                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7070827                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4080259                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4181502                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      8261761                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  33166863497                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  33981034998                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  67147898495                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25195325118                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  25212990469                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  50408315587                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   8922621248                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   8744886500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17667507748                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  12346009492                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12314345000                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  24660354492                       # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1340334000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1349733250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2690067250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        73000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        73000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58362188615                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  59194025467                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 117556214082                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  67284809863                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  67938911967                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 135223721830                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2674522248                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3054322749                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5728844997                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2557892750                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3016153500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5574046250                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5232414998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6070476249                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11302891247                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031850                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032613                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032232                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014456                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014780                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014618                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754722                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759054                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756914                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.781235                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.792186                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786673                       # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059900                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059093                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059494                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3594428                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3635550                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7229978                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4195560                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4260757                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      8456317                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  34255815748                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  34669168995                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  68924984743                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  26736974445                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  26668792594                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  53405767039                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   8942698000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   9200320250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18143018250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  12615089500                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12247899494                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  24862988994                       # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1372094500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1380082250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2752176750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        24499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        73000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        97499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  60992790193                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  61337961589                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 122330751782                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  69935488193                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  70538281839                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 140473770032                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2674956999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3053270500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5728227499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2550639000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3023463750                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5574102750                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5225595999                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6076734250                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11302330249                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032274                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032622                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032448                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014524                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014943                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014734                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.759163                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.761017                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.760107                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.782622                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.790551                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786524                       # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060022                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058193                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059101                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023586                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024141                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023864                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027404                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028067                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027736                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025                       # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        73000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023843                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024214                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024028                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027685                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028224                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.027954                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13410.508275                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13497.816624                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13454.282609                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25707.961856                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24993.058039                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25345.926006                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14876.429802                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14715.638581                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.455897                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20321.680332                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20150.570308                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20237.027186                       # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12039.190482                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12315.565322                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12176.210796                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        24499                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        73000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 48749.500000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16968.705506                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16871.714483                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16919.934166                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16668.928151                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16555.340246                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16611.696325                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -795,79 +927,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         13477112                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.892486                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          842591946                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13477624                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            62.517840                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      32076200250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.322157                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   270.570329                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471332                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.528458                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         13777264                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.892662                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          855737357                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         13777776                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            62.109977                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      32072682250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   274.033427                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   237.859235                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.535222                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.464569                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999790                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        869547204                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       869547204                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    420727456                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    421864490                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      842591946                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    420727456                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    421864490                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       842591946                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    420727456                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    421864490                       # number of overall hits
-system.cpu0.icache.overall_hits::total      842591946                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6744207                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6733422                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     13477629                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6744207                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      6733422                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      13477629                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6744207                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      6733422                       # number of overall misses
-system.cpu0.icache.overall_misses::total     13477629                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  90268756253                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90304288753                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 180573045006                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  90268756253                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  90304288753                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 180573045006                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  90268756253                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  90304288753                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 180573045006                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    427471663                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    428597912                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    856069575                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    427471663                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    428597912                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    856069575                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    427471663                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    428597912                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    856069575                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015777                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015710                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.015744                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015777                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015710                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.015744                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015777                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015710                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.015744                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13384.636067                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13411.351428                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13397.983058                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13397.983058                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13397.983058                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        883292919                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       883292919                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    427701374                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    428035983                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      855737357                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    427701374                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    428035983                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       855737357                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    427701374                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    428035983                       # number of overall hits
+system.cpu0.icache.overall_hits::total      855737357                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6869439                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      6908342                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     13777781                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6869439                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      6908342                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      13777781                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6869439                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      6908342                       # number of overall misses
+system.cpu0.icache.overall_misses::total     13777781                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91986566006                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  92647567751                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 184634133757                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  91986566006                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  92647567751                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 184634133757                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  91986566006                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  92647567751                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 184634133757                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    434570813                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    434944325                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    869515138                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    434570813                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    434944325                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    869515138                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    434570813                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    434944325                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    869515138                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015807                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015883                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.015845                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015807                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015883                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.015845                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015807                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015883                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.015845                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13390.695515                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13410.970064                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13400.861413                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13390.695515                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13410.970064                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13400.861413                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13390.695515                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13410.970064                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13400.861413                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -876,48 +1008,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6744207                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6733422                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     13477629                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6744207                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6733422                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13477629                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6744207                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6733422                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13477629                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  76767439747                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  76823488247                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 153590927994                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  76767439747                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  76823488247                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 153590927994                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  76767439747                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  76823488247                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 153590927994                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6869439                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6908342                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     13777781                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6869439                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      6908342                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     13777781                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6869439                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      6908342                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     13777781                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  78234289494                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  78816452749                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 157050742243                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  78234289494                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  78816452749                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 157050742243                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  78234289494                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  78816452749                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 157050742243                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2831704500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   2831704500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015744                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.015744                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.015744                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11395.990199                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015807                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015883                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015845                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015807                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015883                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.015845                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015807                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015883                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.015845                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11388.745063                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11408.881139                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11398.841529                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11388.745063                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11408.881139                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11398.841529                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11388.745063                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11408.881139                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11398.841529                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -925,6 +1057,14 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -946,27 +1086,81 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   127972                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               127972                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        19780                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92740                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore           16                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       127956                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.265716                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    71.272998                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047       127954    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       127956                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       112536                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22019.187193                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18129.081838                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13444.450617                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767       109487     97.29%     97.29% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         2144      1.91%     99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          659      0.59%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          117      0.10%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839           32      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           27      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375           23      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           20      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            8      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       112536                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   6637919892                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     1.174468                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1158102796    -17.45%    -17.45% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     7796022688    117.45%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   6637919892                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        92740     82.42%     82.42% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        19780     17.58%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       112520                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       127972                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       127972                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       112520                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       112520                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       240492                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    80485889                       # DTB read hits
-system.cpu1.dtb.read_misses                     94650                       # DTB read misses
-system.cpu1.dtb.write_hits                   73083689                       # DTB write hits
-system.cpu1.dtb.write_misses                    28922                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51788                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    81500118                       # DTB read hits
+system.cpu1.dtb.read_misses                     97955                       # DTB read misses
+system.cpu1.dtb.write_hits                   74126007                       # DTB write hits
+system.cpu1.dtb.write_misses                    30017                       # DTB write misses
+system.cpu1.dtb.flush_tlb                       51868                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   69957                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              20724                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    513                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   72099                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4240                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4473                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9564                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                80580539                       # DTB read accesses
-system.cpu1.dtb.write_accesses               73112611                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9907                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                81598073                       # DTB read accesses
+system.cpu1.dtb.write_accesses               74156024                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        153569578                       # DTB hits
-system.cpu1.dtb.misses                         123572                       # DTB misses
-system.cpu1.dtb.accesses                    153693150                       # DTB accesses
+system.cpu1.dtb.hits                        155626125                       # DTB hits
+system.cpu1.dtb.misses                         127972                       # DTB misses
+system.cpu1.dtb.accesses                    155754097                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -988,91 +1182,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                   428597912                       # ITB inst hits
-system.cpu1.itb.inst_misses                     76336                       # ITB inst misses
+system.cpu1.itb.walker.walks                    77421                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                77421                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4271                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        67596                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        77421                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          77421    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        77421                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        71867                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24990.746796                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21538.641816                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14943.355403                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        66410     92.41%     92.41% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         4449      6.19%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          690      0.96%     99.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          184      0.26%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           29      0.04%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           30      0.04%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           33      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           19      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        71867                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1257793296                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1257793296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1257793296                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        67596     94.06%     94.06% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         4271      5.94%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        71867                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77421                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77421                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71867                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71867                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       149288                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   434944325                       # ITB inst hits
+system.cpu1.itb.inst_misses                     77421                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51788                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                       51868                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   51781                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              20724                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    513                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   53256                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               428674248                       # ITB inst accesses
-system.cpu1.itb.hits                        428597912                       # DTB hits
-system.cpu1.itb.misses                          76336                       # DTB misses
-system.cpu1.itb.accesses                    428674248                       # DTB accesses
-system.cpu1.numCycles                     51781450270                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               435021746                       # ITB inst accesses
+system.cpu1.itb.hits                        434944325                       # DTB hits
+system.cpu1.itb.misses                          77421                       # DTB misses
+system.cpu1.itb.accesses                    435021746                       # DTB accesses
+system.cpu1.numCycles                     51860446884                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  428322492                       # Number of instructions committed
-system.cpu1.committedOps                    503238558                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            462373470                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                457847                       # Number of float alu accesses
-system.cpu1.num_func_calls                   25589000                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     65138542                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   462373470                       # number of integer instructions
-system.cpu1.num_fp_insts                       457847                       # number of float instructions
-system.cpu1.num_int_register_reads          672243876                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         366665103                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              741025                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             381476                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           111687570                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          111401234                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    153562143                       # number of memory refs
-system.cpu1.num_load_insts                   80482788                       # Number of load instructions
-system.cpu1.num_store_insts                  73079355                       # Number of store instructions
-system.cpu1.num_idle_cycles              50246687172.676186                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1534763097.323812                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.029639                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.970361                       # Percentage of idle cycles
-system.cpu1.Branches                         95580848                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                348749586     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1110324      0.22%     69.48% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    49704      0.01%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  2      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  8      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 12      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             56056      0.01%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
-system.cpu1.op_class::MemRead                80482788     15.98%     85.49% # Class of executed instruction
-system.cpu1.op_class::MemWrite               73079355     14.51%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                  434661823                       # Number of instructions committed
+system.cpu1.committedOps                    510900396                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            469262912                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                444776                       # Number of float alu accesses
+system.cpu1.num_func_calls                   25944068                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     66238146                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   469262912                       # number of integer instructions
+system.cpu1.num_fp_insts                       444776                       # number of float instructions
+system.cpu1.num_int_register_reads          683773696                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         372368162                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              716331                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             377944                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           113908068                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          113630972                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    155618629                       # number of memory refs
+system.cpu1.num_load_insts                   81496317                       # Number of load instructions
+system.cpu1.num_store_insts                  74122312                       # Number of store instructions
+system.cpu1.num_idle_cycles              50297346072.144875                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1563100811.855124                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030141                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969859                       # Percentage of idle cycles
+system.cpu1.Branches                         97056682                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                354376144     69.32%     69.32% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1097996      0.21%     69.54% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    48675      0.01%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  2      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  5      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  9      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             55297      0.01%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::MemRead                81496317     15.94%     85.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite               74122312     14.50%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 503527836                       # Class of executed instruction
+system.cpu1.op_class::total                 511196757                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq                40424                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40424                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40404                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40404                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
@@ -1092,11 +1326,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231044                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231044                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231004                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231004                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354314                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354274                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1113,11 +1347,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334448                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334448                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7493014                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  7492854                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
@@ -1146,71 +1380,71 @@ system.iobus.reqLayer25.occupancy            32658000                       # La
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy          1042410724                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy          1042408857                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           179081273                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           179045538                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115504                       # number of replacements
-system.iocache.tags.tagsinuse               10.454717                       # Cycle average of tags in use
+system.iocache.tags.replacements               115484                       # number of replacements
+system.iocache.tags.tagsinuse               10.461673                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115520                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13154373196000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.509635                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.945082                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219352                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434068                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653420                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13154364038000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.508099                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.953575                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219256                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434598                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653855                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040055                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040055                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039875                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039875                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8858                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8895                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8838                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8875                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8858                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8898                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8838                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8878                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8858                       # number of overall misses
-system.iocache.overall_misses::total             8898                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5479000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1913667012                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1919146012                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8838                       # number of overall misses
+system.iocache.overall_misses::total             8878                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5485000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1903038512                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1908523512                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28832566439                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  28832566439                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5818000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1913667012                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1919485012                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5818000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1913667012                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1919485012                       # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28811758807                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  28811758807                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5824000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1903038512                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1908862512                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5824000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1903038512                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1908862512                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8858                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8895                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8838                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8875                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8858                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8898                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8838                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8878                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8858                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8898                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8838                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8878                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1224,55 +1458,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 215755.594379                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 215324.565739                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 215044.902761                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 215720.949876                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 215720.949876                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        223529                       # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270116.991740                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 270116.991740                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 215324.565739                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 215010.420365                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       145600                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 215324.565739                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 215010.420365                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        222004                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                27514                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                27403                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.124191                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.101449                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8858                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8895                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8838                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8875                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8858                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8898                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8838                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8878                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8858                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8898                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3555000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1452961512                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1456516512                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8838                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8878                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3561000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1443371512                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1446932512                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3738000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1452961512                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1456699512                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3738000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1452961512                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1456699512                       # number of overall MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23265154883                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23265154883                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3744000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1443371512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1447115512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3744000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1443371512                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1447115512                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1286,286 +1520,290 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164028.167984                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 163745.532546                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163314.269292                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 163034.649239                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218311.637338                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218311.637338                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218116.279935                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218116.279935                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 163314.269292                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 163000.170309                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93600                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 163314.269292                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 163000.170309                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1132290                       # number of replacements
-system.l2c.tags.tagsinuse                65332.905134                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   26887895                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1194294                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    22.513631                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1193420                       # number of replacements
+system.l2c.tags.tagsinuse                65274.322363                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   27445630                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1256045                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.850833                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle               6379783000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38092.537924                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   152.896952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   229.074218                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2954.015231                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9873.444708                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.350600                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   215.925176                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4167.527871                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9496.132455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.581246                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002333                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002309                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        61762                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          241                       # Occupied blocks per task id
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+system.l2c.tags.occ_blocks::cpu0.itb.walker   238.258282                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3135.660678                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9757.187471                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   161.764164                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   237.073896                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3594.762150                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9584.546752                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002531                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.148883                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002468                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003617                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.054852                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.146249                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996007                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62385                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          240                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          421                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2430                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5430                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53446                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003693                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.942413                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                255508368                       # Number of tag accesses
-system.l2c.tags.data_accesses               255508368                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       218363                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       160178                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst            6707988                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data            3047209                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       224681                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       161726                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst            6694510                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data            3129038                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total               20343693                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         7479557                       # number of Writeback hits
-system.l2c.Writeback_hits::total              7479557                       # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data       365275                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data       366564                       # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total       731839                       # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data            4770                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4600                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9370                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           793764                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           822353                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1616117                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        218363                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        160178                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6707988                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3840973                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.itb.walker        161726                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             6694510                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             3951391                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                21959810                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       218363                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       160178                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6707988                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3840973                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       224681                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       161726                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            6694510                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            3951391                       # number of overall hits
-system.l2c.overall_hits::total               21959810                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1675                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1602                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            36219                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           126965                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         1513                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         1620                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst            38912                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data           123410                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               331916                       # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data       247597                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data       246465                       # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total       494062                       # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         17085                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         16773                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             33858                       # number of UpgradeReq misses
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+system.l2c.tags.age_task_id_blocks_1024::3         5459                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54075                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.951920                       # Percentage of cache occupancy per task id
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+system.l2c.ReadReq_hits::total               20802841                       # number of ReadReq hits
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+system.l2c.Writeback_hits::total              7621991                       # number of Writeback hits
+system.l2c.WriteInvalidateReq_hits::cpu0.data       364580                       # number of WriteInvalidateReq hits
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 system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1574,173 +1812,177 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    173897376                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    346739651                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        60000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        70001                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    119482500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    123968000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    121118750                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total  48494032076                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2468159752                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2469002751                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2821001751                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7538131503                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2382381500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2784161000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5166542500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2819508250                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2376122500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2790457500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5166580000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4850541252                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4845125251                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5605162751                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12704674003                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.039999                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.037944                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016054                       # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.403995                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.402045                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.403019                       # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781743                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784775                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.783242                       # mshr miss rate for UpgradeReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5609965750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12704061001                       # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005783                       # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782440                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.783619                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.202662                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.193086                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.197818                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63439.189981                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63571.088259                       # average ReadReq mshr miss latency
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-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21627.881226                       # average WriteInvalidateReq mshr miss latency
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-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21611.964709                       # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.950776                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.980922                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.470317                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        60000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61172.908878                       # average ReadExReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62097.232927                       # average overall mshr miss latency
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+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21598.571767                       # average WriteInvalidateReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.754287                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.761269                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        60000                       # average SCUpgradeReq mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577                       # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::total 61930.149616                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61635.604128                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61909.009377                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61561.742816                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61919.698834                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61930.149616                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -1755,57 +1997,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              417721                       # Transaction distribution
-system.membus.trans_dist::ReadResp             417721                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33871                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33871                       # Transaction distribution
-system.membus.trans_dist::Writeback           1069486                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq       600721                       # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp       600721                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34423                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34424                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            397977                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           397977                       # Transaction distribution
+system.membus.trans_dist::ReadReq              431429                       # Transaction distribution
+system.membus.trans_dist::ReadResp             431429                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33873                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33873                       # Transaction distribution
+system.membus.trans_dist::Writeback           1122241                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq       608883                       # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp       608883                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35220                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35222                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            436846                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           436846                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3570318                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3700502                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       334782                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       334782                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4035284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6948                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3746179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3876375                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       334941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       334941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4211316                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    140106848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    140277172                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14030080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total     14030080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               154307252                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3630                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2443419                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    147371488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    147541836                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14041536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total     14041536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               161583372                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3431                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2557707                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2443419    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2557707    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2443419                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107392500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2557707                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           107352000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5575997                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5560499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         16318205493                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         16960886493                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7697194309                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8211852015                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          186789727                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          186625462                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -1849,55 +2091,55 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq           21137473                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          21129474                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33871                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33871                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          7479557                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq      1332565                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp      1225901                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           43231                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          43232                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2014651                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2014651                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     27041508                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27036574                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       774452                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1144323                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              55996857                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    862740756                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1097639072                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2601008                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3569856                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             1966550692                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          492520                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         31930568                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            5.003619                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.060051                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq           21612149                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          21604161                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33873                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33873                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          7621991                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq      1335253                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp      1228589                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           44226                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          44228                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2062852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2062852                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     27641812                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27580079                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       784917                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1183820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              57190628                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    881950484                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1119524728                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2643752                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3719680                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2007838644                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          494311                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         32599559                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            5.003544                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.059428                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5               31815006     99.64%     99.64% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                 115562      0.36%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5               32484017     99.65%     99.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                 115542      0.35%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           31930568                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        50801737999                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           32599559                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        51716744749                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          4033500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          3993000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       60715950506                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       62067119757                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       38798201181                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       39696027226                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         449711000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         454863250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         698488000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         719296500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index d01497065..0f19127f8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.125918                       # Number of seconds simulated
-sim_ticks                                5125917808500                       # Number of ticks simulated
-final_tick                               5125917808500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.125948                       # Number of seconds simulated
+sim_ticks                                5125948496500                       # Number of ticks simulated
+final_tick                               5125948496500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 163224                       # Simulator instruction rate (inst/s)
-host_op_rate                                   322646                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2051147218                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 753920                       # Number of bytes of host memory used
-host_seconds                                  2499.05                       # Real time elapsed on the host
-sim_insts                                   407905794                       # Number of instructions simulated
-sim_ops                                     806307064                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 181287                       # Simulator instruction rate (inst/s)
+host_op_rate                                   358347                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2277524092                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 808864                       # Number of bytes of host memory used
+host_seconds                                  2250.67                       # Real time elapsed on the host
+sim_insts                                   408017153                       # Number of instructions simulated
+sim_ops                                     806519171                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4160                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1044736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10779456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1048640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10814912                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11857920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1044736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1044736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9592896                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9592896                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           78                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11896448                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1048640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1048640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9598912                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9598912                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           65                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16324                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             168429                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16385                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168983                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                185280                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149889                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149889                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            974                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                185882                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149983                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149983                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            812                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               203814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2102932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               204575                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2109836                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2313326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203814                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203814                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1871449                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1871449                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1871449                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           974                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 2320829                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          204575                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             204575                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1872612                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1872612                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1872612                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           812                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2102932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              204575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2109836                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5531                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4184776                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        185280                       # Number of read requests accepted
-system.physmem.writeReqs                       196609                       # Number of write requests accepted
-system.physmem.readBursts                      185280                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     196609                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11848512                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  12427072                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11857920                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               12582976                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2411                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1705                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11356                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10792                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11765                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11427                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11775                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11293                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11205                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11692                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11087                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11285                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11605                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12031                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11880                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12674                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11994                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11272                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               13000                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               12435                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               11147                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               11517                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               12452                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               12346                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               11719                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               11239                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               12215                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               12097                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              12764                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              12134                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              12379                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              12264                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              12219                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              12246                       # Per bank write bursts
+system.physmem.bw_total::total                4193440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185882                       # Number of read requests accepted
+system.physmem.writeReqs                       196703                       # Number of write requests accepted
+system.physmem.readBursts                      185882                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     196703                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11884864                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  12459008                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11896448                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               12588992                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      181                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2006                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           1725                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11442                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11010                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11990                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11673                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12100                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11243                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11527                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11544                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11275                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11901                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11758                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11788                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11617                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12244                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11799                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10790                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               14290                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               13466                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               12356                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               11306                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               11781                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               11472                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               11444                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               11849                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               11105                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               11337                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              12902                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              12297                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              12359                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              12104                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              12504                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              12100                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5125917756500                       # Total gap between requests
+system.physmem.totGap                    5125948445000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  185280                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185882                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 196609                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    170576                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11800                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2009                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       409                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 196703                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170938                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2076                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       389                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,435 +156,440 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     9692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    11040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    11520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    12479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    12952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    14075                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    13662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    14219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    13150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    12683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    11195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    10547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     4995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     9658                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::20                    12525                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::23                    13789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    14358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    13266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    12891                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::29                     9007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8656                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::34                      406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      371                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        74985                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      323.738348                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     187.730188                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.091209                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          27875     37.17%     37.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17344     23.13%     60.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7346      9.80%     70.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4205      5.61%     75.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3044      4.06%     79.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1991      2.66%     82.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1466      1.96%     84.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1106      1.47%     85.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        10608     14.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          74985                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7802                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.727634                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      544.765031                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7801     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        75254                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      323.488559                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     187.903299                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     341.428888                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          27891     37.06%     37.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17298     22.99%     60.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7596     10.09%     70.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4208      5.59%     75.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3159      4.20%     79.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2000      2.66%     82.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1345      1.79%     84.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1163      1.55%     85.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10594     14.08%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          75254                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7808                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.780866                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      544.702276                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7807     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7802                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7802                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        24.887593                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.377135                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       24.103132                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6364     81.57%     81.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              53      0.68%     82.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              22      0.28%     82.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             275      3.52%     86.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             179      2.29%     88.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              53      0.68%     89.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              27      0.35%     89.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              51      0.65%     90.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             164      2.10%     92.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              17      0.22%     92.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              13      0.17%     92.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.18%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              32      0.41%     93.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              25      0.32%     93.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.09%     93.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              50      0.64%     94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             101      1.29%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.04%     95.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               9      0.12%     95.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95              29      0.37%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99             150      1.92%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             8      0.10%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             7      0.09%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.04%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            28      0.36%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             4      0.05%     98.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            11      0.14%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.05%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            23      0.29%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             7      0.09%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.04%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            14      0.18%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151            10      0.13%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             9      0.12%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             4      0.05%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.01%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             2      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.01%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             3      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7802                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2011030750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5482274500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    925665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10862.63                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7808                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        24.932377                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.361157                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       24.539970                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6379     81.70%     81.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              49      0.63%     82.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27               9      0.12%     82.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             259      3.32%     85.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             187      2.39%     88.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              53      0.68%     88.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              34      0.44%     89.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              61      0.78%     90.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             178      2.28%     92.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              19      0.24%     92.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              13      0.17%     92.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.18%     92.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              27      0.35%     93.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              19      0.24%     93.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.08%     93.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              50      0.64%     94.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              97      1.24%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               8      0.10%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     95.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              20      0.26%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             156      2.00%     97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             7      0.09%     97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            10      0.13%     98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            29      0.37%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     98.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            11      0.14%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             4      0.05%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            16      0.20%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            10      0.13%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             4      0.05%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             6      0.08%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.09%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151            11      0.14%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163            10      0.13%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.01%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             7      0.09%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             2      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.01%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             2      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             4      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7808                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1993300749                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5475194499                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    928505000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10733.93                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29612.63                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.42                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.45                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29483.93                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.43                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.38                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     151985                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    152335                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13422533.14                       # Average gap between requests
-system.physmem.pageHitRate                      80.23                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4919402035500                       # Time in different power states
-system.physmem.memoryStateTime::REF      171165540000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       35350129500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 274957200                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 291929400                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 150026250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 159286875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                712179000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                731850600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               621140400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               637100640                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          334799796240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          334799796240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          129444240060                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          129652397505                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2962001074500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2961818480250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3428003413650                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3428090841510                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.759392                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.776448                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                86891854                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86891854                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            902474                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80057154                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78172464                       # Number of BTB hits
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.04                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     152642                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    152476                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.31                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13398195.03                       # Average gap between requests
+system.physmem.pageHitRate                      80.21                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  279704880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  152616750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 721718400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                634806720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           334801830480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           129444104115                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2962019880750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3428054662095                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.765327                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4927513863750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    171166580000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27267949750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  289215360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  157806000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 726741600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                626667840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           334801830480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           129734124390                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2961765477000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3428101862670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.774535                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4927089550750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    171166580000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27689450500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                86963954                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86963954                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            905408                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80060833                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78220075                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.645819                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1556145                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             178539                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.700801                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1554669                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             179026                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449528542                       # number of cpu cycles simulated
+system.cpu.numCycles                        449722784                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27579139                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      429063602                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86891854                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79728609                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     417924990                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1892404                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     141641                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                49747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        210937                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       127048                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          749                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9185584                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                447344                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4767                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          446980453                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.894336                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.051866                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27725020                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429300438                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86963954                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79774744                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417978242                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1899598                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     143976                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                49214                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        212054                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       124897                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          365                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9198894                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                449574                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4910                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          447183567                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.894463                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051838                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                281454432     62.97%     62.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2285018      0.51%     63.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72162718     16.14%     79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1595292      0.36%     79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2151182      0.48%     80.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2328836      0.52%     80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1532887      0.34%     81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1872269      0.42%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81597819     18.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281562684     62.96%     62.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2296710      0.51%     63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72185404     16.14%     79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1608090      0.36%     79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2152491      0.48%     80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2328628      0.52%     80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1534045      0.34%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1900420      0.42%     81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81615095     18.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            446980453                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.193296                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.954475                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23006879                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             264875775                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150713064                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7438533                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 946202                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              838427175                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 946202                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25861517                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               223289477                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       13277674                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154607234                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              28998349                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834936902                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                476513                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12412504                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 177326                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               13726812                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           997336716                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1813473834                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114859292                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               146                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964283425                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 33053286                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             468997                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         473016                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  39075310                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17327574                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10191135                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1313699                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1076527                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  829405798                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1211413                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 824144334                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            238741                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23374016                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     36157635                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         155810                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     446980453                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.843804                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.418028                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            447183567                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193372                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.954589                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23075597                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264910108                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150816162                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7431901                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 949799                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              838865197                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 949799                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25926245                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               223342995                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13219671                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154710115                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29034742                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              835373495                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                478818                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12412845                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 182552                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               13765619                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           997850152                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1814454577                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1115386152                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               142                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964539686                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 33310464                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             468855                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         472576                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  39019315                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17353635                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10197147                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1310615                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1095058                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  829813890                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1210662                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 824509848                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            239912                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23585262                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     36379120                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         154680                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     447183567                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.843784                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418075                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           262751782     58.78%     58.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13860127      3.10%     61.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10088289      2.26%     64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6929216      1.55%     65.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74323701     16.63%     82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4464363      1.00%     83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72802131     16.29%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1196176      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              564668      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262867260     58.78%     58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13875410      3.10%     61.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10102524      2.26%     64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6917845      1.55%     65.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74366987     16.63%     82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4460507      1.00%     83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72819289     16.28%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1200322      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              573423      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       446980453                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       447183567                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1984017     71.87%     71.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    212      0.01%     71.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                    1649      0.06%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 613790     22.24%     94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160788      5.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1986412     71.97%     71.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    252      0.01%     71.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                    1233      0.04%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 612541     22.19%     94.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159591      5.78%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            292283      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795766200     96.56%     96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150572      0.02%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                125282      0.02%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   8      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18411850      2.23%     98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9398139      1.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            292966      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             796097417     96.55%     96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150721      0.02%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125468      0.02%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18437939      2.24%     98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9405337      1.14%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              824144334                       # Type of FU issued
-system.cpu.iq.rate                           1.833353                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2760456                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003349                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2098268090                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         854003641                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819590055                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 227                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                270                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              824509848                       # Type of FU issued
+system.cpu.iq.rate                           1.833374                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2760029                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003347                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2099202980                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         854622338                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819935754                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 223                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                238                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           62                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826612402                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     105                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1877597                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              826976810                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1879265                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3329866                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14364                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14470                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1763076                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3349902                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15405                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14537                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1763571                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2224552                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         71468                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2224753                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         72078                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 946202                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               205595274                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9411486                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830617211                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            184433                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17327584                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10191135                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             714161                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 416193                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8093117                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14470                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         516905                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       536436                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1053341                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822534076                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              18016449                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1476395                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 949799                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               205606066                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9444034                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           831024552                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            186671                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17353635                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10197147                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             713788                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 414805                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8129418                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14537                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         518368                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       539118                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1057486                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822883825                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              18037381                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1492626                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27187129                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83286990                       # Number of branches executed
-system.cpu.iew.exec_stores                    9170680                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.829771                       # Inst execution rate
-system.cpu.iew.wb_sent                      822027813                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819590117                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640953314                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1050450596                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27216272                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83330623                       # Number of branches executed
+system.cpu.iew.exec_stores                    9178891                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.829758                       # Inst execution rate
+system.cpu.iew.wb_sent                      822374066                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819935816                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 641195588                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1050795800                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.823222                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610170                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.823203                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610200                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        24215626                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1055602                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            914308                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443339838                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.818711                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.675515                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        24410170                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1055982                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            917776                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443513895                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.818476                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.675053                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272569121     61.48%     61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11207092      2.53%     64.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3543073      0.80%     64.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74545535     16.81%     81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2433206      0.55%     82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1610406      0.36%     82.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       913346      0.21%     82.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71032181     16.02%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5485878      1.24%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272662791     61.48%     61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11205596      2.53%     64.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3584252      0.81%     64.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74566158     16.81%     81.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2433850      0.55%     82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1609395      0.36%     82.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       952580      0.21%     82.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71045442     16.02%     98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5453831      1.23%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443339838                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407905794                       # Number of instructions committed
-system.cpu.commit.committedOps              806307064                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443513895                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            408017153                       # Number of instructions committed
+system.cpu.commit.committedOps              806519171                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22425775                       # Number of memory references committed
-system.cpu.commit.loads                      13997716                       # Number of loads committed
-system.cpu.commit.membars                      475203                       # Number of memory barriers committed
-system.cpu.commit.branches                   82185787                       # Number of branches committed
+system.cpu.commit.refs                       22437308                       # Number of memory references committed
+system.cpu.commit.loads                      14003732                       # Number of loads committed
+system.cpu.commit.membars                      475345                       # Number of memory barriers committed
+system.cpu.commit.branches                   82208289                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735131032                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155610                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       174231      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783440615     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144913      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121530      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735327062                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1156001                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       174296      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783640915     97.16%     97.18% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          145051      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121601      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
@@ -611,167 +616,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13997716      1.74%     98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8428059      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        14003732      1.74%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8433576      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806307064                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5485878                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         806519171                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5453831                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1268298437                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1664703185                       # The number of ROB writes
-system.cpu.timesIdled                          295137                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2548089                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9802307300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407905794                       # Number of Instructions Simulated
-system.cpu.committedOps                     806307064                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.102040                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.102040                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907408                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907408                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1092406866                       # number of integer regfile reads
-system.cpu.int_regfile_writes               656005719                       # number of integer regfile writes
+system.cpu.rob.rob_reads                   1268911189                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1665544826                       # The number of ROB writes
+system.cpu.timesIdled                          297395                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2539217                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9802174458                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   408017153                       # Number of Instructions Simulated
+system.cpu.committedOps                     806519171                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.102215                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.102215                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907264                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907264                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1092796597                       # number of integer regfile reads
+system.cpu.int_regfile_writes               656284247                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        62                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416194474                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                322040205                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265569258                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402671                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1659070                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.990007                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19130419                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1659582                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.527251                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 416355955                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                322152728                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265715662                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402877                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1660514                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996956                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19150908                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1661026                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.529565                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.990007                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999980                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999980                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996956                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          203                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          291                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88317394                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88317394                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10978879                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10978879                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8084521                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8084521                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        64338                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         64338                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19063400                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19063400                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19127738                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19127738                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1796470                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1796470                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       333911                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       333911                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406328                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406328                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2130381                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2130381                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2536709                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2536709                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26526077953                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26526077953                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12856931699                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12856931699                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39383009652                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39383009652                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39383009652                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39383009652                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12775349                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12775349                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8418432                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8418432                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       470666                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       470666                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21193781                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21193781                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21664447                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21664447                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140620                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.140620                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039664                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039664                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863304                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.863304                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100519                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100519                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117091                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117091                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18486.369176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18486.369176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15525.237484                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15525.237484                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       375690                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88414778                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88414778                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10992291                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10992291                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8090245                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8090245                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        65628                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         65628                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19082536                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19082536                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19148164                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19148164                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1800200                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1800200                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       333674                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       333674                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406398                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406398                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2133874                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2133874                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2540272                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2540272                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26575138519                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26575138519                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12884484816                       # number of WriteReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total  39459623335                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12792491                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total     21688436                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140723                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.140723                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039610                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039610                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.860965                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.860965                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100577                       # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data     0.117126                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117126                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14762.325585                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14762.325585                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38613.990949                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38613.990949                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18492.011869                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18492.011869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15533.621335                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15533.621335                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       372367                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             39932                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             40008                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.408244                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.307314                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1560667                       # number of writebacks
-system.cpu.dcache.writebacks::total           1560667                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       827312                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       827312                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44114                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44114                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       871426                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       871426                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       871426                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       871426                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       969158                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       969158                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289797                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289797                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402869                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402869                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1258955                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1258955                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1661824                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1661824                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12253110515                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12253110515                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11193391556                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11193391556                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5590029250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5590029250                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23446502071                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23446502071                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29036531321                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29036531321                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97386643000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97386643000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2557063000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2557063000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99943706000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99943706000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075862                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075862                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034424                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034424                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855955                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855955                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.writebacks::writebacks      1561114                       # number of writebacks
+system.cpu.dcache.writebacks::total           1561114                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       829484                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       829484                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44098                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44098                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       873582                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       873582                       # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total       873582                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970716                       # number of ReadReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total       402937                       # number of SoftPFReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      1663229                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12259067013                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12259067013                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11217533642                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11217533642                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5591612757                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5591612757                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23476600655                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total  29068213412                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97390347000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97390347000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2564142000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2564142000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99954489000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99954489000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075882                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075882                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.853633                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.853633                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059402                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.059402                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076707                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076707                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076687                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076687                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12628.891471                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12628.891471                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38737.787807                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38737.787807                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.138999                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.138999                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18627.905799                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18627.905799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17476.976058                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17476.976058                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -779,58 +784,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        73854                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.812426                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       117340                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        73869                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.588488                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.812426                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988277                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988277                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        73235                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.785723                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       116281                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        73250                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.587454                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.785723                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986608                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986608                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       459584                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       459584                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       117385                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       117385                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       117385                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       117385                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       117385                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       117385                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74938                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        74938                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74938                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        74938                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74938                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        74938                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    912423463                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    912423463                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    912423463                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    912423463                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    912423463                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    912423463                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192323                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       192323                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192323                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       192323                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192323                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       192323                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.389647                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.389647                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.389647                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       455451                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       455451                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       116283                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       116283                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       116283                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       116283                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       116283                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       116283                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74295                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        74295                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74295                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        74295                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74295                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        74295                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    915742192                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    915742192                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    915742192                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    915742192                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    915742192                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    915742192                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       190578                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       190578                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       190578                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       190578                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       190578                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       190578                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.389840                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.389840                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.389840                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.389840                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.389840                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.389840                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12325.758019                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12325.758019                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12325.758019                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12325.758019                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12325.758019                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12325.758019                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -839,180 +844,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        19615                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        19615                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74938                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74938                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74938                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        74938                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74938                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        74938                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    762426693                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    762426693                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    762426693                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.389647                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.389647                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.389647                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10174.099829                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        20236                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        20236                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74295                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74295                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74295                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        74295                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74295                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        74295                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    767004478                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    767004478                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    767004478                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    767004478                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    767004478                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    767004478                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.389840                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.389840                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.389840                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.389840                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.389840                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.389840                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10323.769810                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10323.769810                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10323.769810                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            996223                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.034964                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8125334                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            996735                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.151950                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147627648000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.034964                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996162                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1000725                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.147155                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8133580                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1001237                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.123531                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147645528250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.147155                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996381                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996381                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10182364                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10182364                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8125334                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8125334                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8125334                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8125334                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8125334                       # number of overall hits
-system.cpu.icache.overall_hits::total         8125334                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1060246                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1060246                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1060246                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1060246                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1060246                       # number of overall misses
-system.cpu.icache.overall_misses::total       1060246                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14710988702                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14710988702                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14710988702                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14710988702                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14710988702                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14710988702                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9185580                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9185580                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9185580                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9185580                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9185580                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9185580                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115425                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.115425                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.115425                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.115425                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.115425                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.115425                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13875.071165                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13875.071165                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         8852                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10200177                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10200177                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8133580                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8133580                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8133580                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8133580                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8133580                       # number of overall hits
+system.cpu.icache.overall_hits::total         8133580                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1065313                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1065313                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1065313                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1065313                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1065313                       # number of overall misses
+system.cpu.icache.overall_misses::total       1065313                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14771324125                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14771324125                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14771324125                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14771324125                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14771324125                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14771324125                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9198893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9198893                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9198893                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9198893                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9198893                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9198893                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115809                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115809                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115809                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115809                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115809                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115809                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.712823                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13865.712823                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.712823                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13865.712823                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.712823                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13865.712823                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         6681                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               268                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.408638                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    24.929104                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63462                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        63462                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        63462                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        63462                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        63462                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        63462                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       996784                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       996784                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       996784                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       996784                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       996784                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       996784                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12075236643                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12075236643                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12075236643                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12075236643                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12075236643                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12075236643                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108516                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108516                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108516                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12114.195897                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        64029                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        64029                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        64029                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        64029                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        64029                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        64029                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1001284                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1001284                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1001284                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1001284                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1001284                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1001284                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12122903243                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12122903243                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12122903243                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12122903243                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12122903243                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12122903243                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108848                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108848                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108848                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108848                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108848                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108848                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12107.357396                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12107.357396                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12107.357396                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12107.357396                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12107.357396                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12107.357396                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        13757                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.017843                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        26179                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        13772                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.900886                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.017843                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376115                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.376115                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements        14176                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.015804                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26673                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        14191                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.879572                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5101167924000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.015804                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375988                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.375988                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        96280                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        96280                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26178                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26178                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        98532                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        98532                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26674                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        26674                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26180                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26180                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26180                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26180                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14640                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        14640                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14640                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        14640                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14640                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        14640                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    168910997                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    168910997                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    168910997                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    168910997                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    168910997                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    168910997                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40818                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        40818                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26676                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        26676                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26676                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        26676                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        15060                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        15060                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        15060                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        15060                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        15060                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        15060                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    174774993                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    174774993                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    174774993                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    174774993                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    174774993                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    174774993                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41734                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        41734                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40820                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        40820                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40820                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        40820                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358665                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358665                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358648                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.358648                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358648                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.358648                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11537.636407                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41736                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        41736                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41736                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        41736                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.360857                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.360857                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.360840                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.360840                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.360840                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.360840                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11605.245219                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11605.245219                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11605.245219                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11605.245219                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11605.245219                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11605.245219                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1021,177 +1026,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3000                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3000                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14640                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14640                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14640                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        14640                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14640                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        14640                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    139618019                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    139618019                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    139618019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    139618019                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    139618019                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    139618019                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358665                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358665                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358648                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358648                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9536.749932                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
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+system.cpu.itb_walker_cache.writebacks::total         2894                       # number of writebacks
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+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.360857                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.360857                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.360840                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.360840                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.360840                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.360840                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9603.787052                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9603.787052                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9603.787052                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9603.787052                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9603.787052                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9603.787052                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           113048                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64817.930454                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3838289                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           177093                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.673861                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           113005                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64819.841328                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3843950                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           177067                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.709014                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50426.330308                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    22.730844                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.138507                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3266.844648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.769445                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000347                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50385.421591                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    17.865695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.131540                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3266.822655                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11149.599847                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049848                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.169401                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          604                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3317                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5815                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977249                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         35033990                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        35033990                       # Number of data accesses
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-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12092                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        2394965                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1583282                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1583282                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          318                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          318                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       154206                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           78                       # number of ReadReq misses
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3385                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977509                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_accesses::total      1583282                       # number of Writeback accesses(hits+misses)
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1200,99 +1205,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103222                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103222                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819113                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464004                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464004                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102099                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067931                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102099                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067931                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67021.734201                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66081.951717                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10672.514583                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10672.514583                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57252.964800                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57252.964800                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59738.139997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59738.139997                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16385                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169928                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       186384                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5296500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       407000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1043304250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2392591752                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3441599502                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15547443                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15547443                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7667598282                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7667598282                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5296500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       407000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1043304250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10060190034                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11109197784                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5296500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       407000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1043304250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10060190034                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11109197784                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89275614000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89275614000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2397124500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2397124500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91672738500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91672738500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000958                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000478                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026117                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.831154                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.831154                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.466352                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.466352                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000958                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000478                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102338                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067972                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000958                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000478                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102338                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067972                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67833.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63674.351541                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66724.071393                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65787.351416                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.365937                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.365937                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57191.006802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57191.006802                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63674.351541                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59202.662504                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59603.816765                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67833.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63674.351541                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59202.662504                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59603.816765                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1300,63 +1305,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        3068576                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3068035                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1583282                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        3074514                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3073974                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1584244                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2219                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2219                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1993478                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6130100                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29738                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       161735                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8315051                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63788416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207873825                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       966272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5555008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          278183521                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       59487                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4379111                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.010877                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103722                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2203                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2203                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2002463                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6133560                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        30509                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       162399                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8328931                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64075456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207996475                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       988736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5638656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278699323                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       58087                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4385762                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.010862                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103651                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4331481     98.91%     98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47630      1.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            4338126     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47636      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4379111                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4067623882                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4385762                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4071958893                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       571500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       573000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1499268850                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1506070002                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3141964932                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3144166318                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      21966489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      22600980                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     112467385                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     111516357                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               225657                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225657                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57676                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              10956                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               225687                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225687                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57721                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              11001                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1641                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1641                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
@@ -1372,15 +1377,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       471406                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3282                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3282                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  569948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       471544                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95272                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95272                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  570104                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
@@ -1396,19 +1401,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       241980                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6564                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3276368                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3911656                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       242058                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027872                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027872                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3276506                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3917656                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1438,54 +1443,54 @@ system.iobus.reqLayer17.occupancy                9000                       # La
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           448438152                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           448361200                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           460450000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           460543000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52358513                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52371753                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1641000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1644000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47575                       # number of replacements
-system.iocache.tags.tagsinuse                0.091509                       # Cycle average of tags in use
+system.iocache.tags.replacements                47581                       # number of replacements
+system.iocache.tags.tagsinuse                0.091546                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47597                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992976927000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091509                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005719                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005719                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992992715000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091546                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005722                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005722                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
-system.iocache.tags.data_accesses              428670                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428724                       # Number of tag accesses
+system.iocache.tags.data_accesses              428724                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          916                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              916                       # number of ReadReq misses
 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          910                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               910                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          910                       # number of overall misses
-system.iocache.overall_misses::total              910                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151600663                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    151600663                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12348426976                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total  12348426976                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    151600663                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    151600663                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    151600663                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    151600663                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          916                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               916                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          916                       # number of overall misses
+system.iocache.overall_misses::total              916                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149161446                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    149161446                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12345702001                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total  12345702001                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    149161446                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    149161446                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    149161446                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    149161446                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          916                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            916                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          910                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             910                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          910                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            910                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          916                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             916                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          916                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            916                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
@@ -1494,40 +1499,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 166594.135165                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 166594.135165                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 166594.135165                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         70653                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 162840.006550                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 162840.006550                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 162840.006550                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         70237                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 9154                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 9120                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.718265                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.701425                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          916                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          916                       # number of ReadReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
 system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          910                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          910                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          910                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    104259663                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    104259663                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    104259663                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          916                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          916                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          916                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          916                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101504946                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    101504946                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9916256007                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9916256007                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    101504946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    101504946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    101504946                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    101504946                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -1536,79 +1541,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 110813.259825                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 110813.259825                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              662598                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662586                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13841                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13841                       # Transaction distribution
-system.membus.trans_dist::Writeback            149889                       # Transaction distribution
+system.membus.trans_dist::ReadReq              662646                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662640                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13889                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13889                       # Transaction distribution
+system.membus.trans_dist::Writeback            149983                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2184                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1723                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133213                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133211                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1641                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1641                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3282                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3282                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471406                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775060                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723935                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141460                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141460                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1868677                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550117                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18435776                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20227873                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq             2187                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1743                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133791                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133789                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       478766                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1725388                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1870142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242058                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550129                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18480320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20272507                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                26239557                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1606                       # Total snoops (count)
-system.membus.snoop_fanout::samples            385212                       # Request fanout histogram
+system.membus.pkt_size::total                26284203                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1595                       # Total snoops (count)
+system.membus.snoop_fanout::samples            385911                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  385212    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  385911    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              385212                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           251510000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              385911                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           251714500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583228000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583067000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3282000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3288000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1995467500                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1996777999                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               16000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1641000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1644000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3158524545                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3163999272                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           54933487                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54979247                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index b728ac0c9..92c4535bc 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.300742                       # Number of seconds simulated
-sim_ticks                                5300741898500                       # Number of ticks simulated
-final_tick                               5300741898500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.305804                       # Number of seconds simulated
+sim_ticks                                5305803886500                       # Number of ticks simulated
+final_tick                               5305803886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 268181                       # Simulator instruction rate (inst/s)
-host_op_rate                                   514172                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13311463323                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 800056                       # Number of bytes of host memory used
-host_seconds                                   398.21                       # Real time elapsed on the host
-sim_insts                                   106792132                       # Number of instructions simulated
-sim_ops                                     204747982                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 199055                       # Simulator instruction rate (inst/s)
+host_op_rate                                   381625                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9885187347                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 854320                       # Number of bytes of host memory used
+host_seconds                                   536.74                       # Real time elapsed on the host
+sim_insts                                   106841423                       # Number of instructions simulated
+sim_ops                                     204834575                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11447360                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           11447360                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9142976                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total         9142976                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       178865                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              178865                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       142859                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             142859                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0      2159577                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total               2159577                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0      1724848                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total              1724848                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0      3884425                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total              3884425                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      178865                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     142859                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    178865                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   142859                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               11390720                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   56640                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                 9134848                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                11447360                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys              9142976                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    885                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                   106                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11434048                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           11434048                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9128256                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total         9128256                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       178657                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              178657                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       142629                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             142629                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0      2155008                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total               2155008                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0      1720428                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total              1720428                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0      3875436                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total              3875436                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      178657                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     142629                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    178657                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   142629                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               11379712                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   54336                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                 9119680                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                11434048                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys              9128256                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    849                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                   104                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             11083                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             10466                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             10673                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             10751                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             11479                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             11934                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             10746                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             10510                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8             10984                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9             10978                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10            10728                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11            13966                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12            10998                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13            10695                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14            11146                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15            10843                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0              9192                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1              8887                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2              8721                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3              8884                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4              9584                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5              9646                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6              8803                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7              8544                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8              8749                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9              8837                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10             8942                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11             8982                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12             8616                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13             8535                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14             8942                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15             8868                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             10773                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             10609                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             10875                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             11019                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             11847                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             12404                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             11308                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             10254                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8             10790                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9             10382                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10            10431                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11            13895                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12            11043                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13            10450                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14            11056                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15            10672                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0              8646                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1              8740                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2              8909                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3              9072                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4              9699                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5              9645                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6              8889                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7              8365                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8              8684                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9              8653                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10             8512                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11             9107                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12             8716                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13             8645                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14             9206                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15             9007                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                  5300741764000                       # Total gap between requests
+system.mem_ctrls.totGap                  5305803752000                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                178865                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                178657                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               142859                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                  177944                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                      36                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               142629                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                  177742                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                      66                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -135,38 +135,38 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                   2042                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                   2762                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                   8528                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   9126                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   8582                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                   9159                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                   9214                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                   8343                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                   9016                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                   9104                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                   8438                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                   8502                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                   8352                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                   8474                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                   8065                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                   8107                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                   8180                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                   7958                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                    136                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    116                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                    100                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                     96                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                     84                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                     72                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                     61                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                     49                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                     32                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                     21                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                     11                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                   2048                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                   2805                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                   8516                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   9095                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   8606                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                   9164                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                   9192                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                   8373                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                   9017                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                   9032                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                   8415                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                   8498                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                   8325                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                   8422                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                   8038                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                   8077                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                   8151                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                   7943                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                    129                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                    121                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    110                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                     90                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                     88                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                     71                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                     56                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                     51                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                     36                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                     23                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                     13                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::44                      5                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
@@ -184,74 +184,73 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples        60353                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    340.090865                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   200.552614                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   345.449556                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        20341     33.70%     33.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        14451     23.94%     57.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383         6322     10.48%     68.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511         3381      5.60%     73.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639         2729      4.52%     78.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         1822      3.02%     81.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         1379      2.28%     83.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023         1383      2.29%     85.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151         8545     14.16%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total        60353                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples         7902                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      22.522399                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev    318.068462                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023         7896     99.92%     99.92% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples        60600                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    338.272739                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   199.847297                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   343.861949                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        20364     33.60%     33.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        14670     24.21%     57.81% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383         6315     10.42%     68.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511         3448      5.69%     73.92% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639         2734      4.51%     78.43% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         1855      3.06%     81.50% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         1401      2.31%     83.81% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023         1433      2.36%     86.17% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151         8380     13.83%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total        60600                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples         7887                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      22.539115                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev    318.374099                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-1023         7881     99.92%     99.92% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::1024-2047            2      0.03%     99.95% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::2048-3071            2      0.03%     99.97% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total          7902                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples         7902                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      18.062769                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.701265                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      4.160598                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16             5817     73.61%     73.61% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17                9      0.11%     73.73% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18              164      2.08%     75.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19               13      0.16%     75.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20               44      0.56%     76.52% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21              510      6.45%     82.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22              151      1.91%     84.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23               32      0.40%     85.29% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24              635      8.04%     93.33% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25              115      1.46%     94.79% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26                6      0.08%     94.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27               14      0.18%     95.04% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28              297      3.76%     98.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29                8      0.10%     98.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30                4      0.05%     98.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31                6      0.08%     99.03% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32                6      0.08%     99.10% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33                6      0.08%     99.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34                2      0.03%     99.20% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35                4      0.05%     99.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36                1      0.01%     99.27% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37                1      0.01%     99.28% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::38                5      0.06%     99.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::39                3      0.04%     99.38% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40                6      0.08%     99.46% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41                9      0.11%     99.57% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42                6      0.08%     99.65% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43                4      0.05%     99.70% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44                5      0.06%     99.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45                3      0.04%     99.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::46                2      0.03%     99.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48                5      0.06%     99.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::51                9      0.11%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total          7902                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                   1958460749                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat              5295585749                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                  889900000                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                     11003.82                       # Average queueing delay per DRAM burst
+system.mem_ctrls.rdPerTurnAround::total          7887                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples         7887                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      18.067072                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     17.711824                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      4.086646                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16             5792     73.44%     73.44% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17               14      0.18%     73.61% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18              155      1.97%     75.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19               18      0.23%     75.81% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20               48      0.61%     76.42% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21              474      6.01%     82.43% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22              162      2.05%     84.48% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23               48      0.61%     85.09% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24              632      8.01%     93.10% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25              129      1.64%     94.74% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26               11      0.14%     94.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27               12      0.15%     95.03% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28              299      3.79%     98.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29                7      0.09%     98.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30                7      0.09%     99.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::31                8      0.10%     99.10% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32                7      0.09%     99.19% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::33                5      0.06%     99.25% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::34                6      0.08%     99.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::35                3      0.04%     99.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::36                1      0.01%     99.38% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::37                4      0.05%     99.43% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::38                1      0.01%     99.44% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::39                3      0.04%     99.48% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::40               11      0.14%     99.62% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::41                6      0.08%     99.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::42                3      0.04%     99.73% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::43                1      0.01%     99.75% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::44                8      0.10%     99.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::45                2      0.03%     99.87% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::48                3      0.04%     99.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::51                7      0.09%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total          7887                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                   1946379497                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat              5280279497                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                  889040000                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                     10946.52                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                29753.82                       # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW                         2.15                       # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat                29696.52                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW                         2.14                       # Average DRAM read bandwidth in MiByte/s
 system.mem_ctrls.avgWrBW                         1.72                       # Average achieved write bandwidth in MiByte/s
 system.mem_ctrls.avgRdBWSys                      2.16                       # Average system read bandwidth in MiByte/s
 system.mem_ctrls.avgWrBWSys                      1.72                       # Average system write bandwidth in MiByte/s
@@ -260,270 +259,275 @@ system.mem_ctrls.busUtil                         0.03                       # Da
 system.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      27.88                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   142054                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  118304                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 79.81                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                82.87                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                   16476053.28                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    81.18                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE   5045112796500                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF    177003320000                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT     78625657500                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0               223791120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1               232477560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0               122108250                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1               126847875                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0              683599800                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1              704636400                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0             468251280                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1             456652080                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0        346218493920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1        346218493920                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0        148888594485                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1        149563929060                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0        3049839426000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1        3049247027250                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0          3546444264855                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1          3546550064145                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           669.047128                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           669.067087                       # Core power per rank (mW)
+system.mem_ctrls.avgWrQLen                      25.29                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   141783                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  117919                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 79.74                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                82.74                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                   16514270.00                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.07                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                229566960                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                125259750                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy               694894200                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy              466333200                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         346549057920                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy         149180699250                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy         3052619831250                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy           3549865642530                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            669.053779                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5078135564501                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF  177172320000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT   50492285499                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                228569040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                124715250                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy               692000400                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy              457034400                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         346549057920                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy         149006937600                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy         3052772253750                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy           3549830568360                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            669.047168                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5078398943499                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF  177172320000                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT   50232498501                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                     10600620667                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10611607773                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   58326751                       # Number of instructions committed
-system.cpu0.committedOps                    112208544                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            105142610                       # Number of integer alu accesses
+system.cpu0.committedInsts                   58312369                       # Number of instructions committed
+system.cpu0.committedOps                    112077158                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            105052932                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     999393                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      9968022                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   105142610                       # number of integer instructions
+system.cpu0.num_func_calls                     985826                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      9959513                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   105052932                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          198014063                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          89363011                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          198024346                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          89262745                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            60260543                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           43624365                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     12030075                       # number of memory refs
-system.cpu0.num_load_insts                    7288332                       # Number of load instructions
-system.cpu0.num_store_insts                   4741743                       # Number of store instructions
-system.cpu0.num_idle_cycles              10084773874.270475                       # Number of idle cycles
-system.cpu0.num_busy_cycles              515846792.729524                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.048662                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.951338                       # Percentage of idle cycles
-system.cpu0.Branches                         11302630                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass               132692      0.12%      0.12% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 99906926     89.04%     89.15% # Class of executed instruction
-system.cpu0.op_class::IntMult                   87661      0.08%     89.23% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    51849      0.05%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.28% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7288332      6.50%     95.77% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4741743      4.23%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            60301130                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           43624803                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     12143482                       # number of memory refs
+system.cpu0.num_load_insts                    7354533                       # Number of load instructions
+system.cpu0.num_store_insts                   4788949                       # Number of store instructions
+system.cpu0.num_idle_cycles              10094720432.678099                       # Number of idle cycles
+system.cpu0.num_busy_cycles              516887340.321903                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.048710                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.951290                       # Percentage of idle cycles
+system.cpu0.Branches                         11277737                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               133660      0.12%      0.12% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 99659673     88.92%     89.04% # Class of executed instruction
+system.cpu0.op_class::IntMult                   84103      0.08%     89.11% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    57076      0.05%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.17% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7354533      6.56%     95.73% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4788949      4.27%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 112209203                       # Class of executed instruction
+system.cpu0.op_class::total                 112077994                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu1.numCycles                     10601483797                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10608678164                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48465381                       # Number of instructions committed
-system.cpu1.committedOps                     92539438                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             88910462                       # Number of integer alu accesses
+system.cpu1.committedInsts                   48529054                       # Number of instructions committed
+system.cpu1.committedOps                     92757417                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             89083939                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1744945                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8275238                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    88910462                       # number of integer instructions
+system.cpu1.num_func_calls                    1759211                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      8292881                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    89083939                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          172623141                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          73500216                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          172769101                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          73668949                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            51257305                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           33029139                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     14403882                       # number of memory refs
-system.cpu1.num_load_insts                    9271822                       # Number of load instructions
-system.cpu1.num_store_insts                   5132060                       # Number of store instructions
-system.cpu1.num_idle_cycles              10262330670.974064                       # Number of idle cycles
-system.cpu1.num_busy_cycles              339153126.025936                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031991                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968009                       # Percentage of idle cycles
-system.cpu1.Branches                         10623766                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               173936      0.19%      0.19% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 77788975     84.06%     84.25% # Class of executed instruction
-system.cpu1.op_class::IntMult                   96916      0.10%     84.35% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    76680      0.08%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.44% # Class of executed instruction
-system.cpu1.op_class::MemRead                 9271822     10.02%     94.45% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5132060      5.55%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            51289512                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           33065409                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     14308473                       # number of memory refs
+system.cpu1.num_load_insts                    9217545                       # Number of load instructions
+system.cpu1.num_store_insts                   5090928                       # Number of store instructions
+system.cpu1.num_idle_cycles              10270312186.995054                       # Number of idle cycles
+system.cpu1.num_busy_cycles              338365977.004946                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031895                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968105                       # Percentage of idle cycles
+system.cpu1.Branches                         10658677                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               173276      0.19%      0.19% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 78104057     84.20%     84.39% # Class of executed instruction
+system.cpu1.op_class::IntMult                  100669      0.11%     84.50% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    71662      0.08%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.57% # Class of executed instruction
+system.cpu1.op_class::MemRead                 9217545      9.94%     94.51% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5090928      5.49%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  92540389                       # Class of executed instruction
+system.cpu1.op_class::total                  92758137                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq               857926                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              857926                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               36569                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              36569                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1919                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1919                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               857916                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              857916                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               36558                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              36558                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1920                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1920                       # Transaction distribution
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1700                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1642                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3342                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1644                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3344                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4780                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5802                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio         1048                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           82                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           42                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          964                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          990                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          966                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        16892                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743276                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          296                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14942                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743192                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          238                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1704360                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1703174                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5240                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          316                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          400                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        31164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          364                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          348                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31252                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        10236                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12178                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          200                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5148                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        85126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 1792828                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          258                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5238                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        86270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 1792788                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3400                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3284                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6684                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3288                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6688                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2696                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3294                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          524                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           41                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           21                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          482                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1980                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1932                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         8446                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486546                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          592                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7471                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486378                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          476                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1972617                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1971862                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3964                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3366                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          158                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          200                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15582                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          728                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          696                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15626                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         5118                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6089                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          400                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10293                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        51987                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2031288                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy                51000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          516                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10473                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        52670                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2031220                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy                50000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 7500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy             10161500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy             10107000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               144000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               145000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy              1080000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy              1059500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                94000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                96000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                59500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                55000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy             20808000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy             28599000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy            700937500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy              1385500                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1327000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy            31365000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy            39157000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer12.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            23203000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            23099500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -531,19 +535,19 @@ system.iobus.reqLayer15.occupancy                9000                       # La
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           469007612                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           469010624                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             8240496                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             8240920                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy             1330000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             2404108                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             2415044                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy          2025089500                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy          2023919000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy            59993000                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy            76513000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
@@ -560,48 +564,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.ruby.clk_domain.clock                      500                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples               10900696                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.442840                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.830682                       # delay histogram for all message
-system.ruby.delayHist                    |    10297724     94.47%     94.47% |        1479      0.01%     94.48% |      601064      5.51%    100.00% |         150      0.00%    100.00% |         222      0.00%    100.00% |          14      0.00%    100.00% |          41      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                 10900696                       # delay histogram for all message
+system.ruby.delayHist::samples               10911216                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.442136                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.829254                       # delay histogram for all message
+system.ruby.delayHist                    |    10308626     94.48%     94.48% |        1272      0.01%     94.49% |      600907      5.51%    100.00% |         150      0.00%    100.00% |         203      0.00%    100.00% |          20      0.00%    100.00% |          38      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                 10911216                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples    152128630                      
+system.ruby.outstanding_req_hist::samples    152209035                      
 system.ruby.outstanding_req_hist::mean       1.000112                      
 system.ruby.outstanding_req_hist::gmean      1.000078                      
-system.ruby.outstanding_req_hist::stdev      0.010605                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152111520     99.99%     99.99% |       17110      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total     152128630                      
+system.ruby.outstanding_req_hist::stdev      0.010600                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152191931     99.99%     99.99% |       17104      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total     152209035                      
 system.ruby.latency_hist::bucket_size             256                      
 system.ruby.latency_hist::max_bucket             2559                      
-system.ruby.latency_hist::samples           152128629                      
-system.ruby.latency_hist::mean               3.436815                      
-system.ruby.latency_hist::gmean              3.107877                      
-system.ruby.latency_hist::stdev              5.781267                      
-system.ruby.latency_hist                 |   152119575     99.99%     99.99% |        6193      0.00%    100.00% |        2797      0.00%    100.00% |          28      0.00%    100.00% |          34      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total             152128629                      
+system.ruby.latency_hist::samples           152209034                      
+system.ruby.latency_hist::mean               3.436503                      
+system.ruby.latency_hist::gmean              3.107893                      
+system.ruby.latency_hist::stdev              5.762527                      
+system.ruby.latency_hist                 |   152200028     99.99%     99.99% |        6260      0.00%    100.00% |        2677      0.00%    100.00% |          43      0.00%    100.00% |          25      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total             152209034                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples       149464039                      
+system.ruby.hit_latency_hist::samples       149542283                      
 system.ruby.hit_latency_hist::mean                  3                      
 system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   149464039    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total         149464039                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   149542283    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total         149542283                      
 system.ruby.miss_latency_hist::bucket_size          256                      
 system.ruby.miss_latency_hist::max_bucket         2559                      
-system.ruby.miss_latency_hist::samples        2664590                      
-system.ruby.miss_latency_hist::mean         27.938944                      
-system.ruby.miss_latency_hist::gmean        22.546119                      
-system.ruby.miss_latency_hist::stdev        36.016044                      
-system.ruby.miss_latency_hist            |     2655536     99.66%     99.66% |        6193      0.23%     99.89% |        2797      0.10%    100.00% |          28      0.00%    100.00% |          34      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total          2664590                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits     10684802                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses       518536                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses     11203338                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits     67461431                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses       317291                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses     67778722                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples        2666751                      
+system.ruby.miss_latency_hist::mean         27.914090                      
+system.ruby.miss_latency_hist::gmean        22.539704                      
+system.ruby.miss_latency_hist::stdev        35.853723                      
+system.ruby.miss_latency_hist            |     2657745     99.66%     99.66% |        6260      0.23%     99.90% |        2677      0.10%    100.00% |          43      0.00%    100.00% |          25      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total          2666751                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits     10785659                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses       531574                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses     11317233                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits     67530179                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses       328872                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses     67859051                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -611,13 +615,13 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits     13058053                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses      1328322                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14386375                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits     58259753                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses       500441                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses     58760194                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles            15                       # cycles for which number of transistions == max transitions
+system.ruby.l1_cntrl1.L1Dcache.demand_hits     12972395                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses      1316773                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14289168                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits     58254050                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses       489532                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses     58743582                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -627,601 +631,613 @@ system.ruby.l1_cntrl1.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits      2436707                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       227883                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses      2664590                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.fully_busy_cycles            10                       # cycles for which number of transistions == max transitions
+system.ruby.l2_cntrl0.L2cache.demand_hits      2439158                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       227593                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses      2666751                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.fully_busy_cycles             1                       # cycles for which number of transistions == max transitions
 system.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     0.029331                      
-system.ruby.network.routers0.msg_count.Control::0       835827                      
-system.ruby.network.routers0.msg_count.Request_Control::2        42905                      
-system.ruby.network.routers0.msg_count.Response_Data::1       863889                      
-system.ruby.network.routers0.msg_count.Response_Control::1       496114                      
-system.ruby.network.routers0.msg_count.Response_Control::2       492544                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0       292440                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          167                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0       162044                      
-system.ruby.network.routers0.msg_bytes.Control::0      6686616                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       343240                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1     62200008                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1      3968912                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2      3940352                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0     21055680                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        12024                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1296352                      
-system.ruby.network.routers1.percent_links_utilized     0.057975                      
-system.ruby.network.routers1.msg_count.Control::0      1828763                      
-system.ruby.network.routers1.msg_count.Request_Control::2        40586                      
-system.ruby.network.routers1.msg_count.Response_Data::1      1853208                      
-system.ruby.network.routers1.msg_count.Response_Control::1      1269894                      
-system.ruby.network.routers1.msg_count.Response_Control::2      1269686                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0       282914                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          208                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0       948886                      
-system.ruby.network.routers1.msg_bytes.Control::0     14630104                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       324688                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1    133430976                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1     10159152                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2     10157488                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0     20369808                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        14976                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7591088                      
-system.ruby.network.routers2.percent_links_utilized     0.091680                      
-system.ruby.network.routers2.msg_count.Control::0      2843003                      
-system.ruby.network.routers2.msg_count.Request_Control::2        81677                      
-system.ruby.network.routers2.msg_count.Response_Data::1      2894271                      
-system.ruby.network.routers2.msg_count.Response_Control::1      1849723                      
-system.ruby.network.routers2.msg_count.Response_Control::2      1762230                      
-system.ruby.network.routers2.msg_count.Writeback_Data::0       575354                      
-system.ruby.network.routers2.msg_count.Writeback_Data::1          375                      
-system.ruby.network.routers2.msg_count.Writeback_Control::0      1110930                      
-system.ruby.network.routers2.msg_bytes.Control::0     22744024                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2       653416                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1    208387512                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1     14797784                      
-system.ruby.network.routers2.msg_bytes.Response_Control::2     14097840                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41425488                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1        27000                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8887440                      
-system.ruby.network.routers3.percent_links_utilized     0.006831                      
-system.ruby.network.routers3.msg_count.Control::0       178413                      
-system.ruby.network.routers3.msg_count.Response_Data::1       276928                      
-system.ruby.network.routers3.msg_count.Response_Control::1       131535                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0        47550                      
+system.ruby.network.routers0.percent_links_utilized     0.030084                      
+system.ruby.network.routers0.msg_count.Control::0       860446                      
+system.ruby.network.routers0.msg_count.Request_Control::2        42982                      
+system.ruby.network.routers0.msg_count.Response_Data::1       889304                      
+system.ruby.network.routers0.msg_count.Response_Control::1       509254                      
+system.ruby.network.routers0.msg_count.Response_Control::2       506406                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0       297072                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          216                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0       171015                      
+system.ruby.network.routers0.msg_bytes.Control::0      6883568                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2       343856                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1     64029888                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1      4074032                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2      4051248                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0     21389184                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        15552                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1368120                      
+system.ruby.network.routers1.percent_links_utilized     0.057201                      
+system.ruby.network.routers1.msg_count.Control::0      1806305                      
+system.ruby.network.routers1.msg_count.Request_Control::2        40219                      
+system.ruby.network.routers1.msg_count.Response_Data::1      1829948                      
+system.ruby.network.routers1.msg_count.Response_Control::1      1258997                      
+system.ruby.network.routers1.msg_count.Response_Control::2      1258038                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0       278052                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          186                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0       942391                      
+system.ruby.network.routers1.msg_bytes.Control::0     14450440                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2       321752                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1    131756256                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1     10071976                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2     10064304                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0     20019744                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        13392                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7539128                      
+system.ruby.network.routers2.percent_links_utilized     0.091652                      
+system.ruby.network.routers2.msg_count.Control::0      2844938                      
+system.ruby.network.routers2.msg_count.Request_Control::2        81574                      
+system.ruby.network.routers2.msg_count.Response_Data::1      2896372                      
+system.ruby.network.routers2.msg_count.Response_Control::1      1851517                      
+system.ruby.network.routers2.msg_count.Response_Control::2      1764444                      
+system.ruby.network.routers2.msg_count.Writeback_Data::0       575124                      
+system.ruby.network.routers2.msg_count.Writeback_Data::1          402                      
+system.ruby.network.routers2.msg_count.Writeback_Control::0      1113406                      
+system.ruby.network.routers2.msg_bytes.Control::0     22759504                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2       652592                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1    208538784                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1     14812136                      
+system.ruby.network.routers2.msg_bytes.Response_Control::2     14115552                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41408928                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1        28944                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8907248                      
+system.ruby.network.routers3.percent_links_utilized     0.006819                      
+system.ruby.network.routers3.msg_count.Control::0       178187                      
+system.ruby.network.routers3.msg_count.Response_Data::1       276747                      
+system.ruby.network.routers3.msg_count.Response_Control::1       131418                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0        47551                      
 system.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers3.msg_bytes.Control::0      1427304                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1     19938816                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1      1052280                      
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-system.ruby.network.routers6.throttle2.msg_count.Response_Control::1       125324                      
-system.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1762230                      
-system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       575354                      
-system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          375                      
-system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1110930                      
-system.ruby.network.routers6.throttle2.msg_bytes.Control::0     21316720                      
-system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14660496                      
-system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1      1002592                      
-system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14097840                      
-system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41425488                      
-system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        27000                      
-system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8887440                      
-system.ruby.network.routers6.throttle3.link_utilization     0.005288                      
-system.ruby.network.routers6.throttle3.msg_count.Control::0       178413                      
-system.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97701                      
-system.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15947                      
-system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47550                      
-system.ruby.network.routers6.throttle3.msg_bytes.Control::0      1427304                      
-system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7034472                      
-system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       127576                      
-system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380400                      
+system.ruby.network.routers6.throttle0.link_utilization     0.038501                      
+system.ruby.network.routers6.throttle0.msg_count.Request_Control::2        42982                      
+system.ruby.network.routers6.throttle0.msg_count.Response_Data::1       848348                      
+system.ruby.network.routers6.throttle0.msg_count.Response_Control::1       493076                      
+system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       343856                      
+system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1     61081056                      
+system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      3944608                      
+system.ruby.network.routers6.throttle1.link_utilization     0.082209                      
+system.ruby.network.routers6.throttle1.msg_count.Request_Control::2        40219                      
+system.ruby.network.routers6.throttle1.msg_count.Response_Data::1      1796151                      
+system.ruby.network.routers6.throttle1.msg_count.Response_Control::1      1241782                      
+system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       321752                      
+system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1    129322872                      
+system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      9934256                      
+system.ruby.network.routers6.throttle2.link_utilization     0.059751                      
+system.ruby.network.routers6.throttle2.msg_count.Control::0      2666751                      
+system.ruby.network.routers6.throttle2.msg_count.Response_Data::1       203534                      
+system.ruby.network.routers6.throttle2.msg_count.Response_Control::1       124997                      
+system.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1764444                      
+system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       575124                      
+system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          402                      
+system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1113406                      
+system.ruby.network.routers6.throttle2.msg_bytes.Control::0     21334008                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14654448                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1       999976                      
+system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14115552                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41408928                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        28944                      
+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8907248                      
+system.ruby.network.routers6.throttle3.link_utilization     0.005283                      
+system.ruby.network.routers6.throttle3.msg_count.Control::0       178187                      
+system.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97745                      
+system.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15738                      
+system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47551                      
+system.ruby.network.routers6.throttle3.msg_bytes.Control::0      1425496                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7037640                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       125904                      
+system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380408                      
 system.ruby.network.routers6.throttle4.link_utilization     0.000255                      
-system.ruby.network.routers6.throttle4.msg_count.Response_Data::1          814                      
+system.ruby.network.routers6.throttle4.msg_count.Response_Data::1          815                      
 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58608                      
+system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58680                      
 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers6.throttle5.link_utilization            0                      
 system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       6113104                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         0.754972                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        2.341149                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     5536836     90.57%     90.57% |         424      0.01%     90.58% |      575424      9.41%     99.99% |         146      0.00%    100.00% |         217      0.00%    100.00% |          14      0.00%    100.00% |          41      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         6113104                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       6119725                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         0.753707                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        2.339234                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     5543761     90.59%     90.59% |         388      0.01%     90.59% |      575170      9.40%     99.99% |         147      0.00%    100.00% |         201      0.00%    100.00% |          20      0.00%    100.00% |          38      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         6119725                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       4704101                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.045072                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.595912                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     4676918     99.42%     99.42% |         479      0.01%     99.43% |         405      0.01%     99.44% |         650      0.01%     99.45% |       25495      0.54%    100.00% |         145      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         4704101                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       4708290                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.044976                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.595659                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     4681222     99.43%     99.43% |         442      0.01%     99.43% |         339      0.01%     99.44% |         545      0.01%     99.45% |       25596      0.54%    100.00% |         141      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         4708290                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples         83491                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.000264                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.022955                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |       83480     99.99%     99.99% |           0      0.00%     99.99% |          11      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total           83491                       # delay histogram for vnet_2
-system.ruby.LD.latency_hist::bucket_size          256                      
-system.ruby.LD.latency_hist::max_bucket          2559                      
-system.ruby.LD.latency_hist::samples         14918164                      
-system.ruby.LD.latency_hist::mean            4.885826                      
-system.ruby.LD.latency_hist::gmean           3.596048                      
-system.ruby.LD.latency_hist::stdev           9.349489                      
-system.ruby.LD.latency_hist              |    14916026     99.99%     99.99% |        1637      0.01%    100.00% |         485      0.00%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total           14918164                      
+system.ruby.delayVCHist.vnet_2::samples         83201                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.000120                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.015504                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |       83196     99.99%     99.99% |           0      0.00%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total           83201                       # delay histogram for vnet_2
+system.ruby.LD.latency_hist::bucket_size          128                      
+system.ruby.LD.latency_hist::max_bucket          1279                      
+system.ruby.LD.latency_hist::samples         14928118                      
+system.ruby.LD.latency_hist::mean            4.887199                      
+system.ruby.LD.latency_hist::gmean           3.596426                      
+system.ruby.LD.latency_hist::stdev           9.328249                      
+system.ruby.LD.latency_hist              |    14912021     99.89%     99.89% |       13966      0.09%     99.99% |         828      0.01%     99.99% |         820      0.01%    100.00% |         357      0.00%    100.00% |         111      0.00%    100.00% |           2      0.00%    100.00% |           8      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.LD.latency_hist::total           14928118                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples     13527451                      
+system.ruby.LD.hit_latency_hist::samples     13535758                      
 system.ruby.LD.hit_latency_hist::mean               3                      
 system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13527451    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total       13527451                      
-system.ruby.LD.miss_latency_hist::bucket_size          256                      
-system.ruby.LD.miss_latency_hist::max_bucket         2559                      
-system.ruby.LD.miss_latency_hist::samples      1390713                      
-system.ruby.LD.miss_latency_hist::mean      23.229241                      
-system.ruby.LD.miss_latency_hist::gmean     20.959487                      
-system.ruby.LD.miss_latency_hist::stdev     23.803463                      
-system.ruby.LD.miss_latency_hist         |     1388575     99.85%     99.85% |        1637      0.12%     99.96% |         485      0.03%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total       1390713                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13535758    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total       13535758                      
+system.ruby.LD.miss_latency_hist::bucket_size          128                      
+system.ruby.LD.miss_latency_hist::max_bucket         1279                      
+system.ruby.LD.miss_latency_hist::samples      1392360                      
+system.ruby.LD.miss_latency_hist::mean      23.233506                      
+system.ruby.LD.miss_latency_hist::gmean     20.962083                      
+system.ruby.LD.miss_latency_hist::stdev     23.700852                      
+system.ruby.LD.miss_latency_hist         |     1376263     98.84%     98.84% |       13966      1.00%     99.85% |         828      0.06%     99.91% |         820      0.06%     99.97% |         357      0.03%     99.99% |         111      0.01%    100.00% |           2      0.00%    100.00% |           8      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total       1392360                      
 system.ruby.ST.latency_hist::bucket_size          256                      
 system.ruby.ST.latency_hist::max_bucket          2559                      
-system.ruby.ST.latency_hist::samples          9498200                      
-system.ruby.ST.latency_hist::mean            5.193739                      
-system.ruby.ST.latency_hist::gmean           3.303046                      
-system.ruby.ST.latency_hist::stdev          17.710522                      
-system.ruby.ST.latency_hist              |     9492386     99.94%     99.94% |        3703      0.04%     99.98% |        2069      0.02%    100.00% |          12      0.00%    100.00% |          29      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total            9498200                      
+system.ruby.ST.latency_hist::samples          9504180                      
+system.ruby.ST.latency_hist::mean            5.187204                      
+system.ruby.ST.latency_hist::gmean           3.302390                      
+system.ruby.ST.latency_hist::stdev          17.665644                      
+system.ruby.ST.latency_hist              |     9498362     99.94%     99.94% |        3775      0.04%     99.98% |        1993      0.02%    100.00% |          29      0.00%    100.00% |          20      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.latency_hist::total            9504180                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples      9146403                      
+system.ruby.ST.hit_latency_hist::samples      9152723                      
 system.ruby.ST.hit_latency_hist::mean               3                      
 system.ruby.ST.hit_latency_hist::gmean       3.000000                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9146403    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total        9146403                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9152723    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total        9152723                      
 system.ruby.ST.miss_latency_hist::bucket_size          256                      
 system.ruby.ST.miss_latency_hist::max_bucket         2559                      
-system.ruby.ST.miss_latency_hist::samples       351797                      
-system.ruby.ST.miss_latency_hist::mean      62.228953                      
-system.ruby.ST.miss_latency_hist::gmean     40.318436                      
-system.ruby.ST.miss_latency_hist::stdev     71.347621                      
-system.ruby.ST.miss_latency_hist         |      345983     98.35%     98.35% |        3703      1.05%     99.40% |        2069      0.59%     99.99% |          12      0.00%     99.99% |          29      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        351797                      
+system.ruby.ST.miss_latency_hist::samples       351457                      
+system.ruby.ST.miss_latency_hist::mean      62.146880                      
+system.ruby.ST.miss_latency_hist::gmean     40.269218                      
+system.ruby.ST.miss_latency_hist::stdev     71.205537                      
+system.ruby.ST.miss_latency_hist         |      345639     98.34%     98.34% |        3775      1.07%     99.42% |        1993      0.57%     99.99% |          29      0.01%     99.99% |          20      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        351457                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
 system.ruby.IFETCH.latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist::samples    126538916                      
-system.ruby.IFETCH.latency_hist::mean        3.120095                      
-system.ruby.IFETCH.latency_hist::gmean       3.036786                      
-system.ruby.IFETCH.latency_hist::stdev       2.265582                      
-system.ruby.IFETCH.latency_hist          |   126532168     99.99%     99.99% |        5703      0.00%    100.00% |         492      0.00%    100.00% |         323      0.00%    100.00% |         160      0.00%    100.00% |          64      0.00%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total      126538916                      
+system.ruby.IFETCH.latency_hist::samples    126602633                      
+system.ruby.IFETCH.latency_hist::mean        3.119985                      
+system.ruby.IFETCH.latency_hist::gmean       3.036795                      
+system.ruby.IFETCH.latency_hist::stdev       2.244898                      
+system.ruby.IFETCH.latency_hist          |   126595894     99.99%     99.99% |        5742      0.00%    100.00% |         458      0.00%    100.00% |         336      0.00%    100.00% |         141      0.00%    100.00% |          58      0.00%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total      126602633                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist::samples    125721184                      
+system.ruby.IFETCH.hit_latency_hist::samples    125784229                      
 system.ruby.IFETCH.hit_latency_hist::mean            3                      
 system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   125721184    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total    125721184                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   125784229    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total    125784229                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist::samples       817732                      
-system.ruby.IFETCH.miss_latency_hist::mean    21.583892                      
-system.ruby.IFETCH.miss_latency_hist::gmean    19.777346                      
-system.ruby.IFETCH.miss_latency_hist::stdev    21.240290                      
-system.ruby.IFETCH.miss_latency_hist     |      810984     99.17%     99.17% |        5703      0.70%     99.87% |         492      0.06%     99.93% |         323      0.04%     99.97% |         160      0.02%     99.99% |          64      0.01%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total       817732                      
+system.ruby.IFETCH.miss_latency_hist::samples       818404                      
+system.ruby.IFETCH.miss_latency_hist::mean    21.561079                      
+system.ruby.IFETCH.miss_latency_hist::gmean    19.774643                      
+system.ruby.IFETCH.miss_latency_hist::stdev    20.911893                      
+system.ruby.IFETCH.miss_latency_hist     |      811665     99.18%     99.18% |        5742      0.70%     99.88% |         458      0.06%     99.93% |         336      0.04%     99.98% |         141      0.02%     99.99% |          58      0.01%    100.00% |           2      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total       818404                      
 system.ruby.RMW_Read.latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.latency_hist::samples       494265                      
-system.ruby.RMW_Read.latency_hist::mean      6.023605                      
-system.ruby.RMW_Read.latency_hist::gmean     3.954302                      
-system.ruby.RMW_Read.latency_hist::stdev    10.239189                      
-system.ruby.RMW_Read.latency_hist        |      494082     99.96%     99.96% |         137      0.03%     99.99% |          14      0.00%     99.99% |          17      0.00%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.latency_hist::total       494265                      
+system.ruby.RMW_Read.latency_hist::samples       494795                      
+system.ruby.RMW_Read.latency_hist::mean      6.019475                      
+system.ruby.RMW_Read.latency_hist::gmean     3.954538                      
+system.ruby.RMW_Read.latency_hist::stdev    10.125129                      
+system.ruby.RMW_Read.latency_hist        |      494623     99.97%     99.97% |         131      0.03%     99.99% |          11      0.00%     99.99% |          18      0.00%    100.00% |           7      0.00%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.latency_hist::total       494795                      
 system.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.RMW_Read.hit_latency_hist::samples       428815                      
+system.ruby.RMW_Read.hit_latency_hist::samples       429248                      
 system.ruby.RMW_Read.hit_latency_hist::mean            3                      
 system.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428815    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.hit_latency_hist::total       428815                      
+system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      429248    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.hit_latency_hist::total       429248                      
 system.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.miss_latency_hist::samples        65450                      
-system.ruby.RMW_Read.miss_latency_hist::mean    25.833644                      
-system.ruby.RMW_Read.miss_latency_hist::gmean    24.151736                      
-system.ruby.RMW_Read.miss_latency_hist::stdev    18.422970                      
-system.ruby.RMW_Read.miss_latency_hist   |       65267     99.72%     99.72% |         137      0.21%     99.93% |          14      0.02%     99.95% |          17      0.03%     99.98% |          10      0.02%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.miss_latency_hist::total        65450                      
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.latency_hist::samples       339542                      
-system.ruby.Locked_RMW_Read.latency_hist::mean     5.330551                      
-system.ruby.Locked_RMW_Read.latency_hist::gmean     3.775845                      
-system.ruby.Locked_RMW_Read.latency_hist::stdev     8.064390                      
-system.ruby.Locked_RMW_Read.latency_hist |      339293     99.93%     99.93% |         238      0.07%    100.00% |           4      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total       339542                      
+system.ruby.RMW_Read.miss_latency_hist::samples        65547                      
+system.ruby.RMW_Read.miss_latency_hist::mean    25.793126                      
+system.ruby.RMW_Read.miss_latency_hist::gmean    24.141988                      
+system.ruby.RMW_Read.miss_latency_hist::stdev    17.977211                      
+system.ruby.RMW_Read.miss_latency_hist   |       65375     99.74%     99.74% |         131      0.20%     99.94% |          11      0.02%     99.95% |          18      0.03%     99.98% |           7      0.01%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.miss_latency_hist::total        65547                      
+system.ruby.Locked_RMW_Read.latency_hist::bucket_size           64                      
+system.ruby.Locked_RMW_Read.latency_hist::max_bucket          639                      
+system.ruby.Locked_RMW_Read.latency_hist::samples       339654                      
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+system.ruby.Locked_RMW_Read.latency_hist::gmean     3.777860                      
+system.ruby.Locked_RMW_Read.latency_hist::stdev     8.189753                      
+system.ruby.Locked_RMW_Read.latency_hist |      339308     99.90%     99.90% |          89      0.03%     99.92% |         236      0.07%     99.99% |           2      0.00%     99.99% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total       339654                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples       300644                      
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples       300671                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300644    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total       300644                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples        38898                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.343462                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.340350                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.186116                      
-system.ruby.Locked_RMW_Read.miss_latency_hist |       38649     99.36%     99.36% |         238      0.61%     99.97% |           4      0.01%     99.98% |           3      0.01%     99.99% |           1      0.00%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total        38898                      
+system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300671    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist::total       300671                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size           64                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket          639                      
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+system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.361163                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.695962                      
+system.ruby.Locked_RMW_Read.miss_latency_hist |       38637     99.11%     99.11% |          89      0.23%     99.34% |         236      0.61%     99.95% |           2      0.01%     99.95% |           6      0.02%     99.97% |           3      0.01%     99.97% |           2      0.01%     99.98% |           3      0.01%     99.99% |           2      0.01%     99.99% |           3      0.01%    100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist::total        38983                      
 system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.latency_hist::samples       339542                      
+system.ruby.Locked_RMW_Write.latency_hist::samples       339654                      
 system.ruby.Locked_RMW_Write.latency_hist::mean            3                      
 system.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339542    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total       339542                      
+system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.latency_hist::total       339654                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339542                      
+system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339654                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339542    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist::total       339542                      
-system.ruby.Directory_Controller.Fetch         178413      0.00%      0.00%
-system.ruby.Directory_Controller.Data           97701      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       178865      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       142859      0.00%      0.00%
-system.ruby.Directory_Controller.DMA_READ          814      0.00%      0.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist::total       339654                      
+system.ruby.Directory_Controller.Fetch         178187      0.00%      0.00%
+system.ruby.Directory_Controller.Data           97745      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       178657      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       142629      0.00%      0.00%
+system.ruby.Directory_Controller.DMA_READ          815      0.00%      0.00%
 system.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement        15947      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       178413      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_READ          452      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE        45158      0.00%      0.00%
-system.ruby.Directory_Controller.ID.Memory_Data          452      0.00%      0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack        45158      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data         95761      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_READ          362      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE         1578      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement        15947      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       178413      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack        95761      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRD.Data          362      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack          362      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWR.Data         1578      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1578      0.00%      0.00%
-system.ruby.DMA_Controller.ReadRequest   |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.ReadRequest::total          814                      
+system.ruby.Directory_Controller.CleanReplacement        15738      0.00%      0.00%
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+system.ruby.Directory_Controller.I.DMA_READ          470      0.00%      0.00%
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+system.ruby.Directory_Controller.ID.Memory_Data          470      0.00%      0.00%
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+system.ruby.Directory_Controller.M.Data         95548      0.00%      0.00%
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+system.ruby.Directory_Controller.M.DMA_WRITE         1852      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement        15738      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       178187      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack        95548      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRD.Data          345      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack          345      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWR.Data         1852      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1852      0.00%      0.00%
+system.ruby.DMA_Controller.ReadRequest   |         815    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.ReadRequest::total          815                      
 system.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.WriteRequest::total        46736                      
-system.ruby.DMA_Controller.Data          |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.Data::total            814                      
+system.ruby.DMA_Controller.Data          |         815    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.Data::total            815                      
 system.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.Ack::total           46736                      
-system.ruby.DMA_Controller.READY.ReadRequest |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total          814                      
+system.ruby.DMA_Controller.READY.ReadRequest |         815    100.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
-system.ruby.DMA_Controller.BUSY_RD.Data  |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total          814                      
+system.ruby.DMA_Controller.BUSY_RD.Data  |         815    100.00%    100.00% |           0      0.00%    100.00%
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 system.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
-system.ruby.L1Cache_Controller.Load      |     6037097     40.47%     40.47% |     8881067     59.53%    100.00%
-system.ruby.L1Cache_Controller.Load::total     14918164                      
-system.ruby.L1Cache_Controller.Ifetch    |    67778726     53.56%     53.56% |    58760197     46.44%    100.00%
-system.ruby.L1Cache_Controller.Ifetch::total    126538923                      
-system.ruby.L1Cache_Controller.Store     |     5166241     48.41%     48.41% |     5505308     51.59%    100.00%
-system.ruby.L1Cache_Controller.Store::total     10671549                      
-system.ruby.L1Cache_Controller.Inv       |       16573     48.71%     48.71% |       17448     51.29%    100.00%
-system.ruby.L1Cache_Controller.Inv::total        34021                      
-system.ruby.L1Cache_Controller.L1_Replacement |      807951     30.97%     30.97% |     1801234     69.03%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      2609185                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |       12319     50.77%     50.77% |       11946     49.23%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total        24265                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |       14009     55.59%     55.59% |       11192     44.41%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total        25201                      
+system.ruby.L1Cache_Controller.Load      |     6103954     40.89%     40.89% |     8824164     59.11%    100.00%
+system.ruby.L1Cache_Controller.Load::total     14928118                      
+system.ruby.L1Cache_Controller.Ifetch    |    67859054     53.60%     53.60% |    58743585     46.40%    100.00%
+system.ruby.L1Cache_Controller.Ifetch::total    126602639                      
+system.ruby.L1Cache_Controller.Store     |     5213279     48.82%     48.82% |     5465004     51.18%    100.00%
+system.ruby.L1Cache_Controller.Store::total     10678283                      
+system.ruby.L1Cache_Controller.Inv       |       16394     48.51%     48.51% |       17401     51.49%    100.00%
+system.ruby.L1Cache_Controller.Inv::total        33795                      
+system.ruby.L1Cache_Controller.L1_Replacement |      832783     31.89%     31.89% |     1778531     68.11%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      2611314                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |       12220     50.79%     50.79% |       11839     49.21%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total        24059                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |       14364     56.68%     56.68% |       10979     43.32%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total        25343                      
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.Data      |         658     37.77%     37.77% |        1084     62.23%    100.00%
-system.ruby.L1Cache_Controller.Data::total         1742                      
-system.ruby.L1Cache_Controller.Data_Exclusive |      243874     19.04%     19.04% |     1037006     80.96%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total      1280880                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |       11192     44.40%     44.40% |       14013     55.60%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total        25205                      
-system.ruby.L1Cache_Controller.Data_all_Acks |      567820     42.55%     42.55% |      766775     57.45%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total      1334595                      
-system.ruby.L1Cache_Controller.Ack       |       12283     55.41%     55.41% |        9885     44.59%    100.00%
-system.ruby.L1Cache_Controller.Ack::total        22168                      
-system.ruby.L1Cache_Controller.Ack_all   |       12941     54.12%     54.12% |       10969     45.88%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total        23910                      
-system.ruby.L1Cache_Controller.WB_Ack    |      454484     26.95%     26.95% |     1231800     73.05%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total      1686284                      
-system.ruby.L1Cache_Controller.NP.Load   |      272421     19.86%     19.86% |     1099369     80.14%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total      1371790                      
-system.ruby.L1Cache_Controller.NP.Ifetch |      317175     38.82%     38.82% |      499890     61.18%    100.00%
-system.ruby.L1Cache_Controller.NP.Ifetch::total       817065                      
-system.ruby.L1Cache_Controller.NP.Store  |      219379     51.94%     51.94% |      202999     48.06%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       422378                      
-system.ruby.L1Cache_Controller.NP.Inv    |        5530     57.31%     57.31% |        4119     42.69%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         9649                      
-system.ruby.L1Cache_Controller.I.Load    |        8637     45.64%     45.64% |       10286     54.36%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total        18923                      
-system.ruby.L1Cache_Controller.I.Ifetch  |         116     17.39%     17.39% |         551     82.61%    100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total          667                      
-system.ruby.L1Cache_Controller.I.Store   |        5816     50.14%     50.14% |        5783     49.86%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total        11599                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |        8686     50.09%     50.09% |        8655     49.91%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total        17341                      
-system.ruby.L1Cache_Controller.S.Load    |      551952     52.35%     52.35% |      502332     47.65%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total      1054284                      
-system.ruby.L1Cache_Controller.S.Ifetch  |    67461431     53.66%     53.66% |    58259753     46.34%    100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total    125721184                      
-system.ruby.L1Cache_Controller.S.Store   |       12283     55.41%     55.41% |        9885     44.59%    100.00%
-system.ruby.L1Cache_Controller.S.Store::total        22168                      
-system.ruby.L1Cache_Controller.S.Inv     |       10821     45.28%     45.28% |       13078     54.72%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total        23899                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |      344781     38.07%     38.07% |      560779     61.93%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total       905560                      
-system.ruby.L1Cache_Controller.E.Load    |     1077334     27.76%     27.76% |     2803511     72.24%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total      3880845                      
-system.ruby.L1Cache_Controller.E.Store   |       80360     48.21%     48.21% |       86332     51.79%    100.00%
-system.ruby.L1Cache_Controller.E.Store::total       166692                      
-system.ruby.L1Cache_Controller.E.Inv     |          55     56.12%     56.12% |          43     43.88%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total           98                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |      162044     14.59%     14.59% |      948886     85.41%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total      1110930                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |         433     65.81%     65.81% |         225     34.19%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          658                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |         907     40.65%     40.65% |        1324     59.35%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2231                      
-system.ruby.L1Cache_Controller.M.Load    |     4126753     48.03%     48.03% |     4465569     51.97%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total      8592322                      
-system.ruby.L1Cache_Controller.M.Store   |     4848403     48.25%     48.25% |     5200309     51.75%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total     10048712                      
-system.ruby.L1Cache_Controller.M.Inv     |         167     44.53%     44.53% |         208     55.47%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total          375                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |      292440     50.83%     50.83% |      282914     49.17%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       575354                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |       11886     50.35%     50.35% |       11721     49.65%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23607                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |       13102     57.04%     57.04% |        9868     42.96%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total        22970                      
+system.ruby.L1Cache_Controller.Data      |         793     43.48%     43.48% |        1031     56.52%    100.00%
+system.ruby.L1Cache_Controller.Data::total         1824                      
+system.ruby.L1Cache_Controller.Data_Exclusive |      253693     19.77%     19.77% |     1029417     80.23%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total      1283110                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |       10979     43.31%     43.31% |       14368     56.69%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total        25347                      
+system.ruby.L1Cache_Controller.Data_all_Acks |      582883     43.69%     43.69% |      751335     56.31%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total      1334218                      
+system.ruby.L1Cache_Controller.Ack       |       12098     54.37%     54.37% |       10154     45.63%    100.00%
+system.ruby.L1Cache_Controller.Ack::total        22252                      
+system.ruby.L1Cache_Controller.Ack_all   |       12891     53.54%     53.54% |       11185     46.46%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total        24076                      
+system.ruby.L1Cache_Controller.WB_Ack    |      468087     27.72%     27.72% |     1220443     72.28%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total      1688530                      
+system.ruby.L1Cache_Controller.NP.Load   |      281209     20.47%     20.47% |     1092251     79.53%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total      1373460                      
+system.ruby.L1Cache_Controller.NP.Ifetch |      328766     40.20%     40.20% |      488985     59.80%    100.00%
+system.ruby.L1Cache_Controller.NP.Ifetch::total       817751                      
+system.ruby.L1Cache_Controller.NP.Store  |      223831     53.02%     53.02% |      198319     46.98%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       422150                      
+system.ruby.L1Cache_Controller.NP.Inv    |        5086     54.54%     54.54% |        4239     45.46%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         9325                      
+system.ruby.L1Cache_Controller.I.Load    |        8631     45.67%     45.67% |       10269     54.33%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total        18900                      
+system.ruby.L1Cache_Controller.I.Ifetch  |         106     16.23%     16.23% |         547     83.77%    100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total          653                      
+system.ruby.L1Cache_Controller.I.Store   |        5805     50.11%     50.11% |        5779     49.89%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total        11584                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |        8985     51.90%     51.90% |        8328     48.10%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total        17313                      
+system.ruby.L1Cache_Controller.S.Load    |      530372     50.22%     50.22% |      525759     49.78%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total      1056131                      
+system.ruby.L1Cache_Controller.S.Ifetch  |    67530179     53.69%     53.69% |    58254050     46.31%    100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total    125784229                      
+system.ruby.L1Cache_Controller.S.Store   |       12098     54.37%     54.37% |       10155     45.63%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total        22253                      
+system.ruby.L1Cache_Controller.S.Inv     |       11044     46.05%     46.05% |       12940     53.95%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total        23984                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |      355711     39.28%     39.28% |      549760     60.72%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total       905471                      
+system.ruby.L1Cache_Controller.E.Load    |     1138534     29.37%     29.37% |     2737774     70.63%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total      3876308                      
+system.ruby.L1Cache_Controller.E.Store   |       81127     48.65%     48.65% |       85645     51.35%    100.00%
+system.ruby.L1Cache_Controller.E.Store::total       166772                      
+system.ruby.L1Cache_Controller.E.Inv     |          48     57.83%     57.83% |          35     42.17%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total           83                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |      171015     15.36%     15.36% |      942391     84.64%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total      1113406                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |         278     59.40%     59.40% |         190     40.60%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          468                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |        1045     48.60%     48.60% |        1105     51.40%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2150                      
+system.ruby.L1Cache_Controller.M.Load    |     4145208     48.18%     48.18% |     4458111     51.82%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total      8603319                      
+system.ruby.L1Cache_Controller.M.Store   |     4890418     48.63%     48.63% |     5165106     51.37%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total     10055524                      
+system.ruby.L1Cache_Controller.M.Inv     |         216     53.73%     53.73% |         186     46.27%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total          402                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |      297072     51.65%     51.65% |      278052     48.35%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       575124                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |       11941     50.62%     50.62% |       11649     49.38%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23590                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |       13319     57.43%     57.43% |        9874     42.57%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total        23193                      
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |      243874     19.04%     19.04% |     1037006     80.96%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1280880                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11192     44.40%     44.40% |       14013     55.60%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25205                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |      343283     38.04%     38.04% |      559077     61.96%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       902360                      
-system.ruby.L1Cache_Controller.IM.Data   |         658     37.77%     37.77% |        1084     62.23%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total         1742                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |      224537     51.95%     51.95% |      207698     48.05%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       432235                      
-system.ruby.L1Cache_Controller.SM.Ack    |       12283     55.41%     55.41% |        9885     44.59%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total        22168                      
-system.ruby.L1Cache_Controller.SM.Ack_all |       12941     54.12%     54.12% |       10969     45.88%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total        23910                      
-system.ruby.L1Cache_Controller.M_I.Ifetch |           4     57.14%     57.14% |           3     42.86%    100.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch::total            7                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |      454484     26.95%     26.95% |     1231800     73.05%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1686284                      
-system.ruby.L2Cache_Controller.L1_GET_INSTR       817732      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS        1390884      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         433978      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE        22168      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX        1686284      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement        95716      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean        15992      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        178413      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         113648      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data          23349      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean         2231      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               1814      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all           7922      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock          25205      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock      1737025      0.00%      0.00%
-system.ruby.L2Cache_Controller.MEM_Inv           3880      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16558      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS        34140      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       127715      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       801143      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS        84632      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX         1919      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE        22168      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement          243      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7577      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.MEM_Inv            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR           27      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS      1246740      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX       280078      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement        95328      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean         8315      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv         1708      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |      253693     19.77%     19.77% |     1029417     80.23%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1283110                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       10979     43.31%     43.31% |       14368     56.69%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25347                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |      354040     39.24%     39.24% |      548267     60.76%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       902307                      
+system.ruby.L1Cache_Controller.IM.Data   |         793     43.48%     43.48% |        1031     56.52%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total         1824                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |      228843     52.98%     52.98% |      203068     47.02%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431911                      
+system.ruby.L1Cache_Controller.SM.Inv    |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total            1                      
+system.ruby.L1Cache_Controller.SM.Ack    |       12098     54.37%     54.37% |       10154     45.63%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total        22252                      
+system.ruby.L1Cache_Controller.SM.Ack_all |       12891     53.54%     53.54% |       11185     46.46%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total        24076                      
+system.ruby.L1Cache_Controller.M_I.Ifetch |           3     50.00%     50.00% |           3     50.00%    100.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch::total            6                      
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total            1                      
+system.ruby.L1Cache_Controller.M_I.WB_Ack |      468086     27.72%     27.72% |     1220443     72.28%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1688529                      
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |           1    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total            1                      
+system.ruby.L2Cache_Controller.L1_GET_INSTR       818404      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS        1392538      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         433736      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE        22253      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX        1688530      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement        95493      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean        15793      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        178187      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         113483      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data          23599      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean         2150      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               1627      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all           7690      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock          25347      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock      1739097      0.00%      0.00%
+system.ruby.L2Cache_Controller.MEM_Inv           4394      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16549      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS        34274      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       127364      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       801825      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS        83907      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX         1933      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE        22252      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement          275      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7330      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS      1248836      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX       280379      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement        95073      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean         8368      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv         1950      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS        25201      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX        24265      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX      1686284      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS        25343      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX        24059      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX      1688529      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT.L2_Replacement          145      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          100      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv          228      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       113648      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv         1708      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data          330      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean           95      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv          245      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       113483      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv         1950      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data          347      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_I.Ack_all           43      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv          228      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data           45      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all           55      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           1567      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         7577      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack            247      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all          247      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data        34140      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data        16558      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       127715      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS          125      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24087      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS           46      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1712938      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data        22969      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2231      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data            5      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock        25200      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv          245      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data           55      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all           40      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           1351      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         7330      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack            276      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all          277      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data        34274      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data        16549      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       127364      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS          131      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24185      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS           47      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1714912      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data        23196      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2149      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock        25345      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 1dbb00ab9..039ebcc95 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,148 +1,148 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.133759                       # Number of seconds simulated
-sim_ticks                                5133759356500                       # Number of ticks simulated
-final_tick                               5133759356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.136081                       # Number of seconds simulated
+sim_ticks                                5136081138000                       # Number of ticks simulated
+final_tick                               5136081138000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 270712                       # Simulator instruction rate (inst/s)
-host_op_rate                                   538208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5706161187                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 956212                       # Number of bytes of host memory used
-host_seconds                                   899.69                       # Real time elapsed on the host
-sim_insts                                   243556000                       # Number of instructions simulated
-sim_ops                                     484219202                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 275445                       # Simulator instruction rate (inst/s)
+host_op_rate                                   547622                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5813086840                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1006240                       # Number of bytes of host memory used
+host_seconds                                   883.54                       # Real time elapsed on the host
+sim_insts                                   243366027                       # Number of instructions simulated
+sim_ops                                     483844707                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           473664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5506752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           151296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1916928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           343744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2959424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           488576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5525632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           145728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1937472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           336128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2922880                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11383040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       473664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       151296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       343744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          968704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9167488                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9167488                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11386880                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       488576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       145728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       336128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          970432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9156352                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9156352                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7401                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             86043                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2364                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             29952                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           40                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5371                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             46241                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              7634                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             86338                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2277                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             30273                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           28                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5252                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             45670                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                177860                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143242                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143242                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                177920                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143068                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143068                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               92265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1072655                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               29471                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              373397                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               66958                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              576463                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2217291                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          92265                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          29471                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          66958                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             188693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1785726                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1785726                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1785726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               95126                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1075846                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               28373                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              377228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               65444                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              569088                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2217037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          95126                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          28373                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          65444                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             188944                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1782751                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1782751                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1782751                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              92265                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1072655                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              29471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             373397                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              66958                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             576463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4003017                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         84411                       # Number of read requests accepted
-system.physmem.writeReqs                       105225                       # Number of write requests accepted
-system.physmem.readBursts                       84411                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     105225                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5391616                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10688                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6646720                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5402304                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6734400                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      167                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    1370                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            877                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5556                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4342                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4498                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5943                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5610                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4878                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4789                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                4605                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5348                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5424                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4968                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5291                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5168                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6289                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5888                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5647                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6974                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5943                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5537                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6451                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6503                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5766                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6233                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6363                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6662                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6738                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7192                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7225                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6202                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7261                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6520                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6285                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst              95126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1075846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              28373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             377228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              65444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             569088                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3999787                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         83943                       # Number of read requests accepted
+system.physmem.writeReqs                       110041                       # Number of write requests accepted
+system.physmem.readBursts                       83943                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     110041                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5367872                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      4480                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6959552                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5372352                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7042624                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       70                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    1298                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            825                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5657                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4325                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4452                       # Per bank write bursts
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+system.physmem.perBankRdBursts::4                5499                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4854                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                4847                       # Per bank write bursts
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+system.physmem.perBankRdBursts::15               5432                       # Per bank write bursts
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+system.physmem.perBankWrBursts::12               7000                       # Per bank write bursts
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+system.physmem.perBankWrBursts::14               6569                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6112                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5132576110500                       # Total gap between requests
+system.physmem.totGap                    5132269646500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
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 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   84411                       # Read request sizes (log2)
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 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
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 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 105225                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     78589                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4433                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       775                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 110041                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
@@ -161,450 +161,457 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::4                        57                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::8                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        60                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::15                     1625                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::55                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        2                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39329                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      306.093112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.896548                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.057147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15327     38.97%     38.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9261     23.55%     62.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3835      9.75%     72.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2116      5.38%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1579      4.01%     81.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          961      2.44%     84.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          670      1.70%     85.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          553      1.41%     87.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5027     12.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39329                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4061                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.744644                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      186.795472                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            4058     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-6143            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        39516                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      311.960320                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.025881                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     337.744102                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15369     38.89%     38.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9220     23.33%     62.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3764      9.53%     71.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2091      5.29%     77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1514      3.83%     80.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          970      2.45%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          639      1.62%     84.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          601      1.52%     86.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5348     13.53%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39516                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4123                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.342712                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-511            4120     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-6655            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9728-10239            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4061                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4061                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        25.573750                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       20.065998                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       25.155630                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                71      1.75%      1.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15                7      0.17%      1.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            3181     78.33%     80.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             170      4.19%     84.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             129      3.18%     87.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              48      1.18%     88.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             114      2.81%     91.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              18      0.44%     92.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              31      0.76%     92.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              38      0.94%     93.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              54      1.33%     95.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              16      0.39%     95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103             98      2.41%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             9      0.22%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119            19      0.47%     98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             5      0.12%     98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            15      0.37%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             3      0.07%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            11      0.27%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             4      0.10%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.10%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             2      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             3      0.07%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             4      0.10%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.05%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             2      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4061                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      954764500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2534339500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    421220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11333.32                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4123                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4123                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        26.374727                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.353037                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       26.922743                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                71      1.72%      1.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15                7      0.17%      1.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            3190     77.37%     79.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             194      4.71%     83.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             131      3.18%     87.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              35      0.85%     87.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             132      3.20%     91.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              15      0.36%     91.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              23      0.56%     92.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              42      1.02%     93.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              60      1.46%     94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              20      0.49%     95.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             93      2.26%     97.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             8      0.19%     97.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119            26      0.63%     98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             5      0.12%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            22      0.53%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             8      0.19%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            11      0.27%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             2      0.05%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             5      0.12%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             3      0.07%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             3      0.07%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.07%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             5      0.12%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-223             4      0.10%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4123                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      931934250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2504553000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    419365000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11111.25                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30083.32                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29861.25                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.29                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.36                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.37                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      67051                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81719                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.59                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27065410.10                       # Average gap between requests
-system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4938610465000                       # Time in different power states
-system.physmem.memoryStateTime::REF      171427360000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       23717365000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 143949960                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 153377280                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  78544125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  83688000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                313723800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                343379400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               322509600                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               350470800                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          335311916160                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          335311916160                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          122830725285                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          123321765465                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2972506855500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2972076118500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3431508224430                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3431640715605                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.420699                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.446507                       # Core power per rank (mW)
+system.physmem.avgWrQLen                        12.18                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      66618                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     86482                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.53                       # Row buffer hit rate for writes
+system.physmem.avgGap                     26457180.21                       # Average gap between requests
+system.physmem.pageHitRate                      79.48                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  145862640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   79389750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 313817400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                352952640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250172869440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            94379716215                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2235135422250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2580580030335                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.988936                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3685687946000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    127900240000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     17077044750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  152878320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   83263125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 340392000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                351702000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250172869440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            95036922225                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2235169487250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2581307514360                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.001289                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3684742447500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    127900240000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     18039817250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                       816782821                       # number of cpu cycles simulated
+system.cpu0.numCycles                       818737889                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   71499658                       # Number of instructions committed
-system.cpu0.committedOps                    145804776                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            133691400                       # Number of integer alu accesses
+system.cpu0.committedInsts                   71815441                       # Number of instructions committed
+system.cpu0.committedOps                    146372002                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            134241940                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     937441                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14175274                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   133691400                       # number of integer instructions
+system.cpu0.num_func_calls                     946109                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14229680                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   134241940                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          245252400                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         114908320                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          246318200                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         115340862                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            83238542                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55564556                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13632532                       # number of memory refs
-system.cpu0.num_load_insts                   10074437                       # Number of load instructions
-system.cpu0.num_store_insts                   3558095                       # Number of store instructions
-system.cpu0.num_idle_cycles              775198881.273652                       # Number of idle cycles
-system.cpu0.num_busy_cycles              41583939.726348                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050912                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949088                       # Percentage of idle cycles
-system.cpu0.Branches                         15460140                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                93742      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                131973601     90.51%     90.58% # Class of executed instruction
-system.cpu0.op_class::IntMult                   57512      0.04%     90.62% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    47972      0.03%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.65% # Class of executed instruction
-system.cpu0.op_class::MemRead                10074437      6.91%     97.56% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3558095      2.44%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            83590760                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55777582                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13734986                       # number of memory refs
+system.cpu0.num_load_insts                   10122778                       # Number of load instructions
+system.cpu0.num_store_insts                   3612208                       # Number of store instructions
+system.cpu0.num_idle_cycles              777021055.677311                       # Number of idle cycles
+system.cpu0.num_busy_cycles              41716833.322689                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050953                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949047                       # Percentage of idle cycles
+system.cpu0.Branches                         15525387                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                95218      0.07%      0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu                132436366     90.48%     90.54% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58371      0.04%     90.58% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    47638      0.03%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.62% # Class of executed instruction
+system.cpu0.op_class::MemRead                10122778      6.92%     97.53% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3612208      2.47%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 145805359                       # Class of executed instruction
+system.cpu0.op_class::total                 146372579                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          1638252                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999461                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19656533                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1638764                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.994731                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1637223                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999462                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19645241                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1637735                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.995372                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.389920                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.383418                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.226123                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246855                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.547624                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205520                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.457209                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   281.700690                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   103.841562                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246987                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.550197                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.202816                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88454507                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88454507                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4870617                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2557813                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4089779                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11518209                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3418412                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1747628                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2910585                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8076625                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20088                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10280                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29520                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        59888                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8289029                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4305441                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7000364                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19594834                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8309117                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4315721                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7029884                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19654722                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       359255                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       161570                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       796344                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1317169                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       135705                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        61031                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       128691                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       325427                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       152338                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        62833                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       191442                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406613                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       494960                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       222601                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       925035                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1642596                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       647298                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       285434                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1116477                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2049209                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2259833750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13132608806                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  15392442556                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2339164805                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3938449787                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6277614592                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4598998555                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  17071058593                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  21670057148                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4598998555                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  17071058593                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  21670057148                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5229872                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2719383                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4886123                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12835378                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3554117                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1808659                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3039276                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8402052                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172426                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        73113                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       220962                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466501                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8783989                       # number of demand (read+write) accesses
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-system.cpu0.dcache.demand_accesses::total     21237430                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8956415                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4601155                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      8146361                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21703931                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068693                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059414                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.162981                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.102620                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038182                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.033744                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042343                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038732                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.883498                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.859396                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866402                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871623                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056348                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049161                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.116718                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.077344                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072272                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062035                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.137052                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.094416                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.716284                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16491.125451                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11686.004268                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.486114                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30603.925581                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19290.392598                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20660.278054                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18454.500201                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13192.566613                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16112.301110                       # average overall miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::total 10574.839925                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       135105                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88377043                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88377043                       # Number of data accesses
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068708                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059463                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total     0.102186                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.883045                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.860566                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.866665                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871785                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056620                       # miss rate for demand accesses
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+system.cpu0.dcache.demand_miss_rate::total     0.077058                       # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total     0.094138                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14134.281037                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16407.541418                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11583.187769                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38165.458681                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31109.719455                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19006.647869                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20718.073964                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18409.650647                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 13060.629151                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16166.908773                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15215.427408                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10461.106053                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       134433                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            28093                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            27793                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.809205                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.836937                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1547770                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1547770                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           57                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       372578                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       372635                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1579                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        31008                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        32587                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1636                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       403586                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       405222                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1636                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       403586                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       405222                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       161513                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       423766                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       585279                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59452                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        97683                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       157135                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        62832                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       187900                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       250732                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       220965                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       521449                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       742414                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       283797                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       709349                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       993146                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1935504250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5902265073                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7837769323                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2132980169                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3177778177                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5310758346                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    865437000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2825430002                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3690867002                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4068484419                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9080043250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13148527669                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4933921419                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11905473252                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16839394671                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30454123000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33015030500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63469153500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    582453000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    716246000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1298699000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31036576000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33731276500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64767852500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059393                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086728                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045599                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032871                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032140                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018702                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.859382                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850372                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.537474                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048799                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065795                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034958                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061680                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087076                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045759                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11983.581817                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13928.123240                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13391.509559                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35877.349273                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32531.537494                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33797.424800                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13773.825439                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15036.881330                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14720.366774                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18412.347743                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17413.099364                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17710.506091                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17385.389624                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16783.661148                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16955.608411                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1546924                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1546924                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           56                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       365946                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       366002                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1557                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        30874                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        32431                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1613                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       396820                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       398433                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1613                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       396820                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       398433                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       162143                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       418897                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       581040                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59649                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        92853                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       152502                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        62890                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       187206                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       250096                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       221792                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       511750                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       733542                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       284682                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       698956                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       983638                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1966861250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5809520082                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7776381332                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2132969160                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3102124491                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5235093651                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    862802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2814001254                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3676803254                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4099830410                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8911644573                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13011474983                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4962632410                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11725645827                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16688278237                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30452841000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32981775500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63434616500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    580448000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    654820000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1235268000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31033289000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33636595500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64669884500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059443                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087070                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045336                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032920                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031131                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018150                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.860552                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850612                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.536618                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048857                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065662                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034570                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061717                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087219                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.045361                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12130.411119                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13868.612289                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13383.555920                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35758.674244                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33408.985073                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34328.032754                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13719.224042                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15031.576199                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14701.567614                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18485.023851                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17414.058765                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17737.873200                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17432.195959                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16775.942730                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16965.873865                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -615,515 +622,516 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           869855                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.839263                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          129296965                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           870367                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           148.554535                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     149014386250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   139.113677                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.308370                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.417216                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271706                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520134                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205893                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997733                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           864556                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.818449                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129670562                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           865068                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           149.896380                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     150508783000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   137.666475                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   267.493000                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.658974                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.268880                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.522447                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.206365                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997692                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          296                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131061052                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131061052                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     86941528                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39247522                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3107915                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      129296965                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     86941528                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39247522                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3107915                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       129296965                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     86941528                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39247522                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3107915                       # number of overall hits
-system.cpu0.icache.overall_hits::total      129296965                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       320636                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       160378                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       412688                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       893702                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       320636                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       160378                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       412688                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        893702                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       320636                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       160378                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       412688                       # number of overall misses
-system.cpu0.icache.overall_misses::total       893702                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2244294000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5764913336                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8009207336                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2244294000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5764913336                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8009207336                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2244294000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5764913336                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8009207336                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     87262164                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39407900                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3520603                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    130190667                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     87262164                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39407900                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3520603                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    130190667                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     87262164                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39407900                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3520603                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    130190667                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003674                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004070                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117221                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006865                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003674                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004070                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117221                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006865                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003674                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004070                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117221                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006865                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13993.777201                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13969.180921                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8961.832172                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8961.832172                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13993.777201                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13969.180921                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8961.832172                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4336                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131423060                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131423060                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     87330581                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     39275354                       # number of ReadReq hits
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+system.cpu0.icache.ReadReq_hits::total      129670562                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     87330581                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::cpu2.inst      3064627                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       129670562                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     87330581                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     39275354                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3064627                       # number of overall hits
+system.cpu0.icache.overall_hits::total      129670562                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       333345                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       159327                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       394745                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       887417                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       333345                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::cpu2.inst       394745                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        887417                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       333345                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       159327                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       394745                       # number of overall misses
+system.cpu0.icache.overall_misses::total       887417                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2225138500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5515741155                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7740879655                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2225138500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5515741155                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7740879655                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2225138500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5515741155                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7740879655                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     87663926                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     39434681                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3459372                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    130557979                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     87663926                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     39434681                       # number of demand (read+write) accesses
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+system.cpu0.icache.demand_accesses::total    130557979                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     87663926                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     39434681                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3459372                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    130557979                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003803                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004040                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.114109                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006797                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003803                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004040                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.114109                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006797                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003803                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004040                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.114109                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006797                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13965.859522                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13972.922152                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8722.933700                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13965.859522                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13972.922152                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8722.933700                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13965.859522                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13972.922152                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8722.933700                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4752                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              258                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              268                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.806202                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.731343                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23317                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        23317                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        23317                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        23317                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        23317                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        23317                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       160378                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       389371                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       549749                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       160378                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       389371                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       549749                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       160378                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       389371                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       549749                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1922680000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4757652042                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6680332042                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1922680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4757652042                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6680332042                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1922680000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4757652042                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6680332042                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004223                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004223                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004070                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110598                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004223                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12151.603808                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11988.427340                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12218.814555                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12151.603808                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22336                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        22336                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        22336                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        22336                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        22336                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        22336                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       159327                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       372409                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       531736                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       159327                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       372409                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       531736                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       159327                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       372409                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       531736                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1905663500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4555263703                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6460927203                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1905663500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4555263703                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6460927203                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1905663500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4555263703                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6460927203                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004040                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.107652                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004073                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004040                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.107652                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004073                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004040                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.107652                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004073                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11960.706597                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12231.884039                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.629641                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11960.706597                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12231.884039                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.629641                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11960.706597                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12231.884039                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.629641                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2604022160                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2604019962                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35714054                       # Number of instructions committed
-system.cpu1.committedOps                     69387825                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64459883                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35730684                       # Number of instructions committed
+system.cpu1.committedOps                     69408718                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64481893                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     492416                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6558216                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64459883                       # number of integer instructions
+system.cpu1.num_func_calls                     491880                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6558534                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64481893                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          119340959                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55539831                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          119402180                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55560948                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36447320                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27215061                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4790084                       # number of memory refs
-system.cpu1.num_load_insts                    2979771                       # Number of load instructions
-system.cpu1.num_store_insts                   1810313                       # Number of store instructions
-system.cpu1.num_idle_cycles              2477161896.436619                       # Number of idle cycles
-system.cpu1.num_busy_cycles              126860263.563381                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.048717                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.951283                       # Percentage of idle cycles
-system.cpu1.Branches                          7226981                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                35150      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64505894     92.96%     93.01% # Class of executed instruction
-system.cpu1.op_class::IntMult                   31723      0.05%     93.06% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    25263      0.04%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.10% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2979771      4.29%     97.39% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1810313      2.61%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36459460                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27231683                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4801643                       # number of memory refs
+system.cpu1.num_load_insts                    2988079                       # Number of load instructions
+system.cpu1.num_store_insts                   1813564                       # Number of store instructions
+system.cpu1.num_idle_cycles              2476018804.880995                       # Number of idle cycles
+system.cpu1.num_busy_cycles              128001157.119005                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.049155                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.950845                       # Percentage of idle cycles
+system.cpu1.Branches                          7226738                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                34859      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64514544     92.95%     93.00% # Class of executed instruction
+system.cpu1.op_class::IntMult                   31705      0.05%     93.04% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    26275      0.04%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.08% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2988079      4.31%     97.39% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1813564      2.61%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69388114                       # Class of executed instruction
+system.cpu1.op_class::total                  69409026                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29235559                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29235559                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           325219                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26520697                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25831839                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29092929                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29092929                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           315476                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26409431                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25746575                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.402564                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 591824                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             65511                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       154416401                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.490078                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 584007                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             63229                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       153281353                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10884284                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     144162908                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29235559                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26423663                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    142028644                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 680270                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    102603                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                5389                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             9165                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        58663                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles         3537                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          505                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3520608                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               170393                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3486                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         153432274                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.849912                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.030749                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10494646                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     143459530                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29092929                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26330582                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    141345595                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 659748                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     97189                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                4757                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             7888                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        55541                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles         2125                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          437                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3459376                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               164097                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3515                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         152337401                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.854593                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.033085                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                98146892     63.97%     63.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  849455      0.55%     64.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23639563     15.41%     79.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  596355      0.39%     80.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  820460      0.53%     80.85% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  843182      0.55%     81.40% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  578600      0.38%     81.78% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  712944      0.46%     82.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27244823     17.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                97296263     63.87%     63.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  832536      0.55%     64.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23575408     15.48%     79.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  586344      0.38%     80.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  814239      0.53%     80.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  832677      0.55%     81.36% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  567105      0.37%     81.73% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  704147      0.46%     82.19% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27128682     17.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           153432274                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.189329                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.933598                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10016257                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             93700057                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 23552939                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              5059225                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                340786                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             280915475                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                340786                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12183481                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76207577                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4633489                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 26208589                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             13095410                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             279683437                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               223314                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5946104                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 66230                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               4950669                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          334110880                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            610223912                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       374707495                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               50                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            321802825                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12308055                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            159496                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        160992                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 24728287                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6624186                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3707561                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           399799                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          335575                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 277732310                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             423659                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                275640781                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           103956                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8785176                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     13632215                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         64646                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    153432274                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.796498                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.396081                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           152337401                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.189801                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.935923                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9688238                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             93124886                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23395204                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5013369                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                330525                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             279674043                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                330525                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                11836052                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               76001562                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4488572                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 26027497                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             12868079                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             278471354                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               223428                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5927671                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 64367                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4764004                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          332707542                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            607302278                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       372965322                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              116                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            320669422                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                12038120                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            154906                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        156494                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 24500450                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6532282                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3632430                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           395237                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          325236                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 276569941                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             416887                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                274532538                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           100855                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8584816                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     13350787                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         62925                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    152337401                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.802135                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.398465                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           90704132     59.12%     59.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5447937      3.55%     62.67% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3973753      2.59%     65.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3694975      2.41%     67.67% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           22399331     14.60%     82.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2621812      1.71%     83.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23895005     15.57%     99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             478633      0.31%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             216696      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           89943207     59.04%     59.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5345468      3.51%     62.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3937636      2.58%     65.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3657575      2.40%     67.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           22350485     14.67%     82.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2587133      1.70%     83.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23826816     15.64%     99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             472076      0.31%     99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             217005      0.14%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      153432274                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      152337401                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1775129     86.29%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                220574     10.72%     97.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                61430      2.99%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1755222     86.36%     86.36% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     86.36% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                    168      0.01%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.37% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                216539     10.65%     97.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                60595      2.98%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            78003      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            265083835     96.17%     96.20% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               56667      0.02%     96.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                50646      0.02%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6950861      2.52%     98.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3420769      1.24%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            75570      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            264135020     96.21%     96.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               55664      0.02%     96.26% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                49906      0.02%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6866354      2.50%     98.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3350024      1.22%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             275640781                       # Type of FU issued
-system.cpu2.iq.rate                          1.785049                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2057234                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007463                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         706874938                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        286945707                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    274032875                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 88                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                98                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           22                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             277619970                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     42                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          720639                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             274532538                       # Type of FU issued
+system.cpu2.iq.rate                          1.791037                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2032524                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007404                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         703535734                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        285575754                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    272952384                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                122                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes               212                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           32                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             276489433                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     59                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          719306                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1236107                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6357                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5250                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       663784                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1204229                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6084                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         4820                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       645551                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       755898                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        23011                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       756143                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        21686                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                340786                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               71022096                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              1766284                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          278155969                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            42225                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6624208                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3707561                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            245817                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                196681                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              1270617                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5250                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        184655                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       193373                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              378028                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            275054919                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6809103                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           532643                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                330525                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               70849508                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              1741832                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          276986828                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            38338                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6532282                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3632430                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            240586                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                193301                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              1249611                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          4820                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        179927                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       186201                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              366128                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273965652                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6730604                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           516589                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    10142277                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27929616                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3333174                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.781255                       # Inst execution rate
-system.cpu2.iew.wb_sent                     274858802                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    274032897                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                213637344                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                350353641                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9996676                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27816636                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3266072                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.787338                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273775485                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    272952416                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212880444                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                349125324                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.774636                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609776                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.780728                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609754                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9127323                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         359013                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           328005                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    152066658                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.769136                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.649747                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8921992                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         353962                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           318190                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    151004847                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.775201                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.653055                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     94590362     62.20%     62.20% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4261266      2.80%     65.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1284145      0.84%     65.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24598382     16.18%     82.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4      1032712      0.68%     82.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       681511      0.45%     83.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       477761      0.31%     83.47% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23127222     15.21%     98.68% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2013297      1.32%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     93801921     62.12%     62.12% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4186228      2.77%     64.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1259762      0.83%     65.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24518557     16.24%     81.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      1012800      0.67%     82.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       677237      0.45%     83.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       473264      0.31%     83.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23075029     15.28%     98.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2000049      1.32%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    152066658                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           136342288                       # Number of instructions committed
-system.cpu2.commit.committedOps             269026601                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    151004847                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           135819902                       # Number of instructions committed
+system.cpu2.commit.committedOps             268063987                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8431878                       # Number of memory references committed
-system.cpu2.commit.loads                      5388101                       # Number of loads committed
-system.cpu2.commit.membars                     162694                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27513301                       # Number of branches committed
+system.cpu2.commit.refs                       8314932                       # Number of memory references committed
+system.cpu2.commit.loads                      5328053                       # Number of loads committed
+system.cpu2.commit.membars                     161474                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27411077                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                245807321                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              438928                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        45809      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       260445608     96.81%     96.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          54412      0.02%     96.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           48894      0.02%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5388101      2.00%     98.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3043777      1.13%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                244897516                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              434912                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        44620      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       259602696     96.84%     96.86% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          53542      0.02%     96.88% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           48197      0.02%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5328053      1.99%     98.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2986879      1.11%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        269026601                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2013297                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        268063987                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2000049                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   428179753                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  557679634                       # The number of ROB writes
-system.cpu2.timesIdled                         117886                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                         984127                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4904701568                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  136342288                       # Number of Instructions Simulated
-system.cpu2.committedOps                    269026601                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.132564                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.132564                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.882952                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.882952                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               366241285                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              219634896                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72934                       # number of floating regfile reads
+system.cpu2.rob.rob_reads                   425964171                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  555310468                       # The number of ROB writes
+system.cpu2.timesIdled                         112460                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                         943952                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4909839532                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  135819902                       # Number of Instructions Simulated
+system.cpu2.committedOps                    268063987                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.128563                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.128563                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.886082                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.886082                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               364708409                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218787106                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    72944                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                139741848                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               107405291                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               89464185                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                137179                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3554524                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3554524                       # Transaction distribution
+system.cpu2.cc_regfile_reads                139159619                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               107004309                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               89032423                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                133306                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3554527                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3554527                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57693                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              10973                       # Transaction distribution
 system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
@@ -1148,11 +1156,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total      7129192                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95242                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95242                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3332                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3332                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7227766                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7227772                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
@@ -1172,24 +1180,24 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total      3570795                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027752                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027752                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6664                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6605211                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2723904                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  6605235                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2673040                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              5226000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4313000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                25000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                22000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
@@ -1197,64 +1205,64 @@ system.iobus.reqLayer8.occupancy                18000                       # La
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              355000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              345000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            10403000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            10349000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           252354975                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           277910069                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           303598000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           302790000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            31582004                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            34215251                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1142000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1117000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47566                       # number of replacements
-system.iocache.tags.tagsinuse                0.080066                       # Cycle average of tags in use
+system.iocache.tags.replacements                47569                       # number of replacements
+system.iocache.tags.tagsinuse                0.087266                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47582                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000571333009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.080066                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005004                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005004                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000571413009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.087266                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005454                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005454                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428589                       # Number of tag accesses
-system.iocache.tags.data_accesses              428589                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          901                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              901                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
+system.iocache.tags.data_accesses              428616                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
 system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
 system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          901                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               901                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          901                       # number of overall misses
-system.iocache.overall_misses::total              901                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    129757279                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    129757279                       # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   6940731692                       # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total   6940731692                       # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    129757279                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    129757279                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    129757279                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    129757279                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          901                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            901                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
+system.iocache.overall_misses::total              904                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    131125053                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    131125053                       # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   7701347765                       # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total   7701347765                       # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    131125053                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    131125053                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    131125053                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    131125053                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
 system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          901                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             901                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          901                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            901                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
@@ -1263,311 +1271,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 144014.738069                       # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 148560.181764                       # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 148560.181764                       # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 144014.738069                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 144014.738069                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 144014.738069                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         39427                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145049.837389                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145049.837389                       # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 164840.491545                       # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 164840.491545                       # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145049.837389                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145049.837389                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145049.837389                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145049.837389                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         44239                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5130                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 5740                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     7.685575                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.707143                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          749                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        26264                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        26264                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          749                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          749                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          749                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          749                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     90783279                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   5574995700                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     90783279                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     90783279                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     90783279                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.831299                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.562158                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.831299                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.831299                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.831299                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 121205.979973                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212267.579196                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212267.579196                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 121205.979973                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          737                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          737                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        28920                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        28920                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          737                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          737                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          737                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          737                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     92773553                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     92773553                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6197505767                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6197505767                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     92773553                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     92773553                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     92773553                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     92773553                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.815265                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.815265                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.619007                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.619007                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.815265                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.815265                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.815265                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.815265                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 125879.990502                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 214298.263036                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214298.263036                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 125879.990502                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 125879.990502                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104681                       # number of replacements
-system.l2c.tags.tagsinuse                64826.811839                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3703362                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168901                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.926229                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104557                       # number of replacements
+system.l2c.tags.tagsinuse                64826.146133                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3692284                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168716                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.884611                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51337.140952                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134260                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1734.424462                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4936.447431                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      379.153025                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1982.017983                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.155297                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      876.173345                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3570.165084                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.783343                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51357.956330                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134652                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1732.560753                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4954.090850                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      380.669805                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1966.640889                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.273350                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      862.228039                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3565.591465                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.783660                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.026465                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.075324                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.005785                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.030243                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000170                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.013369                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.054476                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.989179                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64220                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
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 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.838517                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.886861                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.834520                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1576,113 +1584,119 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96575                       # number of writebacks
-system.l2c.writebacks::total                    96575                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2364                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu2.data          469                       # number of UpgradeReq MSHR misses
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 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1693,66 +1707,62 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5119623                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5119621                       # Transaction distribution
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-system.membus.trans_dist::WriteResp             13885                       # Transaction distribution
-system.membus.trans_dist::Writeback            143242                       # Transaction distribution
+system.membus.trans_dist::ReadReq             5119668                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5119668                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13886                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13886                       # Transaction distribution
+system.membus.trans_dist::Writeback            143068                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
 system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1670                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1670                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130030                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130030                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1653                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1653                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130108                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130108                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1666                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1666                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3332                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3332                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129192                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039944                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       455611                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10624751                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141603                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141603                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10769686                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3040070                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       455653                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10624915                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141621                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141621                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10769868                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570795                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079885                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17550016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27200696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6014848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      6014848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33222208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              744                       # Total snoops (count)
-system.membus.snoop_fanout::samples            370602                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6080137                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17551104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27202036                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6015808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      6015808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33224508                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              602                       # Total snoops (count)
+system.membus.snoop_fanout::samples            370472                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  370602    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  370472    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              370602                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           163555999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              370472                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           162446500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           314970500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           314906500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2284000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2234000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1078528499                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1120775500                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1142000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1117000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1669525375                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1662967675                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           33021996                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           35567749                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1766,52 +1776,51 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            7445520                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7444981                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13887                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13887                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1547770                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        26264                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1672                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1672                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           291256                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          291256                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740744                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14998032                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73579                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       215574                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17027929                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55702976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213603640                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       275304                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       788512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270370432                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           71210                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4262409                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.011172                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105107                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            7434879                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7434349                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13888                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13888                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          1546924                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        28920                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1664                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1664                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           291412                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          291412                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1730144                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14995223                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        73480                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       207718                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17006565                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55364032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213483380                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       273608                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       760144                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              269881164                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           70776                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4251023                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.011203                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.105249                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                4214788     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  47621      1.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                4203399     98.88%     98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  47624      1.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4262409                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5252515580                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4251023                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5194614325                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           954000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           931500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2476922699                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2395792281                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4880781676                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4837647628                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          25221399                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          25185912                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          92014088                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          87831597                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed