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Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha/tru64/o3-timing')
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini19
-rwxr-xr-xtests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt1170
3 files changed, 600 insertions, 595 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index daf1db8c9..edcedb474 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -479,6 +479,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@@ -511,6 +512,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
index 043586087..4407b6430 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:43:44
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 22:56:39
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -41,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 133778696500 because target called exit()
+Exiting @ tick 133696809500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 80e818735..1f1ca601b 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,45 +1,45 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133774 # Number of seconds simulated
-sim_ticks 133773851500 # Number of ticks simulated
-final_tick 133773851500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133697 # Number of seconds simulated
+sim_ticks 133696809500 # Number of ticks simulated
+final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 262576 # Simulator instruction rate (inst/s)
-host_op_rate 262576 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62108832 # Simulator tick rate (ticks/s)
-host_mem_usage 226536 # Number of bytes of host memory used
-host_seconds 2153.86 # Real time elapsed on the host
+host_inst_rate 77616 # Simulator instruction rate (inst/s)
+host_op_rate 77616 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18348551 # Simulator tick rate (ticks/s)
+host_mem_usage 272684 # Number of bytes of host memory used
+host_seconds 7286.51 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1697536 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 26524 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 455934 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12233661 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12689595 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 455934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 455934 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 501383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 501383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 501383 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 455934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12233661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13190979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 26524 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26526 # Total number of read requests seen
system.physmem.writeReqs 1048 # Total number of write requests seen
-system.physmem.cpureqs 27572 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1697536 # Total number of bytes read from memory
+system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1697664 # Total number of bytes read from memory
system.physmem.bytesWritten 67072 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1697536 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
@@ -47,22 +47,22 @@ system.physmem.perBankRdReqs::0 1631 # Tr
system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1647 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1724 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1675 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1682 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis
@@ -70,21 +70,21 @@ system.physmem.perBankWrReqs::7 56 # Tr
system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 133773818000 # Total gap between requests
+system.physmem.totGap 133696776000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 26524 # Categorize read packet sizes
+system.physmem.readPktSize::6 26526 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
@@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1048 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 8806 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11451 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1096 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
@@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
@@ -156,56 +156,56 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 654284750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1345973500 # Sum of mem lat for all requests
-system.physmem.totBusLat 132545000 # Total cycles spent in databus access
-system.physmem.totBankLat 559143750 # Total cycles spent in bank access
-system.physmem.avgQLat 24681.61 # Average queueing delay per request
-system.physmem.avgBankLat 21092.60 # Average bank access latency per request
+system.physmem.totQLat 652146750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests
+system.physmem.totBusLat 132555000 # Total cycles spent in databus access
+system.physmem.totBankLat 565881250 # Total cycles spent in bank access
+system.physmem.avgQLat 24599.10 # Average queueing delay per request
+system.physmem.avgBankLat 21345.15 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 50774.21 # Average memory access latency
-system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 50944.25 # Average memory access latency
+system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.10 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.24 # Average write queue length over time
-system.physmem.readRowHits 16966 # Number of row buffer hits during reads
-system.physmem.writeRowHits 271 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.00 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
-system.physmem.avgGap 4851799.58 # Average gap between requests
-system.cpu.branchPred.lookups 76502410 # Number of BP lookups
-system.cpu.branchPred.condPredicted 70922676 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2717282 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 43095322 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 41949760 # Number of BTB hits
+system.physmem.avgWrQLen 9.33 # Average write queue length over time
+system.physmem.readRowHits 16975 # Number of row buffer hits during reads
+system.physmem.writeRowHits 275 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes
+system.physmem.avgGap 4848653.66 # Average gap between requests
+system.cpu.branchPred.lookups 76441752 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.341795 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1606512 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 241 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 122629608 # DTB read hits
-system.cpu.dtb.read_misses 28810 # DTB read misses
+system.cpu.dtb.read_hits 122608255 # DTB read hits
+system.cpu.dtb.read_misses 28801 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 122658418 # DTB read accesses
-system.cpu.dtb.write_hits 40760367 # DTB write hits
-system.cpu.dtb.write_misses 25602 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 40785969 # DTB write accesses
-system.cpu.dtb.data_hits 163389975 # DTB hits
-system.cpu.dtb.data_misses 54412 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 163444387 # DTB accesses
-system.cpu.itb.fetch_hits 65529846 # ITB hits
+system.cpu.dtb.read_accesses 122637056 # DTB read accesses
+system.cpu.dtb.write_hits 40754827 # DTB write hits
+system.cpu.dtb.write_misses 25617 # DTB write misses
+system.cpu.dtb.write_acv 1 # DTB write access violations
+system.cpu.dtb.write_accesses 40780444 # DTB write accesses
+system.cpu.dtb.data_hits 163363082 # DTB hits
+system.cpu.dtb.data_misses 54418 # DTB misses
+system.cpu.dtb.data_acv 1 # DTB access violations
+system.cpu.dtb.data_accesses 163417500 # DTB accesses
+system.cpu.itb.fetch_hits 65484737 # ITB hits
system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 65529887 # ITB accesses
+system.cpu.itb.fetch_accesses 65484778 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -219,238 +219,238 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 267547704 # number of cpu cycles simulated
+system.cpu.numCycles 267393620 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 67181660 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 699454641 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 76502410 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 43556272 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 117851527 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11664601 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 73301689 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 65529846 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 933458 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 267250540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.617224 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.444995 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 149399013 55.90% 55.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10348526 3.87% 59.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11849388 4.43% 64.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10578020 3.96% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7012807 2.62% 70.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2871984 1.07% 71.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3578789 1.34% 73.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3106707 1.16% 74.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 68505306 25.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 267250540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.285939 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.614317 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 84320129 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 57595253 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 102753479 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 13668133 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8913546 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3876280 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 932 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 691464517 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3449 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 8913546 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 92299678 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12776720 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1189 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 103108433 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 50150974 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 681302234 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 431 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 38477727 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5455282 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 520934901 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 897390123 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 897387366 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2757 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 57080012 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 63 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 112027328 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 127008438 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 42384710 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14844783 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 10088023 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 621271293 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 604725807 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 299798 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 55080788 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 30005964 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 267250540 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.262767 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.823653 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit.
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+system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 52429829 19.62% 19.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 55852855 20.90% 40.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 53444845 20.00% 60.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 36460113 13.64% 74.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31255141 11.70% 85.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 23773948 8.90% 94.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10075913 3.77% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3406027 1.27% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 551869 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 267250540 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2756472 71.14% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 40 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 728591 18.80% 89.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 389871 10.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 439176954 72.62% 72.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7066 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 124356224 20.56% 93.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 41185515 6.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 604725807 # Type of FU issued
-system.cpu.iq.rate 2.260254 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3874974 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006408 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1480873086 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 676355161 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 596602519 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3840 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2402 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1730 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 608598846 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1935 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 12280408 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued
+system.cpu.iq.rate 2.261003 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes
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+system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12494396 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 35705 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5495 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2933389 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6442 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 54892 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8913546 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1440408 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 191911 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 664145675 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1694595 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 127008438 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 42384710 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 55 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 143753 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7490 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5495 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1342563 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1811283 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3153846 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599598114 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 122658565 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5127693 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 42874327 # number of nop insts executed
-system.cpu.iew.exec_refs 163462793 # number of memory reference insts executed
-system.cpu.iew.exec_branches 66641793 # Number of branches executed
-system.cpu.iew.exec_stores 40804228 # Number of stores executed
-system.cpu.iew.exec_rate 2.241089 # Inst execution rate
-system.cpu.iew.wb_sent 597543507 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 596604249 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 415969736 # num instructions producing a value
-system.cpu.iew.wb_consumers 530347418 # num instructions consuming a value
+system.cpu.iew.exec_nop 42838707 # number of nop insts executed
+system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed
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+system.cpu.iew.exec_rate 2.241913 # Inst execution rate
+system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 415924305 # num instructions producing a value
+system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.229899 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.784334 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 62164646 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2716416 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 258336994 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.329736 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.693311 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 79521079 30.78% 30.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 72557315 28.09% 58.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 25650829 9.93% 68.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9136101 3.54% 72.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 10241480 3.96% 76.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 20967757 8.12% 84.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6801640 2.63% 87.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3711202 1.44% 88.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 29749591 11.52% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 258336994 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -461,192 +461,192 @@ system.cpu.commit.branches 62547159 # Nu
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 29749591 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 892544623 # The number of ROB reads
-system.cpu.rob.rob_writes 1336970755 # The number of ROB writes
-system.cpu.timesIdled 34274 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 297164 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 892250711 # The number of ROB reads
+system.cpu.rob.rob_writes 1336492363 # The number of ROB writes
+system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.473073 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.473073 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.113838 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.113838 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 845171662 # number of integer regfile reads
-system.cpu.int_regfile_writes 490625638 # number of integer regfile writes
-system.cpu.fp_regfile_reads 396 # number of floating regfile reads
+system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 844981893 # number of integer regfile reads
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system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 39 # number of replacements
-system.cpu.icache.tagsinuse 824.684718 # Cycle average of tags in use
-system.cpu.icache.total_refs 65528462 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 971 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 67485.542739 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use
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+system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 824.684718 # Average occupied blocks per requestor
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-system.cpu.icache.occ_percent::total 0.402678 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_hits::total 65528462 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 65528462 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses
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-system.cpu.icache.overall_misses::total 1383 # number of overall misses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52494.938539 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52494.938539 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52494.938539 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52494.938539 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52494.938539 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53388.124547 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53388.124547 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53388.124547 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 25.400000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 33.200000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.WriteReq_mshr_misses::total 254495 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 464937 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 464937 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 464937 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 464937 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697776000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697776000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4104342498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4104342498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6802118498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6802118498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6802118498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6802118498 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12816.443331 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12816.443331 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16121.301810 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16121.301810 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14625.897456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14625.897456 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------