diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha/tru64/simple-timing')
3 files changed, 256 insertions, 181 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 0bc5277c7..83c88fa93 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 36bd68fb7..dfe9fcdd2 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:24:12 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:31 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4d7850adf..4b454bbcf 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2199350 # Simulator instruction rate (inst/s) -host_tick_rate 2797795440 # Simulator tick rate (ticks/s) -host_mem_usage 207676 # Number of bytes of host memory used -host_seconds 273.65 # Real time elapsed on the host +host_inst_rate 2698243 # Simulator instruction rate (inst/s) +host_op_rate 2698243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3432438217 # Simulator tick rate (ticks/s) +host_mem_usage 209572 # Number of bytes of host memory used +host_seconds 223.06 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated +sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5889984 # Number of bytes read from this memory system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory system.physmem.bytes_written 3797824 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.committedInsts 601856964 # Number of instructions committed +system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses system.cpu.num_func_calls 2395217 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 601861103 # To system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.328778 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits -system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits -system.cpu.icache.overall_hits 601861103 # number of overall hits -system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.demand_misses 795 # number of demand (read+write) misses -system.cpu.icache.overall_misses 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 601861103 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 601861103 # number of overall hits +system.cpu.icache.overall_hits::total 601861103 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 795 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 795 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses +system.cpu.icache.overall_misses::total 795 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 601861898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 795 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 153509968 # To system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits +system.cpu.dcache.overall_hits::total 153509968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses +system.cpu.dcache.overall_misses::total 455395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408190 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 445709 # To system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052565 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits +system.cpu.l2cache.overall_hits::total 364159 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses +system.cpu.l2cache.overall_misses::total 92031 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59341 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks +system.cpu.l2cache.writebacks::total 59341 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |