diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/alpha/tru64')
9 files changed, 1096 insertions, 1087 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index c1fb80fc3..201ee02a7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index b4ecd43cf..4b4f6933d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:43:43 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:24 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274300226500 because target called exit() +Exiting @ tick 271948359500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index e5597cd29..c0f2578f2 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274300 # Number of seconds simulated -sim_ticks 274300226500 # Number of ticks simulated -final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271948 # Number of seconds simulated +sim_ticks 271948359500 # Number of ticks simulated +final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112537 # Simulator instruction rate (inst/s) -host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51289289 # Simulator tick rate (ticks/s) -host_mem_usage 215256 # Number of bytes of host memory used -host_seconds 5348.10 # Real time elapsed on the host +host_inst_rate 167086 # Simulator instruction rate (inst/s) +host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75497413 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 3602.09 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory -system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory +system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory +system.physmem.bytes_written::total 57024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory +system.physmem.num_writes::total 891 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517577 # DTB read hits +system.cpu.dtb.read_hits 114517207 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520208 # DTB read accesses -system.cpu.dtb.write_hits 39666608 # DTB write hits +system.cpu.dtb.read_accesses 114519838 # DTB read accesses +system.cpu.dtb.write_hits 39661898 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668910 # DTB write accesses -system.cpu.dtb.data_hits 154184185 # DTB hits +system.cpu.dtb.write_accesses 39664200 # DTB write accesses +system.cpu.dtb.data_hits 154179105 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189118 # DTB accesses -system.cpu.itb.fetch_hits 25020502 # ITB hits +system.cpu.dtb.data_accesses 154184038 # DTB accesses +system.cpu.itb.fetch_hits 25013413 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25020524 # ITB accesses +system.cpu.itb.fetch_accesses 25013435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548600454 # number of cpu cycles simulated +system.cpu.numCycles 543896720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits +system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155051949 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155049936 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. -system.cpu.activity 89.165242 # Percentage of cycles cpu is active +system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. +system.cpu.activity 89.936283 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,72 +114,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads +system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use -system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use +system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits -system.cpu.icache.overall_hits::total 25019479 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits +system.cpu.icache.overall_hits::total 25012389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,70 +188,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits -system.cpu.dcache.overall_hits::total 152394215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses -system.cpu.dcache.overall_misses::total 1571148 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits +system.cpu.dcache.overall_hits::total 152406141 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses +system.cpu.dcache.overall_misses::total 1559222 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,65 +318,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 01ebbe1c7..53e4b73f0 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ef914e93c..21003a7f0 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:29 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 134621123500 because target called exit() +Exiting @ tick 133563007500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index aa861e979..38226af10 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134621 # Number of seconds simulated -sim_ticks 134621123500 # Number of ticks simulated -final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133563 # Number of seconds simulated +sim_ticks 133563007500 # Number of ticks simulated +final_tick 133563007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192359 # Simulator instruction rate (inst/s) -host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45788058 # Simulator tick rate (ticks/s) -host_mem_usage 216172 # Number of bytes of host memory used -host_seconds 2940.09 # Real time elapsed on the host +host_inst_rate 301381 # Simulator instruction rate (inst/s) +host_op_rate 301381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71175252 # Simulator tick rate (ticks/s) +host_mem_usage 220044 # Number of bytes of host memory used +host_seconds 1876.54 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory -system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58688 # Number of bytes written to this memory +system.physmem.bytes_written::total 58688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26383 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 917 # Number of write requests responded to by this memory +system.physmem.num_writes::total 917 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 457612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12184452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12642063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 439403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 457612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12184452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13081466 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123836708 # DTB read hits -system.cpu.dtb.read_misses 23555 # DTB read misses +system.cpu.dtb.read_hits 123849413 # DTB read hits +system.cpu.dtb.read_misses 20691 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123860263 # DTB read accesses -system.cpu.dtb.write_hits 40831838 # DTB write hits -system.cpu.dtb.write_misses 31545 # DTB write misses +system.cpu.dtb.read_accesses 123870104 # DTB read accesses +system.cpu.dtb.write_hits 40835064 # DTB write hits +system.cpu.dtb.write_misses 30091 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40863383 # DTB write accesses -system.cpu.dtb.data_hits 164668546 # DTB hits -system.cpu.dtb.data_misses 55100 # DTB misses +system.cpu.dtb.write_accesses 40865155 # DTB write accesses +system.cpu.dtb.data_hits 164684477 # DTB hits +system.cpu.dtb.data_misses 50782 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164723646 # DTB accesses -system.cpu.itb.fetch_hits 66483943 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 164735259 # DTB accesses +system.cpu.itb.fetch_hits 66492910 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66483980 # ITB accesses +system.cpu.itb.fetch_accesses 66492948 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 269242248 # number of cpu cycles simulated +system.cpu.numCycles 267126016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits +system.cpu.BPredUnit.lookups 78502606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72859176 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3048930 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42879233 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41644328 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1629564 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 215 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68435581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710898129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78502606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43273892 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119207604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12936161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69569484 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66492910 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.661634 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.464377 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147883255 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10367188 3.88% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11844651 4.43% 63.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10612793 3.97% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990815 2.62% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2667876 1.00% 71.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3494727 1.31% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104174 1.16% 73.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70125380 26.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293879 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.661284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85625908 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53897418 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104721883 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12969411 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9876239 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3910148 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702131172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4692 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9876239 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93864195 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11132886 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104174566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48041540 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690226135 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36911224 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4900299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527321421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906904042 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906901104 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2938 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63466532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 116 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106984731 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129019631 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42434130 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14712304 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9648397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626510721 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 98 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608418192 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 334492 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60261200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33473416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 81 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267090859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.835634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52595450 19.69% 19.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54748440 20.50% 40.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53400082 19.99% 60.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36696955 13.74% 73.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30804090 11.53% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24162728 9.05% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10693904 4.00% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3328381 1.25% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 660829 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267090859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2950080 75.40% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 582636 14.89% 90.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 379789 9.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441018930 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7345 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued @@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126131577 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41260299 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued -system.cpu.iq.rate 2.259665 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608418192 # Type of FU issued +system.cpu.iq.rate 2.277645 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3912544 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1488170355 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686774500 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598832188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2359 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612328769 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1967 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12182137 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14505589 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4885 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2982809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6785 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 71183 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9876239 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 295412 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670453714 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691855 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129019631 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42434130 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 98 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 899 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7278 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4885 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1348504 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2206028 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3554532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602596052 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123870207 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5822140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43926324 # number of nop insts executed -system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed -system.cpu.iew.exec_branches 67006670 # Number of branches executed -system.cpu.iew.exec_stores 40880471 # Number of stores executed -system.cpu.iew.exec_rate 2.238049 # Inst execution rate -system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417486240 # num instructions producing a value -system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value +system.cpu.iew.exec_nop 43942895 # number of nop insts executed +system.cpu.iew.exec_refs 164752686 # number of memory reference insts executed +system.cpu.iew.exec_branches 67005259 # Number of branches executed +system.cpu.iew.exec_stores 40882479 # Number of stores executed +system.cpu.iew.exec_rate 2.255849 # Inst execution rate +system.cpu.iew.wb_sent 600080079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598833907 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417539542 # num instructions producing a value +system.cpu.iew.wb_consumers 531416482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back +system.cpu.iew.wb_rate 2.241766 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785711 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68437583 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3047922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257214620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.339902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78375558 30.47% 30.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72865724 28.33% 58.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26619590 10.35% 69.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8074736 3.14% 72.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10311668 4.01% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20443429 7.95% 84.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6319286 2.46% 86.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3488714 1.36% 88.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30715915 11.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257214620 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30715915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 898866221 # The number of ROB reads -system.cpu.rob.rob_writes 1350401622 # The number of ROB writes -system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 896728862 # The number of ROB reads +system.cpu.rob.rob_writes 1350487768 # The number of ROB writes +system.cpu.timesIdled 758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35157 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads -system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848641681 # number of integer regfile reads -system.cpu.int_regfile_writes 492726607 # number of integer regfile writes -system.cpu.fp_regfile_reads 387 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cpi 0.472328 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.472328 # CPI: Total CPI of All Threads +system.cpu.ipc 2.117175 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.117175 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848664377 # number of integer regfile reads +system.cpu.int_regfile_writes 492741272 # number of integer regfile writes +system.cpu.fp_regfile_reads 384 # number of floating regfile reads +system.cpu.fp_regfile_writes 47 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 49 # number of replacements -system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use -system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.496665 # Cycle average of tags in use +system.cpu.icache.total_refs 66491540 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 975 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 68196.451282 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits -system.cpu.icache.overall_hits::total 66482496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses -system.cpu.icache.overall_misses::total 1447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 827.496665 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404051 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404051 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66491540 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66491540 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66491540 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66491540 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66491540 # number of overall hits +system.cpu.icache.overall_hits::total 66491540 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1370 # number of overall misses +system.cpu.icache.overall_misses::total 1370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47830500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47830500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47830500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47830500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66492910 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66492910 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66492910 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66492910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34912.773723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,293 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 395 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 395 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 395 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 395 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits -system.cpu.dcache.overall_hits::total 149091370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses -system.cpu.dcache.overall_misses::total 2023111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31385446422 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999456 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111034129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111034129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38205852 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38205852 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 59 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 59 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149239981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149239981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149239981 # number of overall hits +system.cpu.dcache.overall_hits::total 149239981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 620415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 620415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1245469 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1245469 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1865884 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1865884 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1865884 # number of overall misses +system.cpu.dcache.overall_misses::total 1865884 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17349599733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17349599733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111654544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111654544 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151105865 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151105865 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151105865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151105865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.012348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.012348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.012348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.012348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7598.426054 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7598.426054 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 113496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 187500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4934.608696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks -system.cpu.dcache.writebacks::total 415225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444730 # number of writebacks +system.cpu.dcache.writebacks::total 444730 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410277 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 410277 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 991041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 991041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1401318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1401318 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210138 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254428 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254428 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74480 # number of replacements -system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use -system.cpu.l2cache.total_refs 461925 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90375 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.111203 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 947 # number of replacements +system.cpu.l2cache.tagsinuse 22959.894157 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555227 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23376 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.752011 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15915.661195 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.497783 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1695.845621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.485707 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.538666 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 178382 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 178382 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 415225 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 415225 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194684 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 373066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 373066 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 373066 # number of overall hits -system.cpu.l2cache.overall_hits::total 373066 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1002 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31935 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32937 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 59838 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 59838 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1002 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91773 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92775 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1002 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91773 # number of overall misses -system.cpu.l2cache.overall_misses::total 92775 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34422500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1098528500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1132951000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34422500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3165359000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3199781500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34422500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3165359000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3199781500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1002 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210317 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464839 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465841 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464839 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 955 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26383 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 133026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 162752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801450000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831176000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801450000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831176000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f4efff3d6..265a2a956 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index fcee7bced..be37b32c1 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:36 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 765623032000 because target called exit() +Exiting @ tick 762853846000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4082e04ad..a7b4a0a92 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.765623 # Number of seconds simulated -sim_ticks 765623032000 # Number of ticks simulated -final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762854 # Number of seconds simulated +sim_ticks 762853846000 # Number of ticks simulated +final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675799 # Simulator instruction rate (inst/s) -host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2131786057 # Simulator tick rate (ticks/s) -host_mem_usage 214908 # Number of bytes of host memory used -host_seconds 359.15 # Real time elapsed on the host +host_inst_rate 2331221 # Simulator instruction rate (inst/s) +host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2954822927 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 258.17 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory -system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory +system.physmem.bytes_written::total 56512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory +system.physmem.num_writes::total 883 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numCycles 1525707692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_busy_cycles 1525707692 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,65 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73734 # number of replacements -system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 903 # number of replacements +system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses @@ -325,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 456190 # n system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456190 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -355,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks -system.cpu.l2cache.writebacks::total 59341 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # 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average ReadReq mshr miss latency |