diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1136 |
1 files changed, 566 insertions, 570 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index aa7b7ad18..595117ec0 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,99 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164572 # Number of seconds simulated -sim_ticks 164572262000 # Number of ticks simulated -final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164563 # Number of seconds simulated +sim_ticks 164562530500 # Number of ticks simulated +final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185108 # Simulator instruction rate (inst/s) -host_op_rate 195599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53440170 # Simulator tick rate (ticks/s) -host_mem_usage 241944 # Number of bytes of host memory used -host_seconds 3079.56 # Real time elapsed on the host +host_inst_rate 62422 # Simulator instruction rate (inst/s) +host_op_rate 65960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18020016 # Simulator tick rate (ticks/s) +host_mem_usage 288128 # Number of bytes of host memory used +host_seconds 9132.21 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory -system.physmem.bytes_written::total 162432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27336 # Total number of read requests seen -system.physmem.writeReqs 2538 # Total number of write requests seen -system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749376 # Total number of bytes read from memory -system.physmem.bytesWritten 162432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory +system.physmem.bytes_written::total 162368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27315 # Total number of read requests seen +system.physmem.writeReqs 2537 # Total number of write requests seen +system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1748096 # Total number of bytes read from memory +system.physmem.bytesWritten 162368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164572246000 # Total gap between requests +system.physmem.totGap 164562514500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27336 # Categorize read packet sizes +system.physmem.readPktSize::6 27315 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2538 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2537 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -131,7 +131,7 @@ system.physmem.wrQLenPdf::3 111 # Wh system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see @@ -156,36 +156,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 921339250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests -system.physmem.totBusLat 136675000 # Total cycles spent in databus access -system.physmem.totBankLat 614020000 # Total cycles spent in bank access -system.physmem.avgQLat 33704.25 # Average queueing delay per request -system.physmem.avgBankLat 22461.95 # Average bank access latency per request -system.physmem.avgBusLat 4999.82 # Average bus latency per request -system.physmem.avgMemAccLat 61166.02 # Average memory access latency -system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 922192000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests +system.physmem.totBusLat 136575000 # Total cycles spent in databus access +system.physmem.totBankLat 613318750 # Total cycles spent in bank access +system.physmem.avgQLat 33761.38 # Average queueing delay per request +system.physmem.avgBankLat 22453.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 61214.93 # Average memory access latency +system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.98 # Average write queue length over time -system.physmem.readRowHits 16887 # Number of row buffer hits during reads +system.physmem.avgWrQLen 5.61 # Average write queue length over time +system.physmem.readRowHits 16878 # Number of row buffer hits during reads system.physmem.writeRowHits 1046 # Number of row buffer hits during writes -system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes -system.physmem.avgGap 5508878.82 # Average gap between requests -system.cpu.branchPred.lookups 85156760 # Number of BP lookups -system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits +system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes +system.physmem.avgGap 5512612.71 # Average gap between requests +system.cpu.branchPred.lookups 85150983 # Number of BP lookups +system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,134 +229,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329144525 # number of cpu cycles simulated +system.cpu.numCycles 329125062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued -system.cpu.iq.rate 1.961470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued +system.cpu.iq.rate 1.961548 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3084 # number of nop insts executed -system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed -system.cpu.iew.exec_branches 74674061 # Number of branches executed -system.cpu.iew.exec_stores 75873180 # Number of stores executed -system.cpu.iew.exec_rate 1.949037 # Inst execution rate -system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418732313 # num instructions producing a value -system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value +system.cpu.iew.exec_nop 3079 # number of nop insts executed +system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed +system.cpu.iew.exec_branches 74672084 # Number of branches executed +system.cpu.iew.exec_stores 75881243 # Number of stores executed +system.cpu.iew.exec_rate 1.949135 # Inst execution rate +system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418527294 # num instructions producing a value +system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,69 +472,69 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977066653 # The number of ROB reads -system.cpu.rob.rob_writes 1370815087 # The number of ROB writes -system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977022777 # The number of ROB reads +system.cpu.rob.rob_writes 1370762747 # The number of ROB writes +system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads -system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads -system.cpu.int_regfile_writes 663049374 # number of integer regfile writes +system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads +system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads +system.cpu.int_regfile_writes 663034338 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads +system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 66 # number of replacements -system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use -system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks. +system.cpu.icache.replacements 49 # number of replacements +system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use +system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits -system.cpu.icache.overall_hits::total 67083102 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses -system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.336225 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67072069 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67072069 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67072069 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67072069 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67072069 # number of overall hits +system.cpu.icache.overall_hits::total 67072069 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1113 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1113 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1113 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1113 # number of overall misses +system.cpu.icache.overall_misses::total 1113 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54408499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54408499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54408499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54408499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54408499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54408499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67073182 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67073182 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67073182 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67073182 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67073182 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -543,124 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 832 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 832 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 832 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 832 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 832 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 832 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42177999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42177999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42177999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42177999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42177999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42177999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 304 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 304 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 304 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 304 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 304 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 809 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 809 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 809 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 809 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 809 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 809 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42322999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42322999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42322999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42322999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42322999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42322999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50694.710337 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50694.710337 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50694.710337 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50694.710337 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50694.710337 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50694.710337 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52315.202719 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52315.202719 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2560 # number of replacements -system.cpu.l2cache.tagsinuse 22366.880466 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517335 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24173 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.401357 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2559 # number of replacements +system.cpu.l2cache.tagsinuse 22357.775190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517077 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24151 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.410169 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20764.354614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 652.476885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 950.048967 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633678 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019912 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.028993 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682583 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192787 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192875 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421643 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421643 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225378 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225378 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 418165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418253 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 418165 # number of overall hits -system.cpu.l2cache.overall_hits::total 418253 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 743 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5554 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 743 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26602 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27345 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 743 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses -system.cpu.l2cache.overall_misses::total 27345 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43045.754768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130945.210274 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119263.479269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60140.136197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60140.136197 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43045.754768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72896.823295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72094.674867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440669 # number of replacements -system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use -system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks. +system.cpu.dcache.replacements 440610 # number of replacements +system.cpu.dcache.tagsinuse 4091.483802 # Cycle average of tags in use +system.cpu.dcache.total_refs 197562457 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444706 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.254085 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4091.483802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 131512310 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131512310 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66047494 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66047494 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1326 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1326 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits -system.cpu.dcache.overall_hits::total 197564961 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 197559804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197559804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197559804 # number of overall hits +system.cpu.dcache.overall_hits::total 197559804 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341685 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341685 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3370037 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3370037 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses -system.cpu.dcache.overall_misses::total 3718210 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3711722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3711722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3711722 # number of overall misses +system.cpu.dcache.overall_misses::total 3711722 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5064964500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5064964500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40707637762 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40707637762 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 338000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45772602262 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45772602262 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45772602262 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45772602262 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131853995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131853995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks -system.cpu.dcache.writebacks::total 421643 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks +system.cpu.dcache.writebacks::total 421641 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |