diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt | 280 |
1 files changed, 280 insertions, 0 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..3846f97fb --- /dev/null +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,280 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.796763 # Number of seconds simulated +sim_ticks 796762926000 # Number of ticks simulated +final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1450316 # Simulator instruction rate (inst/s) +host_tick_rate 1924652930 # Simulator tick rate (ticks/s) +host_mem_usage 219100 # Number of bytes of host memory used +host_seconds 413.98 # Real time elapsed on the host +sim_insts 600398281 # Number of instructions simulated +system.physmem.bytes_read 5759488 # Number of bytes read from this memory +system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3704704 # Number of bytes written to this memory +system.physmem.num_reads 89992 # Number of read requests responded to by this memory +system.physmem.num_writes 57886 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 1593525852 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 600398281 # Number of instructions executed +system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 1993546 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls +system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 219173607 # number of memory refs +system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_store_insts 70221013 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1593525852 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use +system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits +system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits +system.cpu.icache.overall_hits 570073892 # number of overall hits +system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses +system.cpu.icache.demand_misses 643 # number of demand (read+write) misses +system.cpu.icache.overall_misses 643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 433468 # number of replacements +system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use +system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 216771819 # number of overall hits +system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses +system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 437564 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 392392 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 71804 # number of replacements +system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use +system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 348215 # number of overall hits +system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 89992 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 57886 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |