diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/arm')
9 files changed, 630 insertions, 405 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 2c3feadf1..c24180c55 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 316fa1ee5..c2143f70c 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:23 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:39:44 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e05b6f985..e204ea2b2 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.177117 # Nu sim_ticks 177116942500 # Number of ticks simulated final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89657 # Simulator instruction rate (inst/s) -host_tick_rate 26362655 # Simulator tick rate (ticks/s) -host_mem_usage 256136 # Number of bytes of host memory used -host_seconds 6718.48 # Real time elapsed on the host -sim_insts 602359810 # Number of instructions simulated +host_inst_rate 193712 # Simulator instruction rate (inst/s) +host_op_rate 204690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60186856 # Simulator tick rate (ticks/s) +host_mem_usage 223404 # Number of bytes of host memory used +host_seconds 2942.78 # Real time elapsed on the host +sim_insts 570051603 # Number of instructions simulated +sim_ops 602359810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5833792 # Number of bytes read from this memory system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory system.physmem.bytes_written 3720320 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle -system.cpu.commit.count 602359861 # Number of instructions committed +system.cpu.commit.committedInsts 570051654 # Number of instructions committed +system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 219173611 # Number of memory references committed system.cpu.commit.loads 148952596 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1023326216 # Th system.cpu.rob.rob_writes 1419524916 # The number of ROB writes system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359810 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated -system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads +system.cpu.committedInsts 570051603 # Number of Instructions Simulated +system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated +system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads +system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads system.cpu.int_regfile_writes 676006750 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -335,26 +340,39 @@ system.cpu.icache.total_refs 74421550 # To system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits -system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits -system.cpu.icache.overall_hits 74421550 # number of overall hits -system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses -system.cpu.icache.demand_misses 996 # number of demand (read+write) misses -system.cpu.icache.overall_misses 996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits +system.cpu.icache.overall_hits::total 74421550 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses +system.cpu.icache.overall_misses::total 996 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 231 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 231 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 231 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 765 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 765 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 765 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26235000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26235000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34294.117647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34294.117647 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 441200 # number of replacements system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use @@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 205785268 # To system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.750887 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 137930344 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67852261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 205782605 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 205782605 # number of overall hits -system.cpu.dcache.ReadReq_misses 248964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1565270 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1814234 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1814234 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3282822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27026336525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 201000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30309158525 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30309158525 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138179308 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 207596839 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 207596839 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001802 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006701 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008739 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008739 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16706.311603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16706.311603 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits +system.cpu.dcache.overall_hits::total 205782605 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 9 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1814234 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1814234 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1814234 # number of overall misses +system.cpu.dcache.overall_misses::total 1814234 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282822000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3282822000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27026336525 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27026336525 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 201000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30309158525 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30309158525 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30309158525 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30309158525 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138179308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138179308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 207596839 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 207596839 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 207596839 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 207596839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001802 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022549 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.006701 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51046 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1368938 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197918 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247378 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8211.509312 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks +system.cpu.dcache.writebacks::total 395250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 72965 # number of replacements system.cpu.l2cache.tagsinuse 17807.300199 # Cycle average of tags in use @@ -467,36 +520,75 @@ system.cpu.l2cache.total_refs 421253 # To system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.760351 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1881.136315 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15926.163884 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.057408 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486028 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165871 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395250 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189027 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354898 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354898 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32808 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58355 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15926.163884 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.771827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1845.364487 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.486028 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001092 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -505,31 +597,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # 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average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks +system.cpu.l2cache.writebacks::total 58130 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 8c7671d34..35f1e8fcc 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 95da0efca..d3f3c8cc8 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:36:54 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:43:07 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f48dc3640..80be44c4e 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2998309 # Simulator instruction rate (inst/s) -host_tick_rate 1499211130 # Simulator tick rate (ticks/s) -host_mem_usage 210136 # Number of bytes of host memory used -host_seconds 200.90 # Real time elapsed on the host -sim_insts 602359851 # Number of instructions simulated +host_inst_rate 3224710 # Simulator instruction rate (inst/s) +host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1703801368 # Simulator tick rate (ticks/s) +host_mem_usage 212692 # Number of bytes of host memory used +host_seconds 176.78 # Real time elapsed on the host +sim_insts 570051644 # Number of instructions simulated +sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory system.physmem.bytes_written 236359611 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 602382741 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 602359851 # Number of instructions executed +system.cpu.committedInsts 570051644 # Number of instructions committed +system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 6a1e2b970..ce56af1f4 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index 589b03862..eee2e0cb2 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:40:26 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:45:54 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 3846f97fb..4b6f6b404 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1450316 # Simulator instruction rate (inst/s) -host_tick_rate 1924652930 # Simulator tick rate (ticks/s) -host_mem_usage 219100 # Number of bytes of host memory used -host_seconds 413.98 # Real time elapsed on the host -sim_insts 600398281 # Number of instructions simulated +host_inst_rate 1806630 # Simulator instruction rate (inst/s) +host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2531848956 # Simulator tick rate (ticks/s) +host_mem_usage 221588 # Number of bytes of host memory used +host_seconds 314.70 # Real time elapsed on the host +sim_insts 568539343 # Number of instructions simulated +sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory system.physmem.bytes_written 3704704 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 48 # Nu system.cpu.numCycles 1593525852 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 600398281 # Number of instructions executed +system.cpu.committedInsts 568539343 # Number of instructions committed +system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 570073892 # To system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits -system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits -system.cpu.icache.overall_hits 570073892 # number of overall hits -system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses -system.cpu.icache.demand_misses 643 # number of demand (read+write) misses -system.cpu.icache.overall_misses 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits +system.cpu.icache.overall_hits::total 570073892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses +system.cpu.icache.overall_misses::total 643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 643 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 643 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 643 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 216774473 # To system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 216771819 # number of overall hits -system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses -system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits +system.cpu.dcache.overall_hits::total 216771819 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses +system.cpu.dcache.overall_misses::total 437564 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 392392 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks +system.cpu.dcache.writebacks::total 392392 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71804 # number of replacements system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 411836 # To system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 348215 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 89992 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits +system.cpu.l2cache.overall_hits::total 348215 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses +system.cpu.l2cache.overall_misses::total 89992 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 57886 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks +system.cpu.l2cache.writebacks::total 57886 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |