diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 1080 |
1 files changed, 540 insertions, 540 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 4f3b9b27a..fc36793dc 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387321 # Number of seconds simulated -sim_ticks 387320726500 # Number of ticks simulated -final_tick 387320726500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387291 # Number of seconds simulated +sim_ticks 387290918500 # Number of ticks simulated +final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176162 # Simulator instruction rate (inst/s) -host_op_rate 176717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48695201 # Simulator tick rate (ticks/s) -host_mem_usage 235496 # Number of bytes of host memory used -host_seconds 7953.98 # Real time elapsed on the host +host_inst_rate 75176 # Simulator instruction rate (inst/s) +host_op_rate 75413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20778674 # Simulator tick rate (ticks/s) +host_mem_usage 280588 # Number of bytes of host memory used +host_seconds 18638.87 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678784 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26231 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4334351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4334351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27427 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27428 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29960 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755264 # Total number of bytes read from memory +system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755328 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755264 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -48,16 +48,16 @@ system.physmem.perBankRdReqs::1 1716 # Tr system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 154 # Tr system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387320698500 # Total gap between requests +system.physmem.totGap 387290890500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27427 # Categorize read packet sizes +system.physmem.readPktSize::6 27428 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 7983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 712904000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1439226500 # Sum of mem lat for all requests -system.physmem.totBusLat 137135000 # Total cycles spent in databus access -system.physmem.totBankLat 589187500 # Total cycles spent in bank access -system.physmem.avgQLat 25992.78 # Average queueing delay per request -system.physmem.avgBankLat 21482.03 # Average bank access latency per request +system.physmem.totQLat 716281750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests +system.physmem.totBusLat 137140000 # Total cycles spent in databus access +system.physmem.totBankLat 588376250 # Total cycles spent in bank access +system.physmem.avgQLat 26114.98 # Average queueing delay per request +system.physmem.avgBankLat 21451.66 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52474.81 # Average memory access latency +system.physmem.avgMemAccLat 52566.65 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -171,252 +171,252 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 16.63 # Average write queue length over time -system.physmem.readRowHits 17586 # Number of row buffer hits during reads -system.physmem.writeRowHits 1048 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes -system.physmem.avgGap 12927927.19 # Average gap between requests -system.cpu.branchPred.lookups 97754812 # Number of BP lookups -system.cpu.branchPred.condPredicted 88045070 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3614513 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65790839 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65487235 # Number of BTB hits +system.physmem.avgWrQLen 17.33 # Average write queue length over time +system.physmem.readRowHits 17584 # Number of row buffer hits during reads +system.physmem.writeRowHits 1051 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes +system.physmem.avgGap 12926500.80 # Average gap between requests +system.cpu.branchPred.lookups 97760274 # Number of BP lookups +system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.538531 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774641454 # number of cpu cycles simulated +system.cpu.numCycles 774581838 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164855086 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642226882 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97754812 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65488562 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329193327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20835132 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263364086 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2508 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161933823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 733897 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774407665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126639 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445214338 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74055584 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37896707 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077649 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106182 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772378 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11485240 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791473 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146008114 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774407665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126194 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.119983 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215996576 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214396476 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284196048 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42825985 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16992580 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636523781 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16992580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239852916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36748965 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52423247 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302028125 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126361832 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625670094 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30926636 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73309992 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3198488 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356344294 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746400105 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712277962 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34122143 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111573855 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2642593 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271720784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436941817 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179749373 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254480906 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83188791 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512511277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2608080 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459319933 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52996 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109213691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130186216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 364409 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774407665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431122 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2643056 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271532800 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436949673 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179753673 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254530912 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83488154 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512578374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608372 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459383903 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130205744 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774347981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145648239 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184522685 23.83% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209864984 27.10% 69.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131209019 16.94% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70693972 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20392101 2.63% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8014841 1.03% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3879808 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182016 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145644273 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184515384 23.83% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209689604 27.08% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131356597 16.96% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70636694 9.12% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8079794 1.04% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181593 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774407665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774347981 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140362 8.20% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95230 5.57% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1159729 67.79% 81.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315506 18.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95504 5.69% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315646 18.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866449380 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644870 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419102646 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171123037 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459319933 # Type of FU issued -system.cpu.iq.rate 1.883865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1710827 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001172 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676966203 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615362108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443197913 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17845151 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9210352 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8546882 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451899562 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9131198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215327027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued +system.cpu.iq.rate 1.884093 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34428974 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58580 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245871 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12901231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3337 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16992580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3019126 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247748 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608802731 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436941817 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179749373 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2524925 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 149083 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1915 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245871 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2268919 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473448 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3742367 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454001167 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416555573 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5318766 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93683374 # number of nop insts executed -system.cpu.iew.exec_refs 587003910 # number of memory reference insts executed -system.cpu.iew.exec_branches 89035290 # Number of branches executed -system.cpu.iew.exec_stores 170448337 # Number of stores executed -system.cpu.iew.exec_rate 1.876999 # Inst execution rate -system.cpu.iew.wb_sent 1452626666 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451744795 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153395564 # num instructions producing a value -system.cpu.iew.wb_consumers 1204642088 # num instructions consuming a value +system.cpu.iew.exec_nop 93685275 # number of nop insts executed +system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed +system.cpu.iew.exec_branches 89035299 # Number of branches executed +system.cpu.iew.exec_stores 170447970 # Number of stores executed +system.cpu.iew.exec_rate 1.877225 # Inst execution rate +system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153472607 # num instructions producing a value +system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874086 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957459 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119183948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3614513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757415085 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966588 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509597 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757347022 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240000251 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275796766 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42566622 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54725654 7.23% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19677570 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13283245 1.75% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30556171 4.03% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10517669 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70291137 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757415085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,70 +427,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70291137 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295766308 # The number of ROB reads -system.cpu.rob.rob_writes 3234429823 # The number of ROB writes -system.cpu.timesIdled 26016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 233789 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295781723 # The number of ROB reads +system.cpu.rob.rob_writes 3234577019 # The number of ROB writes +system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552846 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979081340 # number of integer regfile reads -system.cpu.int_regfile_writes 1275150411 # number of integer regfile writes -system.cpu.fp_regfile_reads 16965180 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491866 # number of floating regfile writes -system.cpu.misc_regfile_reads 592655969 # number of misc regfile reads +system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads +system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962684 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes +system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1035.615179 # Cycle average of tags in use -system.cpu.icache.total_refs 161931886 # Total number of references to valid blocks. +system.cpu.icache.replacements 197 # number of replacements +system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use +system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121025.325859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.615179 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505671 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505671 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161931886 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161931886 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161931886 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161931886 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161931886 # number of overall hits -system.cpu.icache.overall_hits::total 161931886 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1937 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1937 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1937 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1937 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1937 # number of overall misses -system.cpu.icache.overall_misses::total 1937 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 85579500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 85579500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 85579500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 85579500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 85579500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 85579500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161933823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161933823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161933823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161933823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161933823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161933823 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161939953 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161939953 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161939953 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161939953 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161939953 # number of overall hits +system.cpu.icache.overall_hits::total 161939953 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses +system.cpu.icache.overall_misses::total 1943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84888000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84888000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84888000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84888000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84888000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84888000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161941896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161941896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161941896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161941896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161941896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161941896 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44181.466185 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44181.466185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44181.466185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44181.466185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44181.466185 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43689.140504 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43689.140504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43689.140504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43689.140504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -499,120 +499,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62434000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62434000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62434000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62434000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62434000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62434000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62446000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62446000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46627.333831 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46627.333831 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46627.333831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46627.333831 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46636.295743 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46636.295743 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22454.455372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550476 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24273 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.678532 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22452.577609 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550279 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24276 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.667614 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.724619 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1061.167682 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 648.563071 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633079 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032384 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019793 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685256 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 143 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196431 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196574 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443982 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443982 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240656 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240656 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 143 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437087 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.893204 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056616 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059026 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.893204 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056616 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059026 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49872.909699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100222.109762 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89549.007444 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.176727 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.176727 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76317.059832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49872.909699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77522.778392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76317.059832 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 463251 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 464590 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.895444 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027932 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083000 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083000 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.895444 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056619 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059037 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.895444 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056619 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059037 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49783.569641 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100025.179856 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89357.623517 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73089.114366 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73089.114366 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49783.569641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77657.020855 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76438.548199 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49783.569641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77657.020855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76438.548199 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,160 +623,160 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1196 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4446 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5642 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21785 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21785 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1196 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26231 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27427 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1196 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44803245 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708560252 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1753363497 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022133 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027901 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083009 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083009 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.893204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056616 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44804000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389435638 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434239638 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1322391854 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1322391854 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1711827492 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1756631492 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44804000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1711827492 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1756631492 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.895444 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083000 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.895444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056619 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059037 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.895444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056619 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059037 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37367.806505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87552.976169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76897.403577 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60713.091869 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60713.091869 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37367.806505 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65264.687636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64045.190754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37367.806505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65264.687636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64045.190754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459222 # number of replacements -system.cpu.dcache.tagsinuse 4093.797620 # Cycle average of tags in use -system.cpu.dcache.total_refs 365142346 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463318 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.103087 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459155 # number of replacements +system.cpu.dcache.tagsinuse 4093.797450 # Cycle average of tags in use +system.cpu.dcache.total_refs 365215439 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463251 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.374853 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.797620 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.797450 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200185442 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200185442 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955585 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955585 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200258461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200258461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955659 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955659 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365141027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365141027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365141027 # number of overall hits -system.cpu.dcache.overall_hits::total 365141027 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 923072 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 923072 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1891231 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1891231 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365214120 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365214120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365214120 # number of overall hits +system.cpu.dcache.overall_hits::total 365214120 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 922594 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 922594 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891157 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891157 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2814303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2814303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2814303 # number of overall misses -system.cpu.dcache.overall_misses::total 2814303 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14740246000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14740246000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31916028682 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31916028682 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2813751 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2813751 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2813751 # number of overall misses +system.cpu.dcache.overall_misses::total 2813751 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14741568500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14741568500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31920810636 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31920810636 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46656274682 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46656274682 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46656274682 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46656274682 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201108514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201108514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46662379136 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46662379136 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46662379136 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46662379136 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201181055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201181055 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367955330 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367955330 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367955330 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367955330 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004590 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004590 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368027871 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368027871 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368027871 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368027871 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004586 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004586 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.685000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.685000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16875.796073 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16875.796073 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15978.391904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15978.391904 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16878.985000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16878.985000 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16578.269888 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16578.269888 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16578.269888 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 588860 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35662 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.512254 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16583.691711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16583.691711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590874 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.576166 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443982 # number of writebacks -system.cpu.dcache.writebacks::total 443982 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722195 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722195 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628797 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628797 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2350992 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2350992 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2350992 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2350992 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200877 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200877 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262434 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262434 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443878 # number of writebacks +system.cpu.dcache.writebacks::total 443878 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721765 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721765 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628742 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628742 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2350507 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2350507 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2350507 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2350507 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200829 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200829 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262415 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262415 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463311 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463311 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463311 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463311 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2613052500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2613052500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357141500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2611858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2611858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4360853500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360853500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970194000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6970194000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970194000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6970194000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6972711500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6972711500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6972711500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6972711500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -785,16 +785,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13008.221449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13008.221449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16602.808706 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16602.808706 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.382689 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.382689 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16618.156355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16618.156355 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15044.309330 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15044.309330 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |