diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 91 |
1 files changed, 76 insertions, 15 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 327f1f99e..0ce23ef70 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667477 # Simulator instruction rate (inst/s) -host_op_rate 669461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 927773801 # Simulator tick rate (ticks/s) -host_mem_usage 222564 # Number of bytes of host memory used -host_seconds 2224.96 # Real time elapsed on the host +host_inst_rate 1371910 # Simulator instruction rate (inst/s) +host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1906915769 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 1082.51 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3778240 # Number of bytes written to this memory -system.physmem.num_reads 92343 # Number of read requests responded to by this memory -system.physmem.num_writes 59035 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory +system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1485113012 # nu system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 58503000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 569359660 # nu system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74112 # number of replacements system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 453221 system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |