diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 114 |
1 files changed, 57 insertions, 57 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 607412a81..3078a0fec 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.063178 # Number of seconds simulated -sim_ticks 2063177751000 # Number of ticks simulated -final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2063177737000 # Number of ticks simulated +final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349558 # Simulator instruction rate (inst/s) -host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1874864984 # Simulator tick rate (ticks/s) -host_mem_usage 222108 # Number of bytes of host memory used -host_seconds 1100.44 # Real time elapsed on the host -sim_insts 1485108101 # Number of instructions simulated -sim_ops 1489523295 # Number of ops (including micro ops) simulated +host_inst_rate 1527975 # Simulator instruction rate (inst/s) +host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2122729697 # Simulator tick rate (ticks/s) +host_mem_usage 231576 # Number of bytes of host memory used +host_seconds 971.95 # Real time elapsed on the host +sim_insts 1485108088 # Number of instructions simulated +sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 31858 # To system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4126355502 # number of cpu cycles simulated +system.cpu.numCycles 4126355474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108101 # Number of instructions committed -system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.committedInsts 1485108088 # Number of instructions committed +system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481286 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written +system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365767 # number of memory refs -system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365766 # number of memory refs +system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4126355502 # Number of busy cycles +system.cpu.num_busy_cycles 4126355474 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use -system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits -system.cpu.icache.overall_hits::total 1485111905 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits +system.cpu.icache.overall_hits::total 1485111892 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 58777000 system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses @@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits -system.cpu.dcache.overall_hits::total 568906446 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits +system.cpu.dcache.overall_hits::total 568906445 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses @@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses @@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy |