diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86/linux/simple-timing')
4 files changed, 44 insertions, 43 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 5736b9341..cec3db95e 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr index f5691fd64..e45cd058f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 5f5879b0d..01addadef 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:22:44 +gem5 compiled Mar 11 2013 13:21:48 +gem5 started Mar 11 2013 13:30:24 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1800193397000 because target called exit() +Exiting @ tick 1800193398000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 088aad8da..2279afb65 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.800193 # Number of seconds simulated -sim_ticks 1800193397000 # Number of ticks simulated -final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1800193398000 # Number of ticks simulated +final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 575805 # Simulator instruction rate (inst/s) -host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1177876462 # Simulator tick rate (ticks/s) -host_mem_usage 292800 # Number of bytes of host memory used -host_seconds 1528.34 # Real time elapsed on the host +host_inst_rate 392596 # Simulator instruction rate (inst/s) +host_op_rate 723379 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 803099848 # Simulator tick rate (ticks/s) +host_mem_usage 292568 # Number of bytes of host memory used +host_seconds 2241.56 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated -sim_ops 1621493927 # Number of ops (including micro ops) simulated +sim_ops 1621493928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory @@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 25668 # To system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3600386794 # number of cpu cycles simulated +system.cpu.numCycles 3600386796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed -system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses +system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354438 # number of integer instructions +system.cpu.num_int_insts 1621354440 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read -system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written +system.cpu.num_int_register_reads 4204103517 # number of times the integer registers were read +system.cpu.num_int_register_writes 1886895260 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228179 # number of memory refs -system.cpu.num_load_insts 419042121 # Number of load instructions +system.cpu.num_mem_refs 607228180 # number of memory refs +system.cpu.num_load_insts 419042122 # Number of load instructions system.cpu.num_store_insts 188186058 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3600386794 # Number of busy cycles +system.cpu.num_busy_cycles 3600386796 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197305 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.197305 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits @@ -136,12 +136,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2532 # number of replacements -system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22211.029315 # Cycle average of tags in use system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21021.301343 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy @@ -271,22 +271,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.905740 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786132 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1372.670235 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 771788000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905740 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 418844796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits -system.cpu.dcache.overall_hits::total 606786131 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 606786132 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786132 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786132 # number of overall hits +system.cpu.dcache.overall_hits::total 606786132 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses @@ -303,14 +303,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 419042122 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042122 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 607228180 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228180 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228180 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228180 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses |