diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/x86')
6 files changed, 180 insertions, 54 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 7b2a9ad59..5eab9f73c 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:07:25 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 639bcc189..26e1be238 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.636988 # Nu sim_ticks 636988382500 # Number of ticks simulated final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71818 # Simulator instruction rate (inst/s) -host_op_rate 132329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51984066 # Simulator tick rate (ticks/s) -host_mem_usage 250428 # Number of bytes of host memory used -host_seconds 12253.53 # Real time elapsed on the host +host_inst_rate 63436 # Simulator instruction rate (inst/s) +host_op_rate 116883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45916521 # Simulator tick rate (ticks/s) +host_mem_usage 227532 # Number of bytes of host memory used +host_seconds 13872.75 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3731712 # Number of bytes written to this memory -system.physmem.num_reads 91157 # Number of read requests responded to by this memory -system.physmem.num_writes 58308 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9158798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 15017166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory +system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory +system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory +system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1273976766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -322,11 +335,17 @@ system.cpu.icache.demand_accesses::total 186830267 # nu system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,11 +373,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32805000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 445407 # number of replacements system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use @@ -402,13 +427,21 @@ system.cpu.dcache.demand_accesses::total 453124365 # nu system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,13 +477,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 72883 # number of replacements system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use @@ -519,18 +560,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 449505 system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,18 +614,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 87bcc8171..db4607fa4 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:08:17 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 14740711a..0e02ab2e6 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 688761 # Simulator instruction rate (inst/s) -host_op_rate 1269079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 754478822 # Simulator tick rate (ticks/s) -host_mem_usage 239576 # Number of bytes of host memory used -host_seconds 1277.69 # Real time elapsed on the host +host_inst_rate 1254577 # Simulator instruction rate (inst/s) +host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1374282564 # Simulator tick rate (ticks/s) +host_mem_usage 216676 # Number of bytes of host memory used +host_seconds 701.45 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11334586825 # Number of bytes read from this memory -system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory -system.physmem.bytes_written 864451000 # Number of bytes written to this memory -system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory -system.physmem.num_writes 188186057 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory +system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory +system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 9ebad8844..7f0dbded6 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:13:02 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 4294088ef..00ab9a331 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 617600 # Simulator instruction rate (inst/s) -host_op_rate 1137962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1265523884 # Simulator tick rate (ticks/s) -host_mem_usage 248496 # Number of bytes of host memory used -host_seconds 1424.91 # Real time elapsed on the host +host_inst_rate 587265 # Simulator instruction rate (inst/s) +host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1203364849 # Simulator tick rate (ticks/s) +host_mem_usage 225604 # Number of bytes of host memory used +host_seconds 1498.51 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5725952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3712448 # Number of bytes written to this memory -system.physmem.num_reads 89468 # Number of read requests responded to by this memory -system.physmem.num_writes 58007 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory +system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory +system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1186516740 # nu system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38266000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 607228182 # nu system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71208 # number of replacements system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 442048 system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |