diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
10 files changed, 2324 insertions, 2311 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 26d645fed..f0d94be3d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:21 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:26 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274500333500 because target called exit() +Exiting @ tick 274300226500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 1a8f04561..206fd9b5c 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274500 # Number of seconds simulated -sim_ticks 274500333500 # Number of ticks simulated -final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274300 # Number of seconds simulated +sim_ticks 274300226500 # Number of ticks simulated +final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160535 # Simulator instruction rate (inst/s) -host_op_rate 160535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73218214 # Simulator tick rate (ticks/s) +host_inst_rate 157937 # Simulator instruction rate (inst/s) +host_op_rate 157937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71980747 # Simulator tick rate (ticks/s) host_mem_usage 209892 # Number of bytes of host memory used -host_seconds 3749.07 # Real time elapsed on the host +host_seconds 3810.74 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894016 # Number of bytes read from this memory +system.physmem.bytes_read 5894080 # Number of bytes read from this memory system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798080 # Number of bytes written to this memory -system.physmem.num_reads 92094 # Number of read requests responded to by this memory -system.physmem.num_writes 59345 # Number of write requests responded to by this memory +system.physmem.bytes_written 3798144 # Number of bytes written to this memory +system.physmem.num_reads 92095 # Number of read requests responded to by this memory +system.physmem.num_writes 59346 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517577 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39666597 # DTB write hits +system.cpu.dtb.read_accesses 114520208 # DTB read accesses +system.cpu.dtb.write_hits 39666608 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668899 # DTB write accesses -system.cpu.dtb.data_hits 154184165 # DTB hits +system.cpu.dtb.write_accesses 39668910 # DTB write accesses +system.cpu.dtb.data_hits 154184185 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189098 # DTB accesses -system.cpu.itb.fetch_hits 27986226 # ITB hits +system.cpu.dtb.data_accesses 154189118 # DTB accesses +system.cpu.itb.fetch_hits 25020502 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 27986248 # ITB accesses +system.cpu.itb.fetch_accesses 25020524 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 549000668 # number of cpu cycles simulated +system.cpu.numCycles 548600454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. -system.cpu.activity 89.164571 # Percentage of cycles cpu is active +system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. +system.cpu.activity 89.165242 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads -system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits +system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154582342 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051949 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use -system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use +system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits -system.cpu.icache.overall_hits::total 27985205 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses -system.cpu.icache.overall_misses::total 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits +system.cpu.icache.overall_hits::total 25019479 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses +system.cpu.icache.overall_misses::total 1021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.126386 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394244 # number of overall hits -system.cpu.dcache.overall_hits::total 152394244 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits +system.cpu.dcache.overall_hits::total 152394215 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177586 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571119 # number of overall misses -system.cpu.dcache.overall_misses::total 1571119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33395984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses +system.cpu.dcache.overall_misses::total 1571148 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029849 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks -system.cpu.dcache.writebacks::total 408188 # number of writebacks +system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks +system.cpu.dcache.writebacks::total 408190 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -269,75 +269,75 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562138000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466740000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # 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Cycle average of tags in use +system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses +system.cpu.l2cache.overall_misses::total 92095 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -345,65 +345,65 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks -system.cpu.l2cache.writebacks::total 59345 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks +system.cpu.l2cache.writebacks::total 59346 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index e473c70fd..2e14d6c64 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:10:26 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:40 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 144450185500 because target called exit() +Exiting @ tick 134621123500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 6a8942beb..001739477 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144450 # Number of seconds simulated -sim_ticks 144450185500 # Number of ticks simulated -final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134621 # Number of seconds simulated +sim_ticks 134621123500 # Number of ticks simulated +final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 270959 # Simulator instruction rate (inst/s) -host_op_rate 270959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69206896 # Simulator tick rate (ticks/s) -host_mem_usage 211048 # Number of bytes of host memory used -host_seconds 2087.22 # Real time elapsed on the host +host_inst_rate 282179 # Simulator instruction rate (inst/s) +host_op_rate 282179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67168296 # Simulator tick rate (ticks/s) +host_mem_usage 211096 # Number of bytes of host memory used +host_seconds 2004.24 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5936768 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797120 # Number of bytes written to this memory -system.physmem.num_reads 92762 # Number of read requests responded to by this memory -system.physmem.num_writes 59330 # Number of write requests responded to by this memory +system.physmem.bytes_read 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3797952 # Number of bytes written to this memory +system.physmem.num_reads 92775 # Number of read requests responded to by this memory +system.physmem.num_writes 59343 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125584378 # DTB read hits -system.cpu.dtb.read_misses 26780 # DTB read misses +system.cpu.dtb.read_hits 123836708 # DTB read hits +system.cpu.dtb.read_misses 23555 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125611158 # DTB read accesses -system.cpu.dtb.write_hits 41433696 # DTB write hits -system.cpu.dtb.write_misses 32002 # DTB write misses +system.cpu.dtb.read_accesses 123860263 # DTB read accesses +system.cpu.dtb.write_hits 40831838 # DTB write hits +system.cpu.dtb.write_misses 31545 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41465698 # DTB write accesses -system.cpu.dtb.data_hits 167018074 # DTB hits -system.cpu.dtb.data_misses 58782 # DTB misses +system.cpu.dtb.write_accesses 40863383 # DTB write accesses +system.cpu.dtb.data_hits 164668546 # DTB hits +system.cpu.dtb.data_misses 55100 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167076856 # DTB accesses -system.cpu.itb.fetch_hits 70952399 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 164723646 # DTB accesses +system.cpu.itb.fetch_hits 66483943 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 70952439 # ITB accesses +system.cpu.itb.fetch_accesses 66483980 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 288900372 # number of cpu cycles simulated +system.cpu.numCycles 269242248 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits +system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued -system.cpu.iq.rate 2.148217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued +system.cpu.iq.rate 2.259665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45034525 # number of nop insts executed -system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed -system.cpu.iew.exec_branches 68658345 # Number of branches executed -system.cpu.iew.exec_stores 41485194 # Number of stores executed -system.cpu.iew.exec_rate 2.122282 # Inst execution rate -system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420036286 # num instructions producing a value -system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value +system.cpu.iew.exec_nop 43926324 # number of nop insts executed +system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed +system.cpu.iew.exec_branches 67006670 # Number of branches executed +system.cpu.iew.exec_stores 40880471 # Number of stores executed +system.cpu.iew.exec_rate 2.238049 # Inst execution rate +system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417486240 # num instructions producing a value +system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back +system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 935932678 # The number of ROB reads -system.cpu.rob.rob_writes 1385724156 # The number of ROB writes -system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 898866221 # The number of ROB reads +system.cpu.rob.rob_writes 1350401622 # The number of ROB writes +system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads -system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 863490102 # number of integer regfile reads -system.cpu.int_regfile_writes 500818441 # number of integer regfile writes -system.cpu.fp_regfile_reads 272 # number of floating regfile reads +system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads +system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848641681 # number of integer regfile reads +system.cpu.int_regfile_writes 492726607 # number of integer regfile writes +system.cpu.fp_regfile_reads 387 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use -system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. +system.cpu.icache.replacements 49 # number of replacements +system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use +system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 801.236568 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.391229 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.391229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 70951127 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70951127 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70951127 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70951127 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70951127 # number of overall hits -system.cpu.icache.overall_hits::total 70951127 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1272 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1272 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1272 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1272 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1272 # number of overall misses -system.cpu.icache.overall_misses::total 1272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45919500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45919500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45919500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45919500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45919500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70952399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70952399 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70952399 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70952399 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70952399 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000018 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits +system.cpu.icache.overall_hits::total 66482496 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses +system.cpu.icache.overall_misses::total 1447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,245 +371,253 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 944 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 944 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 944 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33676000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470690 # number of replacements -system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use -system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.940031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 113064898 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113064898 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38147626 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38147626 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 151212524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151212524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151212524 # number of overall hits -system.cpu.dcache.overall_hits::total 151212524 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 732041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 732041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1303695 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1303695 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2035736 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2035736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2035736 # number of overall misses -system.cpu.dcache.overall_misses::total 2035736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11783533000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19632740219 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31416273219 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31416273219 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31416273219 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 113796939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113796939 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460743 # number of replacements +system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use +system.cpu.dcache.total_refs 149091432 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464839 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 320.737787 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126301000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.783086 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999459 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 110940808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 110940808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38150562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits +system.cpu.dcache.overall_hits::total 149091370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses +system.cpu.dcache.overall_misses::total 2023111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31385446422 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31385446422 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31385446422 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111663160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111663160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153248260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153248260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153248260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153248260 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033046 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 423044 # number of writebacks -system.cpu.dcache.writebacks::total 423044 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 513277 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 513277 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1047673 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1560950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1560950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1560950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 218764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 218764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 256022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 256022 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 474786 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 474786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 474786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1640072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3027658494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4667730994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4667730994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003098 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7496.994478 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9831.231321 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks +system.cpu.dcache.writebacks::total 415225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74463 # number of replacements -system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74480 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index c2143f70c..4180d507c 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:39:44 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:00:24 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 177116942500 because target called exit() +Exiting @ tick 164280509500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index e204ea2b2..65753c5e3 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.177117 # Number of seconds simulated -sim_ticks 177116942500 # Number of ticks simulated -final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164281 # Number of seconds simulated +sim_ticks 164280509500 # Number of ticks simulated +final_tick 164280509500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193712 # Simulator instruction rate (inst/s) -host_op_rate 204690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60186856 # Simulator tick rate (ticks/s) -host_mem_usage 223404 # Number of bytes of host memory used -host_seconds 2942.78 # Real time elapsed on the host -sim_insts 570051603 # Number of instructions simulated -sim_ops 602359810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5833792 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3720320 # Number of bytes written to this memory -system.physmem.num_reads 91153 # Number of read requests responded to by this memory -system.physmem.num_writes 58130 # Number of write requests responded to by this memory +host_inst_rate 203818 # Simulator instruction rate (inst/s) +host_op_rate 215370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58737354 # Simulator tick rate (ticks/s) +host_mem_usage 223536 # Number of bytes of host memory used +host_seconds 2796.87 # Real time elapsed on the host +sim_insts 570051663 # Number of instructions simulated +sim_ops 602359870 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5845888 # Number of bytes read from this memory +system.physmem.bytes_inst_read 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3721728 # Number of bytes written to this memory +system.physmem.num_reads 91342 # Number of read requests responded to by this memory +system.physmem.num_writes 58152 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 32937515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 265226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 21004879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 53942395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35584793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 300754 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22654714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58239508 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 354233886 # number of cpu cycles simulated +system.cpu.numCycles 328561020 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91144697 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 84232652 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4003225 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 86347481 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 80064419 # Number of BTB hits +system.cpu.BPredUnit.lookups 85502166 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80303538 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2364558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47128818 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46810492 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1704141 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1603 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 76798037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 703840817 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91144697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81768560 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 159197395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18458844 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 103018501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 74422546 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1338162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127927 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980484 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441322 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2014 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68931697 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669727391 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85502166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48251814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130042659 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13473975 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117702916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67497554 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807456 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.177756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200257 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194196282 54.95% 54.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25625707 7.25% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19294200 5.46% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24432014 6.91% 74.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11774546 3.33% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13391437 3.79% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4604134 1.30% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7796226 2.21% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52278982 14.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197667987 60.32% 60.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955558 6.39% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944545 1.51% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317291 4.37% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8979833 2.74% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9404994 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4387469 1.34% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814392 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61238365 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 353393528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257301 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 98941962 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83442113 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 137180071 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19452898 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14376484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6300700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2518 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 740147617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7037 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14376484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 111904204 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9631562 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118839 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 143566748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73795691 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 727217623 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 278 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59684680 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10267337 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 752950298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3380504235 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3380504107 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327710434 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260232 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038365 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93127005 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94874868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108614475 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20063382 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11030704 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784748 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1773 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706010986 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5362 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11030704 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107410901 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13982712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118932 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114322879 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80844306 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697216799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59255173 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19368550 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 660 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723821711 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241352610 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241352482 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 125532896 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13135 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 13128 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 131736703 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 179759563 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 82851365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19142240 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24648771 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 702464419 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9443 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 663065354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 737309 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 99563138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 237077273 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3096 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 353393528 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876280 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.733355 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417498 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96404213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11540 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169974240 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172906537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80619433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21532364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27969964 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681972253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9148 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646841509 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79435960 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197814866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2789 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327710434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.973820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.737996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 85420653 24.17% 24.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90592891 25.64% 49.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76061550 21.52% 71.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 42517322 12.03% 83.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 25489615 7.21% 90.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18140901 5.13% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7279964 2.06% 97.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6670408 1.89% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1220224 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68514298 20.91% 20.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84850419 25.89% 46.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75242172 22.96% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40564366 12.38% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28638763 8.74% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15215694 4.64% 95.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5886369 1.80% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6524912 1.99% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2273441 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 353393528 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327710434 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 202199 4.87% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2984693 71.84% 76.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 967527 23.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205233 5.10% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2909479 72.37% 77.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 905756 22.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412589272 62.22% 62.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172499638 26.02% 88.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 77969869 11.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403929410 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6579 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166116267 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76789250 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 663065354 # Type of FU issued -system.cpu.iq.rate 1.871829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4154419 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006265 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1684415928 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 802048612 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650214601 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646841509 # Type of FU issued +system.cpu.iq.rate 1.968710 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4020468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006216 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626837984 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761428768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638548229 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 667219753 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650861957 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 29667951 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30419634 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30806967 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 225012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11842 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12630350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23953929 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 128648 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11649 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10398406 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13680 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12577 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12456 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14376484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 831826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 58719 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 702543187 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1852399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 179759563 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 82851365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 8113 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13094 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5271 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11842 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4161334 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494337 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4655671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656082264 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169130146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6983090 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11030704 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 854813 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 57677 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682047620 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 663984 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172906537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80619433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7812 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4667 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11649 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1314819 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1584401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2899220 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642689835 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163986431 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4151674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69325 # number of nop insts executed -system.cpu.iew.exec_refs 245820033 # number of memory reference insts executed -system.cpu.iew.exec_branches 76462484 # Number of branches executed -system.cpu.iew.exec_stores 76689887 # Number of stores executed -system.cpu.iew.exec_rate 1.852116 # Inst execution rate -system.cpu.iew.wb_sent 652222843 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650214617 # cumulative count of insts written-back -system.cpu.iew.wb_producers 423345319 # num instructions producing a value -system.cpu.iew.wb_consumers 657402766 # num instructions consuming a value +system.cpu.iew.exec_nop 66219 # number of nop insts executed +system.cpu.iew.exec_refs 239991845 # number of memory reference insts executed +system.cpu.iew.exec_branches 74670108 # Number of branches executed +system.cpu.iew.exec_stores 76005414 # Number of stores executed +system.cpu.iew.exec_rate 1.956075 # Inst execution rate +system.cpu.iew.wb_sent 640041427 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638548245 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420154647 # num instructions producing a value +system.cpu.iew.wb_consumers 654937446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943469 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641519 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 339017045 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.776783 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.152670 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570051714 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359921 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79697124 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6359 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2424958 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316679731 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108187576 31.91% 31.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 106522126 31.42% 63.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49316522 14.55% 77.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9859363 2.91% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23336266 6.88% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14305882 4.22% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7916477 2.34% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1329398 0.39% 94.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18243435 5.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92723381 29.28% 29.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103992421 32.84% 62.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43071500 13.60% 75.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8912974 2.81% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25679598 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13104188 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7581196 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156714 0.37% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20457759 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051654 # Number of instructions committed -system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316679731 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051714 # Number of instructions committed +system.cpu.commit.committedOps 602359921 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173611 # Number of memory references committed -system.cpu.commit.loads 148952596 # Number of loads committed +system.cpu.commit.refs 219173635 # Number of memory references committed +system.cpu.commit.loads 148952608 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828603 # Number of branches committed +system.cpu.commit.branches 70828615 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522695 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18243435 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20457759 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1023326216 # The number of ROB reads -system.cpu.rob.rob_writes 1419524916 # The number of ROB writes -system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051603 # Number of Instructions Simulated -system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated -system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads -system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads -system.cpu.int_regfile_writes 676006750 # number of integer regfile writes +system.cpu.rob.rob_reads 978278405 # The number of ROB reads +system.cpu.rob.rob_writes 1375177371 # The number of ROB writes +system.cpu.timesIdled 40898 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850586 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051663 # Number of Instructions Simulated +system.cpu.committedOps 602359870 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051663 # Number of Instructions Simulated +system.cpu.cpi 0.576371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576371 # CPI: Total CPI of All Threads +system.cpu.ipc 1.734995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.734995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210435772 # number of integer regfile reads +system.cpu.int_regfile_writes 664215714 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 943708295 # number of misc regfile reads -system.cpu.misc_regfile_writes 2660 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 657.275674 # Cycle average of tags in use -system.cpu.icache.total_refs 74421550 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905058829 # number of misc regfile reads +system.cpu.misc_regfile_writes 2684 # number of misc regfile writes +system.cpu.icache.replacements 57 # number of replacements +system.cpu.icache.tagsinuse 691.796995 # Cycle average of tags in use +system.cpu.icache.total_refs 67496461 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 810 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83328.964198 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 74421550 # number of overall hits -system.cpu.icache.overall_hits::total 74421550 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 996 # number of overall misses -system.cpu.icache.overall_misses::total 996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 74422546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 74422546 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 74422546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 74422546 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 74422546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000013 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 691.796995 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67496461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67496461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67496461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67496461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67496461 # number of overall hits +system.cpu.icache.overall_hits::total 67496461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1093 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1093 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1093 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.icache.overall_misses::total 1093 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37450500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37450500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37450500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37450500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37450500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67497554 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67497554 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67497554 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67497554 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67497554 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34263.952425 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,269 +381,270 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 231 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 231 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 231 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 231 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 231 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 765 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 765 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 765 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 765 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 765 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 765 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26235000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26235000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26235000 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 811 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 811 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 811 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 811 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 811 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27589000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27589000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27589000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27589000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34018.495684 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441200 # number of replacements -system.cpu.dcache.tagsinuse 4094.750887 # Cycle average of tags in use -system.cpu.dcache.total_refs 205785268 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445296 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 462.131409 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87972000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.750887 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137930344 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137930344 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67852261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67852261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1329 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1329 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 205782605 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 205782605 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 205782605 # number of overall hits -system.cpu.dcache.overall_hits::total 205782605 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 248964 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 248964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1565270 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1565270 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 9 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 9 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 249332 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 249332 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543912 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1793244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1793244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1793244 # number of overall misses +system.cpu.dcache.overall_misses::total 1793244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3286822500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27023570462 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30310392962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30310392962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30310392962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132322362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132322362 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008739 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008739 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1473 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201739893 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201739893 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201739893 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201739893 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022241 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008889 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13182.513677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17503.310073 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16902.548098 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9610962 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2243 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4284.869371 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 395250 # number of writebacks -system.cpu.dcache.writebacks::total 395250 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51046 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51046 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1317892 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1368938 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1368938 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1368938 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197918 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197918 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247378 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247378 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 445296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 445296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 445296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1625205500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2544318027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4169523527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4169523527 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002145 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8211.509312 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9363.487494 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 394903 # number of writebacks +system.cpu.dcache.writebacks::total 394903 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51902 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1296808 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3108568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3135095000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 810 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 197428 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 198238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 394903 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247105 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 810 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 444533 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445343 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 810 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 444533 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445343 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.953086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163498 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.953086 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.203764 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.953086 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.203764 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34361.398964 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34325.288888 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.711583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34361.398964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.480901 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1658000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 329 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5039.513678 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks -system.cpu.l2cache.writebacks::total 58130 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 58152 # number of writebacks +system.cpu.l2cache.writebacks::total 58152 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33041 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58301 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91342 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24032500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027503500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820086500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24032500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2847590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24032500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2847590000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31130.181347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31097.059097 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.786985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 337dcecf7..709a4d648 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:56:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:18:25 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 408816360000 because target called exit() +Exiting @ tick 388554296500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 3c7a99cbd..dd253efff 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,266 +1,266 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408816 # Number of seconds simulated -sim_ticks 408816360000 # Number of ticks simulated -final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.388554 # Number of seconds simulated +sim_ticks 388554296500 # Number of ticks simulated +final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218783 # Simulator instruction rate (inst/s) -host_op_rate 219472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63832966 # Simulator tick rate (ticks/s) -host_mem_usage 214000 # Number of bytes of host memory used -host_seconds 6404.47 # Real time elapsed on the host +host_inst_rate 229375 # Simulator instruction rate (inst/s) +host_op_rate 230098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63606554 # Simulator tick rate (ticks/s) +host_mem_usage 214136 # Number of bytes of host memory used +host_seconds 6108.71 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 6021376 # Number of bytes read from this memory -system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3792448 # Number of bytes written to this memory -system.physmem.num_reads 94084 # Number of read requests responded to by this memory -system.physmem.num_writes 59257 # Number of write requests responded to by this memory +system.physmem.bytes_read 5987456 # Number of bytes read from this memory +system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3788160 # Number of bytes written to this memory +system.physmem.num_reads 93554 # Number of read requests responded to by this memory +system.physmem.num_writes 59190 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 817632721 # number of cpu cycles simulated +system.cpu.numCycles 777108594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103174324 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92051331 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5438120 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 100325127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 99277633 # Number of BTB hits +system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 220 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 175005792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1720391035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103174324 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99278863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 370286255 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31094297 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 246539947 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1680 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 170773896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 991956 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.110623 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.012258 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446988679 54.69% 54.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82419688 10.08% 64.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45028734 5.51% 70.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23714407 2.90% 73.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33177153 4.06% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33877408 4.15% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14961867 1.83% 83.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7384305 0.90% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 129722693 15.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 817274934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126187 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.104112 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 224321388 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 200349407 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 337624010 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 29538890 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 25441239 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1710162106 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 25441239 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255728945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34334751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55175561 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334633255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111961183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1694040603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27905496 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 64677715 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3154928 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1413596061 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2861791975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2827818793 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973182 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 168825609 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3228150 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3270628 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 258968806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 454536844 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 185491805 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 260927641 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 90896258 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1566773345 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3062819 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1493172729 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111198 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 163655037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 180232812 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 819148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 817274934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.827014 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.412188 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168134039 20.57% 20.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190992211 23.37% 43.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210117454 25.71% 69.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 154482053 18.90% 88.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 65263213 7.99% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16377311 2.00% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7979086 0.98% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3751008 0.46% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 178559 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 817274934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154618 7.33% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 176227 8.36% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1421289 67.40% 83.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 356622 16.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 886609078 59.38% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623677 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 430399729 28.82% 88.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173540245 11.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1493172729 # Type of FU issued -system.cpu.iq.rate 1.826214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2108756 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3787980335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1724526520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1473498966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17860011 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9206634 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8523998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1486074999 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9206486 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 205830187 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued +system.cpu.iq.rate 1.879873 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 52024000 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213849 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 253991 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18643663 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 681 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45180 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 25441239 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2526766 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 145081 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1668881823 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4258646 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 454536844 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 185491805 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2961001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 253991 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5294422 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 459505 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5753927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1485801812 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427360543 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7370917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99045659 # number of nop insts executed -system.cpu.iew.exec_refs 599531836 # number of memory reference insts executed -system.cpu.iew.exec_branches 90620288 # Number of branches executed -system.cpu.iew.exec_stores 172171293 # Number of stores executed -system.cpu.iew.exec_rate 1.817200 # Inst execution rate -system.cpu.iew.wb_sent 1483493878 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1482022964 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1178273779 # num instructions producing a value -system.cpu.iew.wb_consumers 1228157747 # num instructions consuming a value +system.cpu.iew.exec_nop 94187571 # number of nop insts executed +system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed +system.cpu.iew.exec_branches 89112581 # Number of branches executed +system.cpu.iew.exec_stores 170576694 # Number of stores executed +system.cpu.iew.exec_rate 1.872734 # Inst execution rate +system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154378236 # num instructions producing a value +system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back +system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 791834306 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.881105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.451655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 260467018 32.89% 32.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288028220 36.37% 69.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 45072234 5.69% 74.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56206737 7.10% 82.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24021941 3.03% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8787658 1.11% 86.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30300633 3.83% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10698376 1.35% 91.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68251489 8.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -271,64 +271,64 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68251489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2392297077 # The number of ROB reads -system.cpu.rob.rob_writes 3363039880 # The number of ROB writes -system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2302721032 # The number of ROB reads +system.cpu.rob.rob_writes 3245242057 # The number of ROB writes +system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.583528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.713714 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.713714 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads -system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes -system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads -system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes -system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads +system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads +system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads +system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes +system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads +system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes +system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 166 # number of replacements -system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use -system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use +system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1031.400456 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.503614 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.503614 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 170772098 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170772098 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170772098 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170772098 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170772098 # number of overall hits -system.cpu.icache.overall_hits::total 170772098 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1798 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1798 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1798 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1798 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1798 # number of overall misses -system.cpu.icache.overall_misses::total 1798 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62741500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62741500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62741500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62741500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62741500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170773896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170773896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170773896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170773896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170773896 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits +system.cpu.icache.overall_hits::total 162821549 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses +system.cpu.icache.overall_misses::total 1976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -337,214 +337,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 499 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 499 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 499 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 499 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 499 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45206000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45206000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45206000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45206000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475353 # number of replacements -system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use -system.cpu.dcache.total_refs 385593109 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.165283 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 220654856 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 220654856 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164936934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164936934 # number of WriteReq hits +system.cpu.dcache.replacements 458031 # number of replacements +system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use +system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 385591790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 385591790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 385591790 # number of overall hits -system.cpu.dcache.overall_hits::total 385591790 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 815916 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 815916 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1909882 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1909882 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits +system.cpu.dcache.overall_hits::total 365777354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2725798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2725798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2725798 # number of overall misses -system.cpu.dcache.overall_misses::total 2725798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11966603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29861651909 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 268000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41828254909 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41828254909 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41828254909 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 221470772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 221470772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses +system.cpu.dcache.overall_misses::total 2675956 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 388317588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 388317588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 388317588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 388317588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003684 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011447 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 426654 # number of writebacks -system.cpu.dcache.writebacks::total 426654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642625 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 267257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks +system.cpu.dcache.writebacks::total 413195 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75859 # number of replacements -system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464590 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75325 # number of replacements +system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use +system.cpu.l2cache.total_refs 440162 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90846 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.845145 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 179822 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 426654 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,44 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks -system.cpu.l2cache.writebacks::total 59257 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # 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average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 59190 # number of writebacks +system.cpu.l2cache.writebacks::total 59190 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1329 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32167 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 60058 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 93554 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1329 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 93554 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41203500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 997353500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1038557000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1880936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2878289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2919493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41203500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dd2c66002..0aefca8ea 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:08:06 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:30:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -19,9 +19,9 @@ info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 -info: Increasing stack size by one page. Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 586834596000 because target called exit() +Exiting @ tick 637054100000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index db3272b03..b9dc005fb 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,265 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.586835 # Number of seconds simulated -sim_ticks 586834596000 # Number of ticks simulated -final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.637054 # Number of seconds simulated +sim_ticks 637054100000 # Number of ticks simulated +final_tick 637054100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106927 # Simulator instruction rate (inst/s) -host_op_rate 197018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71302744 # Simulator tick rate (ticks/s) -host_mem_usage 220908 # Number of bytes of host memory used -host_seconds 8230.18 # Real time elapsed on the host +host_inst_rate 99624 # Simulator instruction rate (inst/s) +host_op_rate 183562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72118142 # Simulator tick rate (ticks/s) +host_mem_usage 221144 # Number of bytes of host memory used +host_seconds 8833.48 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5879616 # Number of bytes read from this memory -system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3743488 # Number of bytes written to this memory -system.physmem.num_reads 91869 # Number of read requests responded to by this memory -system.physmem.num_writes 58492 # Number of write requests responded to by this memory +system.physmem.bytes_read 5835840 # Number of bytes read from this memory +system.physmem.bytes_inst_read 58688 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3733184 # Number of bytes written to this memory +system.physmem.num_reads 91185 # Number of read requests responded to by this memory +system.physmem.num_writes 58331 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10019205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 97172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6379119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 16398324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 9160666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 92124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5860074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 15020740 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1173669193 # number of cpu cycles simulated +system.cpu.numCycles 1274108201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 140536614 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 140536614 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7896314 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 133769291 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 132901689 # Number of BTB hits +system.cpu.BPredUnit.lookups 154805091 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 154805091 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26670333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76796607 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76433583 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 138231227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1143529036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 140536614 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132901689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330118681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 56348337 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 656952944 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 136534174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2392311 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.778199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.100517 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180707581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491843077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 154805091 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76433583 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402290589 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93779674 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 624095429 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1350 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186629859 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9332096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.001845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.237422 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 846464435 72.13% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 17271965 1.47% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15892053 1.35% 74.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 19142892 1.63% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23218397 1.98% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16689415 1.42% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 22145456 1.89% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30830267 2.63% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 181919905 15.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878972627 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24230578 1.90% 70.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15474142 1.21% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17847771 1.40% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26734269 2.10% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18266815 1.43% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28459666 2.23% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39787641 3.12% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224272222 17.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1173574785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119741 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.974320 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 240018155 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 564065687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 224667967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 96551481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 48271495 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2053347825 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 48271495 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 288250921 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 136396250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3594 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 255481832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 445170693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2022383034 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 772 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278054588 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 132157059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2011799289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4917261318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4917257566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1274045731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121501 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.170892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300115536 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537090427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281718880 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88170292 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66950596 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2369584116 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66950596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352574967 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124103280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302559797 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427854412 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2273931919 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293394028 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103133099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2267658104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5579907383 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5579899199 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8184 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 393804639 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 795963127 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 515675644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225280197 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 353360778 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147850226 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1972232230 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 190 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1776284004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 173989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 350598274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 640215855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1173574785 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.513567 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.313751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 649663454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 100 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745849512 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 546580267 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222259773 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352635383 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146994929 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027928806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 590 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785553597 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119193 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 406267408 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 856006289 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1274045731 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.401483 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.311552 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268099715 22.84% 22.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 420406461 35.82% 58.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 239398162 20.40% 79.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 159391711 13.58% 92.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 48358537 4.12% 96.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24330955 2.07% 98.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11625243 0.99% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1646303 0.14% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 317698 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347008054 27.24% 27.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447518543 35.13% 62.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243291159 19.10% 81.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151236902 11.87% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40950901 3.21% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32374953 2.54% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9944821 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1368449 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351949 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1173574785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1274045731 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 185497 7.34% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2190114 86.61% 93.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153108 6.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 236653 9.21% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2158500 84.00% 93.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 174415 6.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26819156 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1098315644 61.83% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 456429787 25.70% 89.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194719417 10.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46809774 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1066762754 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479507335 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192473734 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1776284004 # Type of FU issued -system.cpu.iq.rate 1.513445 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2528719 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4728845466 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2323038766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1755173186 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1751993548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 207962564 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785553597 # Type of FU issued +system.cpu.iq.rate 1.401414 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2569568 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001439 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4847841100 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2434377268 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1726804996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2320 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741313206 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 185 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208932159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 96633519 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 76725 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 215178 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37094140 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 127538142 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36788 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189688 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34073716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2016 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 48271495 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1965747 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154206 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1972232420 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7113535 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 515675644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225280197 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 69568 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 118 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 215178 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4620478 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3457907 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8078385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1762068190 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 450602678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 14215814 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66950596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 381980 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88146 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027929396 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63814072 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 546580267 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222259773 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48025 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189688 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2136326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24658477 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26794803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767571508 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473890078 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17982089 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 644481818 # number of memory reference insts executed -system.cpu.iew.exec_branches 111935144 # Number of branches executed -system.cpu.iew.exec_stores 193879140 # Number of stores executed -system.cpu.iew.exec_rate 1.501333 # Inst execution rate -system.cpu.iew.wb_sent 1756702193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1755173198 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1327558450 # num instructions producing a value -system.cpu.iew.wb_consumers 1975144997 # num instructions consuming a value +system.cpu.iew.exec_refs 665732549 # number of memory reference insts executed +system.cpu.iew.exec_branches 109682584 # Number of branches executed +system.cpu.iew.exec_stores 191842471 # Number of stores executed +system.cpu.iew.exec_rate 1.387301 # Inst execution rate +system.cpu.iew.wb_sent 1728142176 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1726805056 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262100818 # num instructions producing a value +system.cpu.iew.wb_consumers 1868205499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back +system.cpu.iew.wb_rate 1.355305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675569 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 406439731 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1125303290 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.440940 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26670511 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207095135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.660532 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 343524257 30.53% 30.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 441933791 39.27% 69.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 99674686 8.86% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 136523006 12.13% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 31731928 2.82% 93.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26136643 2.32% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22505633 2.00% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8189692 0.73% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15083654 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437349851 36.23% 36.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432546759 35.83% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93488393 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134921626 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35737028 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23235805 1.92% 95.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25789335 2.14% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8868292 0.73% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15158046 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1207095135 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,62 +270,62 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15083654 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15158046 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082456564 # The number of ROB reads -system.cpu.rob.rob_writes 3992764754 # The number of ROB writes -system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3219870802 # The number of ROB reads +system.cpu.rob.rob_writes 4122835024 # The number of ROB writes +system.cpu.timesIdled 1341 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 62470 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads -system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads -system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 905288155 # number of misc regfile reads -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 807.278486 # Cycle average of tags in use -system.cpu.icache.total_refs 136532946 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks. +system.cpu.cpi 1.447809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447809 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690699 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690699 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3282350370 # number of integer regfile reads +system.cpu.int_regfile_writes 1699874197 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.misc_regfile_reads 911417902 # number of misc regfile reads +system.cpu.icache.replacements 15 # number of replacements +system.cpu.icache.tagsinuse 828.919506 # Cycle average of tags in use +system.cpu.icache.total_refs 186628505 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 202857.070652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 807.278486 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.394179 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.394179 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 136532946 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 136532946 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 136532946 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 136532946 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 136532946 # number of overall hits -system.cpu.icache.overall_hits::total 136532946 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1228 # number of overall misses -system.cpu.icache.overall_misses::total 1228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43195500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43195500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43195500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43195500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43195500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 136534174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 136534174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 136534174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 136534174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 136534174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 828.919506 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186628507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186628507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186628507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186628507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186628507 # number of overall hits +system.cpu.icache.overall_hits::total 186628507 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses +system.cpu.icache.overall_misses::total 1352 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45933500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45933500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45933500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45933500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45933500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186629859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186629859 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186629859 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186629859 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186629859 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33974.482249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33974.482249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,80 +334,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 334 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 428 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 924 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 924 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 924 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 924 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 924 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32509500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32509500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32509500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32509500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35183.441558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35183.441558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459037 # number of replacements -system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use -system.cpu.dcache.total_refs 430357004 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 929.229841 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 414463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.269422 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 242420503 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 242420503 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187936501 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187936501 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 430357004 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1006.963684 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 723787000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.514188 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264747763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264747763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939802 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939802 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452687565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452687565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452687565 # 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number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,116 +416,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 409999 # number of writebacks -system.cpu.dcache.writebacks::total 409999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3488 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 35 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3523 # 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mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 400737 # number of writebacks +system.cpu.dcache.writebacks::total 400737 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 26 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3450 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1809374000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2798437500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2826925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2798437500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2826925500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156902 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.237034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996739 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200792 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31066.521265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.181619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.479731 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31066.521265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.434617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |