diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
9 files changed, 2853 insertions, 2868 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 56312634f..011acdd4e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274137 # Number of seconds simulated -sim_ticks 274137453500 # Number of ticks simulated -final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271545 # Number of seconds simulated +sim_ticks 271544682500 # Number of ticks simulated +final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134061 # Simulator instruction rate (inst/s) -host_op_rate 134061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61063086 # Simulator tick rate (ticks/s) -host_mem_usage 219148 # Number of bytes of host memory used -host_seconds 4489.41 # Real time elapsed on the host +host_inst_rate 105483 # Simulator instruction rate (inst/s) +host_op_rate 105483 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47591638 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 5705.72 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data 25316 # Nu system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114518787 # DTB read hits +system.cpu.dtb.read_hits 114517787 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114521418 # DTB read accesses -system.cpu.dtb.write_hits 39662426 # DTB write hits +system.cpu.dtb.read_accesses 114520418 # DTB read accesses +system.cpu.dtb.write_hits 39661840 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664728 # DTB write accesses -system.cpu.dtb.data_hits 154181213 # DTB hits +system.cpu.dtb.write_accesses 39664142 # DTB write accesses +system.cpu.dtb.data_hits 154179627 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154186146 # DTB accesses -system.cpu.itb.fetch_hits 25086764 # ITB hits +system.cpu.dtb.data_accesses 154184560 # DTB accesses +system.cpu.itb.fetch_hits 25070818 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25086786 # ITB accesses +system.cpu.itb.fetch_accesses 25070840 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548274908 # number of cpu cycles simulated +system.cpu.numCycles 543089366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81377487 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36366052 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52958494 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34331818 # Number of BTB hits +system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155050348 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36361065 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26186838 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.133148 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334459 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155051796 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed. -system.cpu.activity 89.213788 # Percentage of cycles cpu is active +system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed. +system.cpu.activity 90.059732 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.910972 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads +system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use -system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use +system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25085741 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25085741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25085741 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25085741 # number of overall hits -system.cpu.icache.overall_hits::total 25085741 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57700000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57700000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57700000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57700000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57700000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25086762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25086762 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25086762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25086762 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25086762 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits +system.cpu.icache.overall_hits::total 25069794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56513.222331 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21750 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46832500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46832500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46832500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46832500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120497 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38285544 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38285544 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406041 # number of overall hits -system.cpu.dcache.overall_hits::total 152406041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393545 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393545 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165777 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1559322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses -system.cpu.dcache.overall_misses::total 1559322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits +system.cpu.dcache.overall_hits::total 152406162 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses +system.cpu.dcache.overall_misses::total 1559201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029550 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911614 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103927 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.696955 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197099 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197113 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232980 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232980 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits @@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total 26157 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254176 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254176 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses @@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020475 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024550 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total 26157 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index f78f2bef4..73ec0cee6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135471 # Number of seconds simulated -sim_ticks 135471331500 # Number of ticks simulated -final_tick 135471331500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133202 # Number of seconds simulated +sim_ticks 133202081500 # Number of ticks simulated +final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 255662 # Simulator instruction rate (inst/s) -host_op_rate 255662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61240707 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 2212.11 # Real time elapsed on the host +host_inst_rate 189557 # Simulator instruction rate (inst/s) +host_op_rate 189557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44645563 # Simulator tick rate (ticks/s) +host_mem_usage 220464 # Number of bytes of host memory used +host_seconds 2983.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1689280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58944 # Number of bytes written to this memory -system.physmem.bytes_written::total 58944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26395 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 921 # Number of write requests responded to by this memory -system.physmem.num_writes::total 921 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 456835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12012815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12469649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 435103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 435103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 456835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12012815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12904752 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627520 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory +system.physmem.bytes_written::total 58752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory +system.physmem.num_writes::total 918 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 460293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12218428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12678721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 441074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 441074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 460293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12218428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13119795 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123970603 # DTB read hits -system.cpu.dtb.read_misses 28720 # DTB read misses +system.cpu.dtb.read_hits 123824653 # DTB read hits +system.cpu.dtb.read_misses 18111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123999323 # DTB read accesses -system.cpu.dtb.write_hits 40821734 # DTB write hits -system.cpu.dtb.write_misses 42993 # DTB write misses +system.cpu.dtb.read_accesses 123842764 # DTB read accesses +system.cpu.dtb.write_hits 40832181 # DTB write hits +system.cpu.dtb.write_misses 27219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40864727 # DTB write accesses -system.cpu.dtb.data_hits 164792337 # DTB hits -system.cpu.dtb.data_misses 71713 # DTB misses +system.cpu.dtb.write_accesses 40859400 # DTB write accesses +system.cpu.dtb.data_hits 164656834 # DTB hits +system.cpu.dtb.data_misses 45330 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164864050 # DTB accesses -system.cpu.itb.fetch_hits 66629589 # ITB hits +system.cpu.dtb.data_accesses 164702164 # DTB accesses +system.cpu.itb.fetch_hits 66456282 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66629628 # ITB accesses +system.cpu.itb.fetch_accesses 66456321 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 270942664 # number of cpu cycles simulated +system.cpu.numCycles 266404164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78540801 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72908130 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3045250 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42784442 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41679238 # Number of BTB hits +system.cpu.BPredUnit.lookups 78470433 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72835844 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3045377 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42694984 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41620121 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1625962 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68608304 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 712216936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78540801 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43305200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119376688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13084394 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72934666 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1626012 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68396808 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710651464 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78470433 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43246133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119157795 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12900055 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68967877 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66629589 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 948387 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.629013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.455853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1025 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66456282 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 943162 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.667916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.466169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151529905 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10364245 3.83% 59.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11839822 4.37% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610225 3.92% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6991463 2.58% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2667986 0.98% 71.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3540757 1.31% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105472 1.15% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70256718 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147211723 55.27% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10361930 3.89% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11839981 4.44% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10604273 3.98% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6985851 2.62% 70.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2662888 1.00% 71.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3489906 1.31% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104255 1.17% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70108711 26.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270906593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289880 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.628663 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86218522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56873885 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104030125 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13799230 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9984831 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3903379 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1089 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703205131 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9984831 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94485896 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12289062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104300720 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49844418 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 691143238 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5409 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37459217 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6250189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527606706 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907468723 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907465803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2920 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 266369518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.294554 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.667569 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85436450 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53444664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104479529 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13163939 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9844936 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3905187 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1152 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 701891597 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4998 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9844936 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93666462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10915780 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104171147 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47770208 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690014062 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37142293 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4412591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527194579 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906673497 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906670681 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2816 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63751817 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110700400 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129196942 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42484118 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14760258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9703253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626892028 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 99 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608695355 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 350153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60644934 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33797171 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270906593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.246883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.833563 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63339690 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106261883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128976533 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42417035 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14777590 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9627827 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626339991 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608311695 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 332491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60098493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33347060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 266369518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.283714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.821089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55377469 20.44% 20.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55325876 20.42% 40.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 54071762 19.96% 60.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36846414 13.60% 74.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30891550 11.40% 85.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23842623 8.80% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10560250 3.90% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3379294 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 611355 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 51762898 19.43% 19.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53589578 20.12% 39.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53994858 20.27% 59.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37661936 14.14% 73.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31638901 11.88% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23703533 8.90% 94.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10074612 3.78% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3319964 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 623238 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270906593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 266369518 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2755770 75.48% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 573872 15.72% 91.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 321392 8.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2702741 76.36% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 515259 14.56% 90.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321532 9.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441149057 72.47% 72.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7297 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126283457 20.75% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41255500 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 440952184 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7450 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126098325 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41253693 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608695355 # Type of FU issued -system.cpu.iq.rate 2.246584 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3651064 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005998 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492294648 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687539732 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598944947 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3872 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2425 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612344476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1943 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12180058 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608311695 # Type of FU issued +system.cpu.iq.rate 2.283417 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3539537 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005819 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1486861080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686441117 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598748300 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3856 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2343 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 611849296 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1936 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12174453 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14682900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33847 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5158 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3032797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14462491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33569 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4944 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2965714 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6745 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162513 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6773 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 155 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9984831 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 591994 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 671175480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1733020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129196942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42484118 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 99 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5158 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1342632 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2208039 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3550671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602850413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123999444 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5844942 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9844936 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227072 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16439 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670244681 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1692417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128976533 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42417035 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6445 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4188 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4944 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342659 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2208068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3550727 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602499469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123842867 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5812226 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44283353 # number of nop insts executed -system.cpu.iew.exec_refs 164880697 # number of memory reference insts executed -system.cpu.iew.exec_branches 67045865 # Number of branches executed -system.cpu.iew.exec_stores 40881253 # Number of stores executed -system.cpu.iew.exec_rate 2.225011 # Inst execution rate -system.cpu.iew.wb_sent 600209978 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598946660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417271834 # num instructions producing a value -system.cpu.iew.wb_consumers 532298467 # num instructions consuming a value +system.cpu.iew.exec_nop 43904609 # number of nop insts executed +system.cpu.iew.exec_refs 164718956 # number of memory reference insts executed +system.cpu.iew.exec_branches 66994757 # Number of branches executed +system.cpu.iew.exec_stores 40876089 # Number of stores executed +system.cpu.iew.exec_rate 2.261599 # Inst execution rate +system.cpu.iew.wb_sent 599990050 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598749999 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417673921 # num instructions producing a value +system.cpu.iew.wb_consumers 531386701 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.210603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783906 # average fanout of values written-back +system.cpu.iew.wb_rate 2.247525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786007 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69202424 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68221188 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3044252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 260921762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.306657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.693748 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3044329 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 256524582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.346196 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 81870366 31.38% 31.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72918515 27.95% 59.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26232772 10.05% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8204750 3.14% 72.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10788682 4.13% 76.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20849092 7.99% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6203888 2.38% 87.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3594438 1.38% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30259259 11.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77999684 30.41% 30.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72616675 28.31% 58.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26248532 10.23% 68.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7743107 3.02% 71.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10914414 4.25% 76.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20847110 8.13% 84.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6257952 2.44% 86.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3103879 1.21% 88.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30793229 12.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 260921762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 256524582 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30259259 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30793229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 901657501 # The number of ROB reads -system.cpu.rob.rob_writes 1352126118 # The number of ROB writes -system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36071 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 895745115 # The number of ROB reads +system.cpu.rob.rob_writes 1350023504 # The number of ROB writes +system.cpu.timesIdled 796 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34646 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.479076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479076 # CPI: Total CPI of All Threads -system.cpu.ipc 2.087351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.087351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848921354 # number of integer regfile reads -system.cpu.int_regfile_writes 492788777 # number of integer regfile writes -system.cpu.fp_regfile_reads 376 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cpi 0.471051 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.471051 # CPI: Total CPI of All Threads +system.cpu.ipc 2.122911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.122911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848545483 # number of integer regfile reads +system.cpu.int_regfile_writes 492673182 # number of integer regfile writes +system.cpu.fp_regfile_reads 367 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 46 # number of replacements -system.cpu.icache.tagsinuse 834.348638 # Cycle average of tags in use -system.cpu.icache.total_refs 66628172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67301.183838 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.655289 # Cycle average of tags in use +system.cpu.icache.total_refs 66454892 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67880.379980 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.348638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407397 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407397 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66628172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66628172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66628172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66628172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66628172 # number of overall hits -system.cpu.icache.overall_hits::total 66628172 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1417 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1417 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1417 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1417 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1417 # number of overall misses -system.cpu.icache.overall_misses::total 1417 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51973000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51973000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51973000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51973000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51973000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66629589 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66629589 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66629589 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66629589 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66629589 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 827.655289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404129 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404129 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66454892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66454892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66454892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66454892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66454892 # number of overall hits +system.cpu.icache.overall_hits::total 66454892 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1390 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66456282 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66456282 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66456282 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36678.193366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36678.193366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36678.193366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34673.741007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34673.741007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34673.741007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34673.741007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37526.262626 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37526.262626 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36228.294178 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36228.294178 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36228.294178 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1770625 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1770625 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2348384 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2348384 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2348384 # number of overall misses -system.cpu.dcache.overall_misses::total 2348384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8217146500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8217146500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45283421033 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45283421033 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 321.888467 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 135777000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.413189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999368 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111075212 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111075212 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38533998 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38533998 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 43 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 43 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149609210 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7625818400 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7625818400 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10903574900 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10903574900 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10903574900 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10903574900 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111643340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111643340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151111803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151111803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151111803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151111803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005174 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005174 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044881 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.044881 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015541 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015541 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015541 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015541 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14222.446556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14222.446556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25574.823033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25574.823033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22781.865118 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 260996 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 99 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2636.323232 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151094661 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151094661 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151094661 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151094661 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005089 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.023252 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009831 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009831 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5769.397917 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5769.397917 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8313.122423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8313.122423 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444797 # number of writebacks -system.cpu.dcache.writebacks::total 444797 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367652 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367652 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1516116 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1516116 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2751.940307 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5386.637052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4194.661621 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 464786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 465765 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 464786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 465765 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083054 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978550 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.054713 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.056655 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978550 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.054713 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.056655 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10499.428571 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 921 # number of writebacks -system.cpu.l2cache.writebacks::total 921 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5263 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26395 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 136100000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167740000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 754125496 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 890225496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 921865496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 890225496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 921865496 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083029 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056690 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054729 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056690 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32719.751810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31680.633147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31871.556147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35686.423244 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32719.751810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.654554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34925.762303 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 918 # number of writebacks +system.cpu.l2cache.writebacks::total 918 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5250 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21138 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26388 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083054 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054713 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 6b056dd7e..cd0e43aa8 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.764109 # Number of seconds simulated -sim_ticks 764109115000 # Number of ticks simulated -final_tick 764109115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762398 # Number of seconds simulated +sim_ticks 762397656000 # Number of ticks simulated +final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2465110 # Simulator instruction rate (inst/s) -host_op_rate 2465110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3129668646 # Simulator tick rate (ticks/s) -host_mem_usage 218984 # Number of bytes of host memory used -host_seconds 244.15 # Real time elapsed on the host +host_inst_rate 1514073 # Simulator instruction rate (inst/s) +host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1917939864 # Simulator tick rate (ticks/s) +host_mem_usage 219440 # Number of bytes of host memory used +host_seconds 397.51 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25315 # Nu system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory system.physmem.num_writes::total 883 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 65582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2120325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2185908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 65582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 73958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 73958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 65582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2120325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2259866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1528218230 # number of cpu cycles simulated +system.cpu.numCycles 1524795312 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1528218230 # Number of busy cycles +system.cpu.num_busy_cycles 1524795312 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.286058 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.286058 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328753 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328753 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44165000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55553.459119 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41780000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41780000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.128141 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 590218000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.128141 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2991812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4452609000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7444421000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7444421000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7444421000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16347.173333 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2388116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3690120000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6078236000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078236000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6078236000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22839.375690 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21645.673483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.235332 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 525.466875 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020393 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 3e2378b89..20eccd335 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164735 # Number of seconds simulated -sim_ticks 164735271500 # Number of ticks simulated -final_tick 164735271500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.163008 # Number of seconds simulated +sim_ticks 163008222000 # Number of ticks simulated +final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151833 # Simulator instruction rate (inst/s) -host_op_rate 160438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43876980 # Simulator tick rate (ticks/s) -host_mem_usage 229232 # Number of bytes of host memory used -host_seconds 3754.48 # Real time elapsed on the host -sim_insts 570052715 # Number of instructions simulated -sim_ops 602360921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1771392 # Number of bytes read from this memory -system.physmem.bytes_read::total 1819904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 204096 # Number of bytes written to this memory -system.physmem.bytes_written::total 204096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27678 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28436 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3189 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3189 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 294485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10752961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11047446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 294485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 294485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1238933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1238933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1238933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 294485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10752961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12286379 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 104701 # Simulator instruction rate (inst/s) +host_op_rate 110635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29939476 # Simulator tick rate (ticks/s) +host_mem_usage 234836 # Number of bytes of host memory used +host_seconds 5444.59 # Real time elapsed on the host +sim_insts 570052710 # Number of instructions simulated +sim_ops 602360916 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1771648 # Number of bytes read from this memory +system.physmem.bytes_read::total 1819712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 204352 # Number of bytes written to this memory +system.physmem.bytes_written::total 204352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27682 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28433 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3193 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3193 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 294856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10868458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11163314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 294856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 294856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1253630 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1253630 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1253630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 294856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10868458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12416944 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329470544 # number of cpu cycles simulated +system.cpu.numCycles 326016445 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85543194 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80343428 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2410851 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47247808 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46879382 # Number of BTB hits +system.cpu.BPredUnit.lookups 85521826 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80321411 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2409005 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47176245 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46862526 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438508 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 957 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68858387 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669531966 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85543194 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48317890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130053558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13436601 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119467619 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438689 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 908 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68838729 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669384047 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85521826 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48301215 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130014225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13401210 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 116068554 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 664 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67410579 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 785974 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329380053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195076 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67395150 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 787497 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 325897750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.188570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.203934 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199326735 60.52% 60.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20925869 6.35% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4976270 1.51% 68.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14401478 4.37% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8915823 2.71% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9447821 2.87% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4394131 1.33% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5797396 1.76% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61194530 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 195883756 60.11% 60.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20926266 6.42% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4973061 1.53% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14397687 4.42% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8914249 2.74% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9438407 2.90% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4391608 1.35% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5795696 1.78% 81.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61177020 18.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329380053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259638 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93515183 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96161670 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108196547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20508331 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10998322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4720780 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1591 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705885224 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5921 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10998322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107743564 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14112964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 43222 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114413091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82068890 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697152675 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59727344 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20123270 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 641 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723862465 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241326776 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241326648 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 325897750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.262324 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053222 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92928440 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93325217 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108744555 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19925503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10974035 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4721193 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1619 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705690133 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6091 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10974035 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107218931 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12903831 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39750 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114312743 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80448460 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 696999769 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59211261 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 18958262 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 603 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723690859 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3240622549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3240622421 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96443284 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2057 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2011 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169978483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172921644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80622072 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21488970 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28010178 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681988292 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646797787 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1412727 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79459503 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198007283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 345 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329380053 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727918 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96271686 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2053 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2007 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169155311 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172874803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80609628 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21505343 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28086060 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681842513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3260 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646713779 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1407547 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79314162 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197591004 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 331 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 325897750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.984407 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.742434 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69019799 20.95% 20.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85512996 25.96% 46.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75829369 23.02% 69.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 41034711 12.46% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28570777 8.67% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15062101 4.57% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5699719 1.73% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6474655 1.97% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2175926 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67307339 20.65% 20.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84522408 25.94% 46.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74985673 23.01% 69.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40267786 12.36% 81.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28844208 8.85% 90.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15117912 4.64% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5722755 1.76% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6923607 2.12% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2206062 0.68% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329380053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 325897750 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206481 5.38% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2616685 68.13% 73.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1017800 26.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205384 5.40% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2833511 74.46% 79.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 766298 20.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403890666 62.44% 62.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6567 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403852803 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6571 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166105526 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76795025 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166065084 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76789318 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646797787 # Type of FU issued -system.cpu.iq.rate 1.963143 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3840966 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005938 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628229284 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761462946 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638497717 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646713779 # Type of FU issued +system.cpu.iq.rate 1.983685 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3805193 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005884 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624538012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761171255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638446114 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650638733 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650518952 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30397502 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30376789 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23968825 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 126112 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12134 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10400833 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23921985 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123764 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11533 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10388390 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12732 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35377 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12747 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17143 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10998322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 671065 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80095 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 681994740 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 717531 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172921644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80622072 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1925 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21947 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12134 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389665 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1520287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2909952 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642597340 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163964037 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4200447 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10974035 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 319837 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41126 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 681848951 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 703596 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172874803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80609628 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10996 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4141 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11533 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1387510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519308 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2906818 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642524921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163926120 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4188858 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3173 # number of nop insts executed -system.cpu.iew.exec_refs 239958391 # number of memory reference insts executed -system.cpu.iew.exec_branches 74720339 # Number of branches executed -system.cpu.iew.exec_stores 75994354 # Number of stores executed -system.cpu.iew.exec_rate 1.950394 # Inst execution rate -system.cpu.iew.wb_sent 639963641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638497733 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419111890 # num instructions producing a value -system.cpu.iew.wb_consumers 650388459 # num instructions consuming a value +system.cpu.iew.exec_nop 3178 # number of nop insts executed +system.cpu.iew.exec_refs 239918745 # number of memory reference insts executed +system.cpu.iew.exec_branches 74716876 # Number of branches executed +system.cpu.iew.exec_stores 75992625 # Number of stores executed +system.cpu.iew.exec_rate 1.970836 # Inst execution rate +system.cpu.iew.wb_sent 639915699 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638446130 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420790055 # num instructions producing a value +system.cpu.iew.wb_consumers 656091526 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937951 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644402 # average fanout of values written-back +system.cpu.iew.wb_rate 1.958325 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641359 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79643282 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2930 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2409350 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318381732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233867 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79497382 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2407463 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 314923716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.912720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.240103 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93812247 29.47% 29.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104551370 32.84% 62.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43266938 13.59% 75.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8778657 2.76% 78.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26036096 8.18% 86.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12762730 4.01% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7569326 2.38% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1269179 0.40% 93.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20335189 6.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91160511 28.95% 28.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103755163 32.95% 61.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42928794 13.63% 75.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8971951 2.85% 78.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25547635 8.11% 86.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13484569 4.28% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7640580 2.43% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1100606 0.35% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20333907 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318381732 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052766 # Number of instructions committed -system.cpu.commit.committedOps 602360972 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 314923716 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052761 # Number of instructions committed +system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174058 # Number of memory references committed -system.cpu.commit.loads 148952819 # Number of loads committed +system.cpu.commit.refs 219174056 # Number of memory references committed +system.cpu.commit.loads 148952818 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892750 # Number of branches committed +system.cpu.commit.branches 70892749 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523535 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523531 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20335189 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20333907 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980050185 # The number of ROB reads -system.cpu.rob.rob_writes 1375038514 # The number of ROB writes -system.cpu.timesIdled 6612 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052715 # Number of Instructions Simulated -system.cpu.committedOps 602360921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052715 # Number of Instructions Simulated -system.cpu.cpi 0.577965 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577965 # CPI: Total CPI of All Threads -system.cpu.ipc 1.730208 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.730208 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210034168 # number of integer regfile reads -system.cpu.int_regfile_writes 664124835 # number of integer regfile writes +system.cpu.rob.rob_reads 976447546 # The number of ROB reads +system.cpu.rob.rob_writes 1374722217 # The number of ROB writes +system.cpu.timesIdled 15150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 118695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052710 # Number of Instructions Simulated +system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated +system.cpu.cpi 0.571906 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.571906 # CPI: Total CPI of All Threads +system.cpu.ipc 1.748540 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.748540 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3209706655 # number of integer regfile reads +system.cpu.int_regfile_writes 664060053 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 904851739 # number of misc regfile reads -system.cpu.misc_regfile_writes 3108 # number of misc regfile writes -system.cpu.icache.replacements 59 # number of replacements -system.cpu.icache.tagsinuse 698.555131 # Cycle average of tags in use -system.cpu.icache.total_refs 67409471 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 828 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81412.404589 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 904689637 # number of misc regfile reads +system.cpu.misc_regfile_writes 3106 # number of misc regfile writes +system.cpu.icache.replacements 58 # number of replacements +system.cpu.icache.tagsinuse 694.540428 # Cycle average of tags in use +system.cpu.icache.total_refs 67394031 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 818 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82388.790954 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 698.555131 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.341091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.341091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67409471 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67409471 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67409471 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67409471 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67409471 # number of overall hits -system.cpu.icache.overall_hits::total 67409471 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses -system.cpu.icache.overall_misses::total 1108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38972000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38972000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38972000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38972000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38972000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38972000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67410579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67410579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67410579 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67410579 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67410579 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67410579 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35173.285199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35173.285199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35173.285199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35173.285199 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 694.540428 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.339131 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.339131 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67394031 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67394031 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67394031 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67394031 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67394031 # number of overall hits +system.cpu.icache.overall_hits::total 67394031 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1119 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1119 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1119 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1119 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1119 # number of overall misses +system.cpu.icache.overall_misses::total 1119 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37389000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37389000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37389000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37389000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37389000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37389000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67395150 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67395150 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67395150 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67395150 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67395150 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67395150 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33412.868633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33412.868633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33412.868633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33412.868633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33412.868633 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,309 +398,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 828 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 828 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 828 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 828 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 818 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 818 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 818 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 818 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 818 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28166000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28166000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28166000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28166000 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66856753 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1705 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1705 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1553 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1553 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 198864103 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 198864103 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 198864103 # number of overall hits -system.cpu.dcache.overall_hits::total 198864103 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 301339 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 301339 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2560778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2560778 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11662167592 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11662167592 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 117000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12868664092 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12868664092 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12868664092 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12868664092 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132309711 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132309711 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # 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miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036889 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036889 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012739 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012739 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014188 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014188 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014188 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014188 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12251.183883 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12251.183883 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15795.642625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15795.642625 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10886.363636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10886.363636 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15422.463033 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15422.463033 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30346130 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2896 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1720 # 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miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012791 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012791 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007472 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007472 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007472 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007472 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5573.349933 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5573.349933 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9034.018137 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9034.018137 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 5318.181818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 5318.181818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28514592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10478.636050 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9460.714001 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420958 # number of writebacks -system.cpu.dcache.writebacks::total 420958 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104059 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104059 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2313654 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2313654 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks +system.cpu.dcache.writebacks::total 421091 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 19124 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7839.542782 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11142.485671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11142.485671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9676.241953 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9676.241953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9676.241953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9676.241953 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3002.639953 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3002.639953 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5915.328647 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031534 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089787 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089787 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063868 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32802.110818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31962.652578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32064.510965 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37799.823561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37799.823561 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5494 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6245 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22188 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22188 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27682 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28433 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27682 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28433 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072307301 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1097104801 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072307301 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1097104801 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089785 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089785 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063852 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062280 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 7bce23d96..e1fc6c299 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.795271 # Number of seconds simulated -sim_ticks 795270546000 # Number of ticks simulated -final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.793710 # Number of seconds simulated +sim_ticks 793709507000 # Number of ticks simulated +final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1274959 # Simulator instruction rate (inst/s) -host_op_rate 1346403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783406999 # Simulator tick rate (ticks/s) -host_mem_usage 227740 # Number of bytes of host memory used -host_seconds 445.93 # Real time elapsed on the host +host_inst_rate 1083083 # Simulator instruction rate (inst/s) +host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1512037928 # Simulator tick rate (ticks/s) +host_mem_usage 233820 # Number of bytes of host memory used +host_seconds 524.93 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 27110 # Nu system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2181698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2230868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 244888 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 244888 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 244888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2181698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2475756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1590541092 # number of cpu cycles simulated +system.cpu.numCycles 1587419014 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 568539335 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 219173606 # nu system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1590541092 # Number of busy cycles +system.cpu.num_busy_cycles 1587419014 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.715333 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.715333 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282088 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282088 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34792000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34792000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34792000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34792000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34792000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34792000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54108.864697 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54108.864697 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32863000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32863000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32863000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32863000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32863000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32863000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.191707 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 547974000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.191707 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999559 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999559 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2866972000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2866972000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4400884000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4400884000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7267856000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7267856000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7267856000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7267856000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16609.812507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16609.812507 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2297524000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2297524000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3657640000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3657640000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5955164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5955164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5955164000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5955164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 3963 # number of replacements -system.cpu.l2cache.tagsinuse 21579.150724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20939.895204 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 130.071130 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 509.184390 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.639035 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.003969 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.658543 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits @@ -323,16 +323,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 611 # system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses system.cpu.l2cache.overall_misses::total 27721 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) @@ -358,16 +358,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,16 +390,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses @@ -412,16 +412,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c0dac2931..b8b444d29 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389171 # Number of seconds simulated -sim_ticks 389171400000 # Number of ticks simulated -final_tick 389171400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.386987 # Number of seconds simulated +sim_ticks 386986985000 # Number of ticks simulated +final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248197 # Simulator instruction rate (inst/s) -host_op_rate 248980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68935275 # Simulator tick rate (ticks/s) -host_mem_usage 223264 # Number of bytes of host memory used -host_seconds 5645.46 # Real time elapsed on the host +host_inst_rate 135169 # Simulator instruction rate (inst/s) +host_op_rate 135595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37331500 # Simulator tick rate (ticks/s) +host_mem_usage 223688 # Number of bytes of host memory used +host_seconds 10366.23 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679232 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory -system.physmem.bytes_written::total 163392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27465 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 201783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4314891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4516673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 419846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 419846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 419846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679104 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163264 # Number of bytes written to this memory +system.physmem.bytes_written::total 163264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26236 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27467 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2551 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2551 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4338916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4542499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 421885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 421885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 421885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4338916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4964384 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778342801 # number of cpu cycles simulated +system.cpu.numCycles 773973971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88413236 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785239 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66015510 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65664831 # Number of BTB hits +system.cpu.BPredUnit.lookups 98196903 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88415122 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785922 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66048945 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65663541 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1336 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 1365 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165881717 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648798034 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98197174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264316803 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778298468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 165893347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648920679 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98196903 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65664906 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330423745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21687705 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 259909474 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2700 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162828772 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 752135 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 773928223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.136454 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.151019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447887264 57.55% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28163510 3.62% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18828809 2.42% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11510131 1.48% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871378 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 443504478 57.31% 57.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74374556 9.61% 66.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37974673 4.91% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9085275 1.17% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28162152 3.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18827829 2.43% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11514662 1.49% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3870211 0.50% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146614387 18.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778298468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217730424 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214714897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285147825 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43019384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241679770 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51960576 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127037200 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73402475 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721856567 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33843505 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 773928223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126874 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.130460 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216918337 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211126972 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285339114 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42844971 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17698829 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642655288 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17698829 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 240878845 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33665029 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51866735 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303087743 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126731042 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631322359 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30917915 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73728979 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3098650 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360964482 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755920727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2722080159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33840568 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116053960 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2679524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2694715 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273063750 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82754827 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54636 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778298468 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116194043 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680701 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2696386 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 272557720 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438727279 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180254007 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255223658 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82981799 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517066880 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635302 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460886365 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45400 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113758577 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136602100 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391631 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 773928223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.887625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429425 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147064058 18.90% 18.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186545303 23.97% 42.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210910021 27.10% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70782478 9.09% 95.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7762489 1.00% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 144009666 18.61% 18.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 185251464 23.94% 42.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210317974 27.18% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131221648 16.96% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70752732 9.14% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20294392 2.62% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7875333 1.02% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4040989 0.52% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 164025 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778298468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 773928223 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 166579 10.26% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1139492 70.19% 87.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90190 5.49% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 99214 6.04% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1093274 66.56% 78.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 359776 21.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867086456 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867180921 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2642669 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2647347 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,84 +193,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419773044 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171266889 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419785067 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171273030 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued -system.cpu.iq.rate 1.876768 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1623526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3683829702 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453371392 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460886365 # Type of FU issued +system.cpu.iq.rate 1.887514 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1642454 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001124 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3679668823 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624597420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444476565 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17719984 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9099813 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8555773 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453469070 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9059749 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215381487 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36194595 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55177 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245195 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13401611 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36214436 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54352 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244694 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13405865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3537 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56120 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3598 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17685938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1543124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 135108 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613772123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123534 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438707438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180249753 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549312 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88176 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3284 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245195 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2354964 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1564711 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919675 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455222367 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417054039 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5546691 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17698829 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 443700 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14828 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613898358 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123447 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438727279 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180254007 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549639 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8198 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1497 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244694 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356359 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1563564 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919923 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455334067 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417065579 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5552298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94195438 # number of nop insts executed -system.cpu.iew.exec_refs 587626307 # number of memory reference insts executed -system.cpu.iew.exec_branches 89109233 # Number of branches executed -system.cpu.iew.exec_stores 170572268 # Number of stores executed -system.cpu.iew.exec_rate 1.869642 # Inst execution rate -system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154316776 # num instructions producing a value -system.cpu.iew.wb_consumers 1205166275 # num instructions consuming a value +system.cpu.iew.exec_nop 94196176 # number of nop insts executed +system.cpu.iew.exec_refs 587643036 # number of memory reference insts executed +system.cpu.iew.exec_branches 89109340 # Number of branches executed +system.cpu.iew.exec_stores 170577457 # Number of stores executed +system.cpu.iew.exec_rate 1.880340 # Inst execution rate +system.cpu.iew.wb_sent 1453944636 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1453032338 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154452527 # num instructions producing a value +system.cpu.iew.wb_consumers 1205669839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back +system.cpu.iew.wb_rate 1.877366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957520 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124266701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760613141 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756230005 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.969670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506799 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276879555 36.40% 68.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43195229 5.68% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19686776 2.59% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13341139 1.75% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10352976 1.36% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70115496 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 237695032 31.43% 31.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276589849 36.57% 68.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43049426 5.69% 73.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54802104 7.25% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19618852 2.59% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13377170 1.77% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30585382 4.04% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10542801 1.39% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69969389 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760613141 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756230005 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,70 +281,70 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70115496 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69969389 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304117872 # The number of ROB reads -system.cpu.rob.rob_writes 3245080355 # The number of ROB writes -system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2299985729 # The number of ROB reads +system.cpu.rob.rob_writes 3245302839 # The number of ROB writes +system.cpu.timesIdled 3314 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 45748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.555487 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555487 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800221 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800221 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980525328 # number of integer regfile reads -system.cpu.int_regfile_writes 1276196147 # number of integer regfile writes -system.cpu.fp_regfile_reads 16956232 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491758 # number of floating regfile writes -system.cpu.misc_regfile_reads 593298094 # number of misc regfile reads +system.cpu.cpi 0.552369 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552369 # CPI: Total CPI of All Threads +system.cpu.ipc 1.810383 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.810383 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980648344 # number of integer regfile reads +system.cpu.int_regfile_writes 1276312589 # number of integer regfile writes +system.cpu.fp_regfile_reads 16966196 # number of floating regfile reads +system.cpu.fp_regfile_writes 10497856 # number of floating regfile writes +system.cpu.misc_regfile_reads 593314657 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 214 # number of replacements -system.cpu.icache.tagsinuse 1046.066234 # Cycle average of tags in use -system.cpu.icache.total_refs 162817587 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119543.015419 # Average number of references to valid blocks. +system.cpu.icache.replacements 209 # number of replacements +system.cpu.icache.tagsinuse 1046.532429 # Cycle average of tags in use +system.cpu.icache.total_refs 162826872 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1358 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119901.967599 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1046.066234 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510775 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510775 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162817587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162817587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162817587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162817587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162817587 # number of overall hits -system.cpu.icache.overall_hits::total 162817587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1912 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1912 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1912 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1912 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1912 # number of overall misses -system.cpu.icache.overall_misses::total 1912 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62928500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62928500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62928500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162819499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162819499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162819499 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162819499 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162819499 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162819499 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1046.532429 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.511002 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.511002 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162826872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162826872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162826872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162826872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162826872 # number of overall hits +system.cpu.icache.overall_hits::total 162826872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1900 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1900 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1900 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1900 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1900 # number of overall misses +system.cpu.icache.overall_misses::total 1900 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60525500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60525500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60525500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60525500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60525500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60525500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162828772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162828772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162828772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162828772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162828772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162828772 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32912.395397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32912.395397 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32912.395397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32912.395397 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31855.526316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31855.526316 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31855.526316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31855.526316 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31855.526316 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,248 +353,248 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083205 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083205 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059275 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059275 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31596.984515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.965051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.185094 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2551 # number of writebacks +system.cpu.l2cache.writebacks::total 2551 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1231 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4442 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5673 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21794 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21794 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27467 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27467 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39025000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138834500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177859500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 777128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 777128500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915963000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 954988000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39025000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915963000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 954988000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022179 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059228 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.905813 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056740 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059228 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31701.868400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31254.952724 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31351.930196 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35657.910434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35657.910434 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31701.868400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34912.448544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34768.558634 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 3078a0fec..c111732e8 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.063178 # Number of seconds simulated -sim_ticks 2063177737000 # Number of ticks simulated -final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061067 # Number of seconds simulated +sim_ticks 2061066683000 # Number of ticks simulated +final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1527975 # Simulator instruction rate (inst/s) -host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2122729697 # Simulator tick rate (ticks/s) -host_mem_usage 231576 # Number of bytes of host memory used -host_seconds 971.95 # Real time elapsed on the host +host_inst_rate 1352034 # Simulator instruction rate (inst/s) +host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1876383782 # Simulator tick rate (ticks/s) +host_mem_usage 222536 # Number of bytes of host memory used +host_seconds 1098.43 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26134 # Nu system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 842537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4126355474 # number of cpu cycles simulated +system.cpu.numCycles 4122133366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108088 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365766 # nu system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4126355474 # Number of busy cycles +system.cpu.num_busy_cycles 4122133366 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58777000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58777000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58777000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53095.754291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53095.754291 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55456000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888728000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2888728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554574000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4554574000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16423.371741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16423.371741 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2308270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2308270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6083660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6083660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6083660000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6083660000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.499465 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.213631 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677100 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits @@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 27161 # nu system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses system.cpu.l2cache.overall_misses::total 27161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53406000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275654000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) @@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.059783 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27161 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 7a2ddd771..bad8d0f8e 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.609567 # Number of seconds simulated -sim_ticks 609566727000 # Number of ticks simulated -final_tick 609566727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.609798 # Number of seconds simulated +sim_ticks 609797568500 # Number of ticks simulated +final_tick 609797568500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62263 # Simulator instruction rate (inst/s) -host_op_rate 114724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43127912 # Simulator tick rate (ticks/s) -host_mem_usage 276908 # Number of bytes of host memory used -host_seconds 14133.93 # Real time elapsed on the host +host_inst_rate 67150 # Simulator instruction rate (inst/s) +host_op_rate 123728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46530668 # Simulator tick rate (ticks/s) +host_mem_usage 230840 # Number of bytes of host memory used +host_seconds 13105.28 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1752832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162880 # Number of bytes written to this memory -system.physmem.bytes_written::total 162880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26476 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2545 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2545 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2779784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2875538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2779784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3142744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694784 # Number of bytes read from this memory +system.physmem.bytes_read::total 1752896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory +system.physmem.bytes_written::total 162816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26481 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2779257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2874554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95297 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2779257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3141554 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1219133455 # number of cpu cycles simulated +system.cpu.numCycles 1219595138 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154519843 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154519843 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26678926 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77274626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76985066 # Number of BTB hits +system.cpu.BPredUnit.lookups 153419281 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 153419281 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26709105 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 75190754 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 74807048 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180157368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1482244654 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154519843 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76985066 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400441074 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91643666 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 573697614 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 180231048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1488409356 # Number of instructions fetch has processed +system.cpu.fetch.Branches 153419281 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 74807048 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400557825 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92407802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 573234633 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186403933 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9747583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1219106465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.078734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.272852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185924931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9228337 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1219569114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.084484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.278873 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 825883799 67.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24475369 2.01% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15188361 1.25% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18161843 1.49% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26717986 2.19% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18155688 1.49% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28775832 2.36% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39425650 3.23% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 222321937 18.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 826230375 67.75% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23815932 1.95% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15671088 1.28% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17469051 1.43% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26718016 2.19% 74.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18180169 1.49% 76.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 27807273 2.28% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39426907 3.23% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224250303 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1219106465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126746 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215818 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289371714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497062295 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275168406 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92693923 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 64810127 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2355715170 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 64810127 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337830723 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122995154 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1813 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305493642 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387975006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2259654010 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242278891 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120849469 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2627164074 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5766696541 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5766690921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5620 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1219569114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125795 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.220413 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289356881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 496684656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275171365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92810894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65545318 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2357736314 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 65545318 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337721602 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122595128 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1576 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305744833 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387960657 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2261287899 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242284686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120945759 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2627574208 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5773835618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5773831438 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4180 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740268817 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 96 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 730471883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 541137404 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220343917 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 347951990 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144808328 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2010997367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 534 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784139180 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 263264 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 389085977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 810611327 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 484 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1219106465 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.463481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418984 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 740678951 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 84 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 730447231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 543232760 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220439884 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 349480208 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144920713 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2014741693 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 481 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784164311 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260366 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 392823529 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 821144040 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1219569114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.462946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418593 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363767078 29.84% 29.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365542734 29.98% 59.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234442506 19.23% 79.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141155043 11.58% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 61085427 5.01% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39802416 3.26% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10825326 0.89% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1946919 0.16% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 539016 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 363999611 29.85% 29.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365670586 29.98% 59.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234855592 19.26% 79.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140866108 11.55% 90.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60913141 4.99% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40023537 3.28% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10789680 0.88% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1930984 0.16% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 519875 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1219106465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1219569114 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 465020 16.12% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2178971 75.55% 91.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 240132 8.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 467350 16.09% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2184649 75.23% 91.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 251796 8.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46815442 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065636060 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46816435 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065676196 59.73% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued @@ -194,84 +193,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478995198 26.85% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192692480 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478957046 26.84% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192714634 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784139180 # Type of FU issued -system.cpu.iq.rate 1.463449 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2884123 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001617 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4790531580 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2400258808 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725049081 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 632 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1764 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740207554 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209593506 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784164311 # Type of FU issued +system.cpu.iq.rate 1.462915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2903795 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001628 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4791061390 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2407739950 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725073479 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1436 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740251451 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 220 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209520869 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 122095283 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38780 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 181714 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32157860 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 124190639 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36910 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180735 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32253827 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2258 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 452 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2057 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 64810127 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 288054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 51315 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2010997901 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63873969 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 541137404 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220343917 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29041 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 466 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 181714 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2119314 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24709049 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26828363 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766210973 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474185905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17928207 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65545318 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 120938 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15130 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2014742174 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63913352 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 543232760 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220439884 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180735 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2120344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24738064 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26858408 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766248435 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474148133 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17915876 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666011474 # number of memory reference insts executed -system.cpu.iew.exec_branches 110196607 # Number of branches executed -system.cpu.iew.exec_stores 191825569 # Number of stores executed -system.cpu.iew.exec_rate 1.448743 # Inst execution rate -system.cpu.iew.wb_sent 1726341541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725049244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267580159 # num instructions producing a value -system.cpu.iew.wb_consumers 1828717326 # num instructions consuming a value +system.cpu.iew.exec_refs 665987460 # number of memory reference insts executed +system.cpu.iew.exec_branches 110190116 # Number of branches executed +system.cpu.iew.exec_stores 191839327 # Number of stores executed +system.cpu.iew.exec_rate 1.448225 # Inst execution rate +system.cpu.iew.wb_sent 1726426595 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725073583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267591282 # num instructions producing a value +system.cpu.iew.wb_consumers 1828482722 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.414980 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.693153 # average fanout of values written-back +system.cpu.iew.wb_rate 1.414464 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.693248 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 389506426 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 393250539 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26678961 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1154296338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.404747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.831971 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26709142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1154023796 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.405078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832959 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 420857241 36.46% 36.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413520492 35.82% 72.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87361055 7.57% 79.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122186130 10.59% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24494860 2.12% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23109073 2.00% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18457710 1.60% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12056348 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32253429 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 421087806 36.49% 36.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412894237 35.78% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87424698 7.58% 79.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122293813 10.60% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24525346 2.13% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22502511 1.95% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19027826 1.65% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12052514 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32215045 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1154296338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1154023796 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,68 +281,68 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32253429 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32215045 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3133043260 # The number of ROB reads -system.cpu.rob.rob_writes 4086848885 # The number of ROB writes -system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3136553215 # The number of ROB reads +system.cpu.rob.rob_writes 4095072141 # The number of ROB writes +system.cpu.timesIdled 539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26024 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.385339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.385339 # CPI: Total CPI of All Threads -system.cpu.ipc 0.721845 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.721845 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541474948 # number of integer regfile reads -system.cpu.int_regfile_writes 1975063996 # number of integer regfile writes -system.cpu.fp_regfile_reads 163 # number of floating regfile reads -system.cpu.misc_regfile_reads 910391945 # number of misc regfile reads -system.cpu.icache.replacements 26 # number of replacements -system.cpu.icache.tagsinuse 823.006550 # Cycle average of tags in use -system.cpu.icache.total_refs 186402559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 924 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201734.371212 # Average number of references to valid blocks. +system.cpu.cpi 1.385864 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.385864 # CPI: Total CPI of All Threads +system.cpu.ipc 0.721572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.721572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541346034 # number of integer regfile reads +system.cpu.int_regfile_writes 1975100349 # number of integer regfile writes +system.cpu.fp_regfile_reads 104 # number of floating regfile reads +system.cpu.misc_regfile_reads 910400266 # number of misc regfile reads +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 820.177123 # Cycle average of tags in use +system.cpu.icache.total_refs 185923597 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 202310.769314 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 823.006550 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401859 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401859 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186402560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186402560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186402560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186402560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186402560 # number of overall hits -system.cpu.icache.overall_hits::total 186402560 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses -system.cpu.icache.overall_misses::total 1373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48027000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48027000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48027000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48027000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48027000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48027000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186403933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186403933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186403933 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186403933 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186403933 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186403933 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 820.177123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.400477 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.400477 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185923597 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185923597 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185923597 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185923597 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185923597 # number of overall hits +system.cpu.icache.overall_hits::total 185923597 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1334 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1334 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1334 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1334 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1334 # number of overall misses +system.cpu.icache.overall_misses::total 1334 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44859000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44859000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44859000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44859000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44859000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44859000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185924931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185924931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185924931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185924931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185924931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185924931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34979.606701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34979.606701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34979.606701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34979.606701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34979.606701 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33627.436282 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33627.436282 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33627.436282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 33627.436282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33627.436282 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 5948.730051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 5948.730051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 5948.730051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,136 +447,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428431 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 851042000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022385 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026751 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060816 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.987013 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060816 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32317.982456 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31112.881952 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31314.136605 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.613353 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.613353 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32317.982456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31030.669285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31073.535855 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2544 # number of writebacks +system.cpu.l2cache.writebacks::total 2544 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4552 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21929 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21929 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27389 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29285500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 170951000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 682609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 682609000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 824274500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 853560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 824274500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 853560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022373 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026715 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060776 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.988030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060776 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32252.753304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31121.594903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31309.706960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31128.140818 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31128.140818 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32252.753304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31127.015596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.336047 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 045a8ad7b..e35ba34dd 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.801980 # Number of seconds simulated -sim_ticks 1801979679000 # Number of ticks simulated -final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.800193 # Number of seconds simulated +sim_ticks 1800193072000 # Number of ticks simulated +final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 528145 # Simulator instruction rate (inst/s) -host_op_rate 973136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1081454463 # Simulator tick rate (ticks/s) -host_mem_usage 274856 # Number of bytes of host memory used -host_seconds 1666.26 # Real time elapsed on the host +host_inst_rate 480678 # Simulator instruction rate (inst/s) +host_op_rate 885676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 983283018 # Simulator tick rate (ticks/s) +host_mem_usage 228792 # Number of bytes of host memory used +host_seconds 1830.80 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 26287 # Nu system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 933622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3603959358 # number of cpu cycles simulated +system.cpu.numCycles 3600386144 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228178 # nu system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3603959358 # Number of busy cycles +system.cpu.num_busy_cycles 3600386144 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40521000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40521000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40521000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56123.268698 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56123.268698 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38355000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38355000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38355000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38355000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38355000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38355000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905905 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2948308000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2948308000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4362877000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4362877000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4104707000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4104707000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6851259000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6851259000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16539.346406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16539.346406 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2356330000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2356330000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3628711000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3628711000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5985041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5985041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5985041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5985041000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615263000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5967163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.676326 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641480 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.676373 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits @@ -272,14 +272,14 @@ system.cpu.l2cache.overall_misses::total 27009 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143021000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1143021000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1367505000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1405049000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1367505000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1405049000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) @@ -307,14 +307,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.061000 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.445152 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.445152 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52021.511348 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52021.511348 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -339,14 +339,14 @@ system.cpu.l2cache.overall_mshr_misses::total 27009 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 878800000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 878800000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879381000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879381000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1051480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1080360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052061000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1080941000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052061000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1080941000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses @@ -361,14 +361,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40026.445152 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |