diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
7 files changed, 532 insertions, 531 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index c24180c55..5d521d8ff 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 4180d507c..2783a8301 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:00:24 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:17:26 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164280509500 because target called exit() +Exiting @ tick 164277874000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 65753c5e3..46c526502 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164281 # Number of seconds simulated -sim_ticks 164280509500 # Number of ticks simulated -final_tick 164280509500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164278 # Number of seconds simulated +sim_ticks 164277874000 # Number of ticks simulated +final_tick 164277874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203818 # Simulator instruction rate (inst/s) -host_op_rate 215370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58737354 # Simulator tick rate (ticks/s) -host_mem_usage 223536 # Number of bytes of host memory used -host_seconds 2796.87 # Real time elapsed on the host -sim_insts 570051663 # Number of instructions simulated -sim_ops 602359870 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5845888 # Number of bytes read from this memory -system.physmem.bytes_inst_read 49408 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3721728 # Number of bytes written to this memory -system.physmem.num_reads 91342 # Number of read requests responded to by this memory -system.physmem.num_writes 58152 # Number of write requests responded to by this memory +host_inst_rate 203470 # Simulator instruction rate (inst/s) +host_op_rate 215002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58636208 # Simulator tick rate (ticks/s) +host_mem_usage 227276 # Number of bytes of host memory used +host_seconds 2801.65 # Real time elapsed on the host +sim_insts 570051643 # Number of instructions simulated +sim_ops 602359850 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 5845952 # Number of bytes read from this memory +system.physmem.bytes_inst_read 50048 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3721408 # Number of bytes written to this memory +system.physmem.num_reads 91343 # Number of read requests responded to by this memory +system.physmem.num_writes 58147 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35584793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 300754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22654714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58239508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 35585754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 304655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 22653130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 58238884 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,141 +64,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328561020 # number of cpu cycles simulated +system.cpu.numCycles 328555749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85502166 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80303538 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2364558 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47128818 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46810492 # Number of BTB hits +system.cpu.BPredUnit.lookups 85495228 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80299392 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2363839 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47188450 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46808758 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441322 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2014 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68931697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669727391 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85502166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48251814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130042659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13473975 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117702916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67497554 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807456 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327710434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.177756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200257 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1441266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2064 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68932526 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669692235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85495228 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48250024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130038876 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13469589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117716369 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67498352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807371 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 327717199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.177607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.200173 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197667987 60.32% 60.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955558 6.39% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944545 1.51% 68.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14317291 4.37% 72.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8979833 2.74% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9404994 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4387469 1.34% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814392 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61238365 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 197678537 60.32% 60.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20955398 6.39% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4944268 1.51% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317146 4.37% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8982056 2.74% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9405272 2.87% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4386310 1.34% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814100 1.77% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61234112 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327710434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260232 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93127005 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94874868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108614475 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20063382 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11030704 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4784748 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1773 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706010986 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5362 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11030704 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107410901 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13982712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 118932 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114322879 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80844306 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697216799 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 201 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59255173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19368550 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 660 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723821711 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241352610 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241352482 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 327717199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260215 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.038291 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93143264 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94872868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108628769 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20045238 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11027060 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784060 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705973468 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5432 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11027060 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107429081 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13945008 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 118563 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114317154 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80880333 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697178999 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 231 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59283430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19375407 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 624 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723780453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241174730 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241174602 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96404213 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11540 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169974240 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172906537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80619433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21532364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27969964 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681972253 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9148 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646841509 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1424100 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79435960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197814866 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2789 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327710434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.973820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.737996 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96362987 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11553 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11552 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169904976 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172902366 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80616631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21434396 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27805052 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681951411 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9116 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646829241 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79415012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197703011 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 327717199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.973742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.738606 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68514298 20.91% 20.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84850419 25.89% 46.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75242172 22.96% 69.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40564366 12.38% 82.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28638763 8.74% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15215694 4.64% 95.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5886369 1.80% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6524912 1.99% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2273441 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68508405 20.90% 20.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84956160 25.92% 46.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75144846 22.93% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40581693 12.38% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28626833 8.74% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15169754 4.63% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5928523 1.81% 97.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6496810 1.98% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2304175 0.70% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327710434 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 327717199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205233 5.10% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2909479 72.37% 77.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 905756 22.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204843 5.11% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2907010 72.53% 77.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 896423 22.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403929410 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6579 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403920439 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -226,153 +226,153 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166116267 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76789250 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166108811 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76793420 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646841509 # Type of FU issued -system.cpu.iq.rate 1.968710 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4020468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006216 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626837984 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761428768 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638548229 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646829241 # Type of FU issued +system.cpu.iq.rate 1.968705 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4008276 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006197 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1626808250 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761386923 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638549644 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650861957 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650837497 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30419634 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30424903 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23953929 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 128648 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11649 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10398406 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23949762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11648 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10395608 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12846 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12456 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12818 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12531 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11030704 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 854813 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 57677 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682047620 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 663984 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172906537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80619433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7812 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4667 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11649 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1314819 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1584401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2899220 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642689835 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163986431 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4151674 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11027060 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 853408 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62572 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682026706 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 660555 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172902366 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80616631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6245 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11648 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1315368 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2897874 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642687405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163985784 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4141836 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66219 # number of nop insts executed -system.cpu.iew.exec_refs 239991845 # number of memory reference insts executed -system.cpu.iew.exec_branches 74670108 # Number of branches executed -system.cpu.iew.exec_stores 76005414 # Number of stores executed -system.cpu.iew.exec_rate 1.956075 # Inst execution rate -system.cpu.iew.wb_sent 640041427 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638548245 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420154647 # num instructions producing a value -system.cpu.iew.wb_consumers 654937446 # num instructions consuming a value +system.cpu.iew.exec_nop 66179 # number of nop insts executed +system.cpu.iew.exec_refs 239997187 # number of memory reference insts executed +system.cpu.iew.exec_branches 74667058 # Number of branches executed +system.cpu.iew.exec_stores 76011403 # Number of stores executed +system.cpu.iew.exec_rate 1.956098 # Inst execution rate +system.cpu.iew.wb_sent 640040588 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638549660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420197588 # num instructions producing a value +system.cpu.iew.wb_consumers 654962025 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641519 # average fanout of values written-back +system.cpu.iew.wb_rate 1.943505 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641560 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570051714 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602359921 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79697124 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6359 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2424958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316679731 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239397 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570051694 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602359901 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79676133 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6355 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2424230 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 316690140 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.902048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.239406 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92723381 29.28% 29.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103992421 32.84% 62.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43071500 13.60% 75.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8912974 2.81% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25679598 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13104188 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7581196 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1156714 0.37% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20457759 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 92731092 29.28% 29.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104002875 32.84% 62.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43058477 13.60% 75.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8922442 2.82% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25674548 8.11% 86.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13103987 4.14% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7582493 2.39% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1154147 0.36% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20460079 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316679731 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570051714 # Number of instructions committed -system.cpu.commit.committedOps 602359921 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 316690140 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570051694 # Number of instructions committed +system.cpu.commit.committedOps 602359901 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173635 # Number of memory references committed -system.cpu.commit.loads 148952608 # Number of loads committed +system.cpu.commit.refs 219173627 # Number of memory references committed +system.cpu.commit.loads 148952604 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828615 # Number of branches committed +system.cpu.commit.branches 70828611 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522695 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20457759 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20460079 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978278405 # The number of ROB reads -system.cpu.rob.rob_writes 1375177371 # The number of ROB writes -system.cpu.timesIdled 40898 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 850586 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570051663 # Number of Instructions Simulated -system.cpu.committedOps 602359870 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570051663 # Number of Instructions Simulated -system.cpu.cpi 0.576371 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576371 # CPI: Total CPI of All Threads -system.cpu.ipc 1.734995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.734995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210435772 # number of integer regfile reads -system.cpu.int_regfile_writes 664215714 # number of integer regfile writes +system.cpu.rob.rob_reads 978265483 # The number of ROB reads +system.cpu.rob.rob_writes 1375131668 # The number of ROB writes +system.cpu.timesIdled 36876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 838550 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570051643 # Number of Instructions Simulated +system.cpu.committedOps 602359850 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570051643 # Number of Instructions Simulated +system.cpu.cpi 0.576361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.576361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.735023 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.735023 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210434144 # number of integer regfile reads +system.cpu.int_regfile_writes 664206400 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905058829 # number of misc regfile reads -system.cpu.misc_regfile_writes 2684 # number of misc regfile writes -system.cpu.icache.replacements 57 # number of replacements -system.cpu.icache.tagsinuse 691.796995 # Cycle average of tags in use -system.cpu.icache.total_refs 67496461 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 810 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83328.964198 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905030713 # number of misc regfile reads +system.cpu.misc_regfile_writes 2676 # number of misc regfile writes +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 695.805278 # Cycle average of tags in use +system.cpu.icache.total_refs 67497251 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82414.225885 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 691.796995 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.337792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.337792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67496461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67496461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67496461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67496461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67496461 # number of overall hits -system.cpu.icache.overall_hits::total 67496461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1093 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1093 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1093 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1093 # number of overall misses -system.cpu.icache.overall_misses::total 1093 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37450500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37450500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37450500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37450500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37450500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37450500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67497554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67497554 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67497554 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67497554 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67497554 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67497554 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 695.805278 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.339749 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.339749 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67497251 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67497251 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67497251 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67497251 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67497251 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37785500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67498352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67498352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67498352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67498352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67498352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67498352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34263.952425 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34263.952425 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34319.255223 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34319.255223 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,264 +387,260 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 282 system.cpu.icache.demand_mshr_hits::total 282 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 282 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 282 # 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number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27589000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27945500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27945500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27945500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27945500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27945500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27945500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34018.495684 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34018.495684 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34121.489621 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34121.489621 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 449.687300 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88231000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.647718 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999670 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 132073030 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 132073030 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 67873619 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 67873619 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1341 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1341 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 199946649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 199946649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 199946649 # number of overall hits -system.cpu.dcache.overall_hits::total 199946649 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 249332 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 249332 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543912 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 132066425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 132066425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 67860846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 67860846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1466 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1337 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1337 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 199927271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 199927271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 199927271 # number of overall hits +system.cpu.dcache.overall_hits::total 199927271 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 249429 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 249429 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1556685 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1556685 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 16 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30310392962 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30310392962 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30310392962 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132322362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132322362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1806114 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1806114 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1806114 # number of overall misses +system.cpu.dcache.overall_misses::total 1806114 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3287429500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3287429500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27038709023 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27038709023 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 163500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 163500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30326138523 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30326138523 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30326138523 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30326138523 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 132315854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 132315854 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1473 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1473 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1341 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1341 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201739893 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201739893 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201739893 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201739893 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022241 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1337 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1337 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201733385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201733385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201733385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201733385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.010796 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13179.820711 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17369.415793 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10218.750000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16790.821910 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9531023 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2243 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4284.869371 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4356.043419 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 394903 # number of writebacks -system.cpu.dcache.writebacks::total 394903 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51902 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1296808 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1296808 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 394920 # number of writebacks +system.cpu.dcache.writebacks::total 394920 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51943 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4168653962 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4168653962 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1361515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1361515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1361515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1361515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197486 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247113 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247113 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34316.703546 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.841432 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34315.779885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.841432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34315.779885 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1901500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 329 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 340 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5039.513678 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24032500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1003471000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027503500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820086500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820086500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24032500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823557500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2847590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24032500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823557500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2847590000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.953086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203742 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31130.181347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31097.059097 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.786985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31130.181347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.416805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32262 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33044 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58299 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 58299 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 90561 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 91343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 90561 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 91343 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24334000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1002753500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1820295000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1820295000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24334000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2823048500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2847382500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24334000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2823048500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2847382500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235918 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203691 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31117.647059 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.566549 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31223.434364 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31117.647059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31172.894513 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 35f1e8fcc..f06b9ec67 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 80be44c4e..f3821c915 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3224710 # Simulator instruction rate (inst/s) -host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1703801368 # Simulator tick rate (ticks/s) -host_mem_usage 212692 # Number of bytes of host memory used -host_seconds 176.78 # Real time elapsed on the host +host_inst_rate 3323130 # Simulator instruction rate (inst/s) +host_op_rate 3511472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1755802369 # Simulator tick rate (ticks/s) +host_mem_usage 216428 # Number of bytes of host memory used +host_seconds 171.54 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2680160157 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 602359851 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index ce56af1f4..14843a60a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 4b6f6b404..52945d306 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1806630 # Simulator instruction rate (inst/s) -host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2531848956 # Simulator tick rate (ticks/s) -host_mem_usage 221588 # Number of bytes of host memory used -host_seconds 314.70 # Real time elapsed on the host +host_inst_rate 1880906 # Simulator instruction rate (inst/s) +host_op_rate 1986306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2635941289 # Simulator tick rate (ticks/s) +host_mem_usage 225340 # Number of bytes of host memory used +host_seconds 302.27 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated system.physmem.bytes_read 5759488 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 600398281 # Nu system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67018854 # number of instructions that are conditional controls system.cpu.num_int_insts 533522639 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read |